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Unified Diff: src/s390/assembler-s390.h

Issue 2685733002: S390: Use macro to declare rxy format assember function (Closed)
Patch Set: Use static cast for casting integer to Condition Created 3 years, 10 months ago
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Index: src/s390/assembler-s390.h
diff --git a/src/s390/assembler-s390.h b/src/s390/assembler-s390.h
index 64da50f2b3610491302b4a014f1980c135928723..2d27a9a26c326ae0b61740f125242da92316389c 100644
--- a/src/s390/assembler-s390.h
+++ b/src/s390/assembler-s390.h
@@ -733,6 +733,39 @@ class Assembler : public AssemblerBase {
}
#undef DECLARE_S390_RX_INSTRUCTIONS
+#define DECLARE_S390_RXY_INSTRUCTIONS(name, op_name, op_value) \
+ template <class R1, class R2> \
+ inline void name(R1 r1, R2 r2, Register b2, Disp d2) { \
+ rxy_format(op_name, r1.code(), r2.code(), b2.code(), d2); \
+ } \
+ template <class R1> \
+ inline void name(R1 r1, const MemOperand& opnd) { \
+ name(r1, opnd.getIndexRegister(), \
+ opnd.getBaseRegister(), opnd.getDisplacement()); \
+ }
+
+ inline void rxy_format(Opcode opcode, int f1, int f2, int f3, int f4) {
+ DCHECK(is_uint16(opcode));
+ DCHECK(is_int20(f4));
+ emit6bytes(getfield<uint64_t, 6, 0, 8>(opcode >> 8) |
+ getfield<uint64_t, 6, 8, 12>(f1) |
+ getfield<uint64_t, 6, 12, 16>(f2) |
+ getfield<uint64_t, 6, 16, 20>(f3) |
+ getfield<uint64_t, 6, 20, 32>(f4 & 0x0fff) |
+ getfield<uint64_t, 6, 32, 40>(f4 >> 12) |
+ getfield<uint64_t, 6, 40, 48>(opcode & 0x00ff));
+ }
+ S390_RXY_A_OPCODE_LIST(DECLARE_S390_RXY_INSTRUCTIONS)
+
+ void pfd(Condition cond, const MemOperand& opnd) {
+ pfd(cond, opnd.getIndexRegister(),
+ opnd.getBaseRegister(), opnd.getDisplacement());
+ }
+ void pfd(Condition cond, Register x2, Register b2, Disp d2) {
+ rxy_format(PFD, cond, x2.code(), b2.code(), d2);
+ }
+#undef DECLARE_S390_RXY_INSTRUCTIONS
+
// Helper for unconditional branch to Label with update to save register
void b(Register r, Label* l) {
int32_t halfwords = branch_offset(l) / 2;
@@ -839,10 +872,6 @@ class Assembler : public AssemblerBase {
void name(Register r1, Register r3, const MemOperand& opnd); \
void name(Register r1, Register r3, Register b2, Register x2, Disp d2)
-#define RXY_FORM(name) \
- void name(Register r1, Register x2, Register b2, Disp d2); \
- void name(Register r1, const MemOperand& opnd)
-
#define RSI_FORM(name) void name(Register r1, Register r3, const Operand& i)
#define RIS_FORM(name) \
@@ -989,16 +1018,11 @@ class Assembler : public AssemblerBase {
RXE_FORM(ddb);
SS1_FORM(ed);
RRF2_FORM(fidbr);
- RXY_FORM(icy);
RI1_FORM(iihh);
RI1_FORM(iihl);
RI1_FORM(iilh);
RI1_FORM(iill);
- RXY_FORM(ley);
RSY1_FORM(loc);
- RXY_FORM(lrv);
- RXY_FORM(lrvh);
- RXY_FORM(lrvg);
RXE_FORM(mdb);
SS4_FORM(mvck);
SSF_FORM(mvcos);
@@ -1009,47 +1033,19 @@ class Assembler : public AssemblerBase {
RI1_FORM(nilh);
RI1_FORM(nill);
RI1_FORM(oill);
- RXY_FORM(pfd);
- RXY_FORM(dsgf);
- RXY_FORM(msgf);
- RXY_FORM(dsg);
RXE_FORM(sdb);
- RXY_FORM(slgf);
RS1_FORM(srdl);
- RXY_FORM(stey);
- RXY_FORM(strv);
- RXY_FORM(strvh);
- RXY_FORM(strvg);
RI1_FORM(tmll);
SS1_FORM(tr);
S_FORM(ts);
// Load Address Instructions
- void lay(Register r, const MemOperand& opnd);
void larl(Register r, Label* l);
// Load Instructions
- void lb(Register r, const MemOperand& src);
- void lgb(Register r, const MemOperand& src);
- void lhy(Register r, const MemOperand& src);
- void lgh(Register r, const MemOperand& src);
- void ly(Register r, const MemOperand& src);
- void lg(Register r, const MemOperand& src);
- void lgf(Register r, const MemOperand& src);
void lhi(Register r, const Operand& imm);
void lghi(Register r, const Operand& imm);
- // Load And Test Instructions
- void lt_z(Register r, const MemOperand& src);
- void ltg(Register r, const MemOperand& src);
-
- // Load Logical Instructions
- void llc(Register r, const MemOperand& src);
- void llgc(Register r, const MemOperand& src);
- void llgf(Register r, const MemOperand& src);
- void llh(Register r, const MemOperand& src);
- void llgh(Register r, const MemOperand& src);
-
// Load Multiple Instructions
void lm(Register r1, Register r2, const MemOperand& src);
void lmy(Register r1, Register r2, const MemOperand& src);
@@ -1062,10 +1058,6 @@ class Assembler : public AssemblerBase {
void locg(Condition m3, Register r1, const MemOperand& src);
// Store Instructions
- void stcy(Register r, const MemOperand& src);
- void stg(Register r, const MemOperand& src);
- void sthy(Register r, const MemOperand& src);
- void sty(Register r, const MemOperand& src);
// Store Multiple Instructions
void stm(Register r1, Register r2, const MemOperand& src);
@@ -1073,15 +1065,10 @@ class Assembler : public AssemblerBase {
void stmg(Register r1, Register r2, const MemOperand& src);
// Compare Instructions
- void cy(Register r, const MemOperand& opnd);
- void cg(Register r, const MemOperand& opnd);
- void chy(Register r, const MemOperand& opnd);
void chi(Register r, const Operand& opnd);
void cghi(Register r, const Operand& opnd);
// Compare Logical Instructions
- void cly(Register r, const MemOperand& opnd);
- void clg(Register r, const MemOperand& opnd);
void cli(const MemOperand& mem, const Operand& imm);
void cliy(const MemOperand& mem, const Operand& imm);
void clc(const MemOperand& opnd1, const MemOperand& opnd2, Length length);
@@ -1143,90 +1130,56 @@ class Assembler : public AssemblerBase {
void mvc(const MemOperand& opnd1, const MemOperand& opnd2, uint32_t length);
// Branch Instructions
- void bctg(Register r, const MemOperand& opnd);
void bras(Register r, const Operand& opnd);
void brc(Condition c, const Operand& opnd);
void brct(Register r1, const Operand& opnd);
void brctg(Register r1, const Operand& opnd);
// 32-bit Add Instructions
- void ay(Register r1, const MemOperand& opnd);
- void ahy(Register r1, const MemOperand& opnd);
void ahi(Register r1, const Operand& opnd);
void ahik(Register r1, Register r3, const Operand& opnd);
void ark(Register r1, Register r2, Register r3);
void asi(const MemOperand&, const Operand&);
// 64-bit Add Instructions
- void ag(Register r1, const MemOperand& opnd);
- void agf(Register r1, const MemOperand& opnd);
void aghi(Register r1, const Operand& opnd);
void aghik(Register r1, Register r3, const Operand& opnd);
void agrk(Register r1, Register r2, Register r3);
void agsi(const MemOperand&, const Operand&);
// 32-bit Add Logical Instructions
- void aly(Register r1, const MemOperand& opnd);
void alrk(Register r1, Register r2, Register r3);
// 64-bit Add Logical Instructions
- void alg(Register r1, const MemOperand& opnd);
void algrk(Register r1, Register r2, Register r3);
// 32-bit Subtract Instructions
- void sy(Register r1, const MemOperand& opnd);
- void shy(Register r1, const MemOperand& opnd);
void srk(Register r1, Register r2, Register r3);
// 64-bit Subtract Instructions
- void sg(Register r1, const MemOperand& opnd);
- void sgf(Register r1, const MemOperand& opnd);
void sgrk(Register r1, Register r2, Register r3);
// 32-bit Subtract Logical Instructions
- void sly(Register r1, const MemOperand& opnd);
void slrk(Register r1, Register r2, Register r3);
// 64-bit Subtract Logical Instructions
- void slg(Register r1, const MemOperand& opnd);
void slgrk(Register r1, Register r2, Register r3);
// 32-bit Multiply Instructions
- void mfy(Register r1, const MemOperand& opnd);
- void ml(Register r1, const MemOperand& opnd);
- void msy(Register r1, const MemOperand& opnd);
- void mhy(Register r1, const MemOperand& opnd);
void mhi(Register r1, const Operand& opnd);
// 64-bit Multiply Instructions
- void mlg(Register r1, const MemOperand& opnd);
void mghi(Register r1, const Operand& opnd);
- void msg(Register r1, const MemOperand& opnd);
-
- // 32-bit Divide Instructions
- void dl(Register r1, const MemOperand& opnd);
// Bitwise Instructions (AND / OR / XOR)
- void ny(Register r1, const MemOperand& opnd);
void nrk(Register r1, Register r2, Register r3);
- void ng(Register r1, const MemOperand& opnd);
void ngrk(Register r1, Register r2, Register r3);
- void oy(Register r1, const MemOperand& opnd);
void ork(Register r1, Register r2, Register r3);
- void og(Register r1, const MemOperand& opnd);
void ogrk(Register r1, Register r2, Register r3);
- void xy(Register r1, const MemOperand& opnd);
void xrk(Register r1, Register r2, Register r3);
- void xg(Register r1, const MemOperand& opnd);
void xgrk(Register r1, Register r2, Register r3);
void xc(const MemOperand& opnd1, const MemOperand& opnd2, Length length);
- // Floating Point Load / Store Instructions
- void ldy(DoubleRegister r1, const MemOperand& opnd);
- void ley(DoubleRegister r1, const MemOperand& opnd);
- void stdy(DoubleRegister r1, const MemOperand& opnd);
- void stey(DoubleRegister r1, const MemOperand& opnd);
-
// Floating <-> Fixed Point Conversion Instructions
void cdlfbr(Condition m3, Condition m4, DoubleRegister fltReg,
Register fixReg);
@@ -1482,13 +1435,6 @@ class Assembler : public AssemblerBase {
inline void rxf_form(Opcode op, Register r1, Register r3, Register b2,
Register x2, Disp d2);
- inline void rxy_form(Opcode op, Register r1, Register x2, Register b2,
- Disp d2);
- inline void rxy_form(Opcode op, Register r1, Condition m3, Register b2,
- Disp d2);
- inline void rxy_form(Opcode op, DoubleRegister r1, Register x2, Register b2,
- Disp d2);
-
inline void s_form(Opcode op, Register b1, Disp d2);
inline void si_form(Opcode op, const Operand& i2, Register b1, Disp d1);
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