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Side by Side Diff: src/arm64/assembler-arm64-inl.h

Issue 268483002: ARM64: Sign extension on MemOperand for keyed ops (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 6 years, 7 months ago
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1 // Copyright 2013 the V8 project authors. All rights reserved. 1 // Copyright 2013 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_ARM64_ASSEMBLER_ARM64_INL_H_ 5 #ifndef V8_ARM64_ASSEMBLER_ARM64_INL_H_
6 #define V8_ARM64_ASSEMBLER_ARM64_INL_H_ 6 #define V8_ARM64_ASSEMBLER_ARM64_INL_H_
7 7
8 #include "arm64/assembler-arm64.h" 8 #include "arm64/assembler-arm64.h"
9 #include "cpu.h" 9 #include "cpu.h"
10 #include "debug.h" 10 #include "debug.h"
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404 ASSERT((scale >= 0) && (scale <= (64 - kSmiValueSize))); 404 ASSERT((scale >= 0) && (scale <= (64 - kSmiValueSize)));
405 if (scale > kSmiShift) { 405 if (scale > kSmiShift) {
406 return Operand(smi, LSL, scale - kSmiShift); 406 return Operand(smi, LSL, scale - kSmiShift);
407 } else if (scale < kSmiShift) { 407 } else if (scale < kSmiShift) {
408 return Operand(smi, ASR, kSmiShift - scale); 408 return Operand(smi, ASR, kSmiShift - scale);
409 } 409 }
410 return Operand(smi); 410 return Operand(smi);
411 } 411 }
412 412
413 413
414 MemOperand::MemOperand()
415 : base_(NoReg), regoffset_(NoReg), offset_(0), addrmode_(Offset),
416 shift_(NO_SHIFT), extend_(NO_EXTEND), shift_amount_(0) {
417 }
418
419
414 MemOperand::MemOperand(Register base, ptrdiff_t offset, AddrMode addrmode) 420 MemOperand::MemOperand(Register base, ptrdiff_t offset, AddrMode addrmode)
415 : base_(base), regoffset_(NoReg), offset_(offset), addrmode_(addrmode), 421 : base_(base), regoffset_(NoReg), offset_(offset), addrmode_(addrmode),
416 shift_(NO_SHIFT), extend_(NO_EXTEND), shift_amount_(0) { 422 shift_(NO_SHIFT), extend_(NO_EXTEND), shift_amount_(0) {
417 ASSERT(base.Is64Bits() && !base.IsZero()); 423 ASSERT(base.Is64Bits() && !base.IsZero());
418 } 424 }
419 425
420 426
421 MemOperand::MemOperand(Register base, 427 MemOperand::MemOperand(Register base,
422 Register regoffset, 428 Register regoffset,
423 Extend extend, 429 Extend extend,
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1198 1204
1199 1205
1200 void Assembler::ClearRecordedAstId() { 1206 void Assembler::ClearRecordedAstId() {
1201 recorded_ast_id_ = TypeFeedbackId::None(); 1207 recorded_ast_id_ = TypeFeedbackId::None();
1202 } 1208 }
1203 1209
1204 1210
1205 } } // namespace v8::internal 1211 } } // namespace v8::internal
1206 1212
1207 #endif // V8_ARM64_ASSEMBLER_ARM64_INL_H_ 1213 #endif // V8_ARM64_ASSEMBLER_ARM64_INL_H_
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