[Turbofan] Add more non-arithmetic SIMD operations.

src/compiler/arm/instruction-selector-arm.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/base/adapters.h"
 #include "src/base/bits.h"
 #include "src/compiler/instruction-selector-impl.h"
 #include "src/compiler/node-matchers.h"
 #include "src/compiler/node-properties.h"
 
@@ skipping 74 matching lines @@
 }
 
 
 void VisitRRR(InstructionSelector* selector, ArchOpcode opcode, Node* node) {
   ArmOperandGenerator g(selector);
   selector->Emit(opcode, g.DefineAsRegister(node),
                  g.UseRegister(node->InputAt(0)),
                  g.UseRegister(node->InputAt(1)));
 }
 
+void VisitRRRR(InstructionSelector* selector, ArchOpcode opcode, Node* node) {
+  ArmOperandGenerator g(selector);
+  selector->Emit(
+      opcode, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
+      g.UseRegister(node->InputAt(1)), g.UseRegister(node->InputAt(2)));
+}
+
 void VisitRRI(InstructionSelector* selector, ArchOpcode opcode, Node* node) {
   ArmOperandGenerator g(selector);
   int32_t imm = OpParameter<int32_t>(node);
   selector->Emit(opcode, g.DefineAsRegister(node),
                  g.UseRegister(node->InputAt(0)), g.UseImmediate(imm));
 }
 
 void VisitRRIR(InstructionSelector* selector, ArchOpcode opcode, Node* node) {
   ArmOperandGenerator g(selector);
   int32_t imm = OpParameter<int32_t>(node);
@@ skipping 2055 matching lines @@
   InstructionCode code = opcode | AddressingModeField::encode(addressing_mode);
   Emit(code, 0, nullptr, input_count, inputs);
 }
 
 #define SIMD_TYPE_LIST(V) \
   V(Float32x4)            \
   V(Int32x4)              \
   V(Int16x8)              \
   V(Int8x16)
 
+#define SIMD_FORMAT_LIST(V) \
+  V(32x4)                   \
+  V(16x8)                   \
+  V(8x16)
+
 #define SIMD_UNOP_LIST(V)  \
   V(Float32x4FromInt32x4)  \
   V(Float32x4FromUint32x4) \
   V(Float32x4Abs)          \
   V(Float32x4Neg)          \
   V(Int32x4FromFloat32x4)  \
   V(Uint32x4FromFloat32x4) \
   V(Int32x4Neg)            \
   V(Int16x8Neg)            \
-  V(Int8x16Neg)
+  V(Int8x16Neg)            \
+  V(Simd128Not)
 
 #define SIMD_BINOP_LIST(V)      \
   V(Float32x4Add)               \
   V(Float32x4Sub)               \
   V(Float32x4Equal)             \
   V(Float32x4NotEqual)          \
   V(Int32x4Add)                 \
   V(Int32x4Sub)                 \
   V(Int32x4Mul)                 \
   V(Int32x4Min)                 \
@@ skipping 32 matching lines @@
   V(Int8x16Max)                 \
   V(Int8x16Equal)               \
   V(Int8x16NotEqual)            \
   V(Int8x16GreaterThan)         \
   V(Int8x16GreaterThanOrEqual)  \
   V(Uint8x16AddSaturate)        \
   V(Uint8x16SubSaturate)        \
   V(Uint8x16Min)                \
   V(Uint8x16Max)                \
   V(Uint8x16GreaterThan)        \
-  V(Uint8x16GreaterThanOrEqual)
+  V(Uint8x16GreaterThanOrEqual) \
+  V(Simd128And)                 \
+  V(Simd128Or)                  \
+  V(Simd128Xor)
 
 #define SIMD_SHIFT_OP_LIST(V)   \
   V(Int32x4ShiftLeftByScalar)   \
   V(Int32x4ShiftRightByScalar)  \
   V(Uint32x4ShiftRightByScalar) \
   V(Int16x8ShiftLeftByScalar)   \
   V(Int16x8ShiftRightByScalar)  \
   V(Uint16x8ShiftRightByScalar) \
   V(Int8x16ShiftLeftByScalar)   \
   V(Int8x16ShiftRightByScalar)  \
@@ skipping 34 matching lines @@
 SIMD_BINOP_LIST(SIMD_VISIT_BINOP)
 #undef SIMD_VISIT_BINOP
 
 #define SIMD_VISIT_SHIFT_OP(Name)                     \
   void InstructionSelector::Visit##Name(Node* node) { \
     VisitRRI(this, kArm##Name, node);                 \
   }
 SIMD_SHIFT_OP_LIST(SIMD_VISIT_SHIFT_OP)
 #undef SIMD_VISIT_SHIFT_OP
 
-void InstructionSelector::VisitSimd32x4Select(Node* node) {
-  ArmOperandGenerator g(this);
-  Emit(kArmSimd32x4Select, g.DefineAsRegister(node),
-       g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)),
-       g.UseRegister(node->InputAt(2)));
-}
+#define SIMD_VISIT_SELECT_OP(format)                                \
+  void InstructionSelector::VisitSimd##format##Select(Node* node) { \
+    VisitRRRR(this, kArmSimd##format##Select, node);                \
+  }
+SIMD_FORMAT_LIST(SIMD_VISIT_SELECT_OP)
+#undef SIMD_VISIT_SELECT_OP
 
 // static
 MachineOperatorBuilder::Flags
 InstructionSelector::SupportedMachineOperatorFlags() {
   MachineOperatorBuilder::Flags flags;
   if (CpuFeatures::IsSupported(SUDIV)) {
     // The sdiv and udiv instructions correctly return 0 if the divisor is 0,
     // but the fall-back implementation does not.
     flags |= MachineOperatorBuilder::kInt32DivIsSafe |
              MachineOperatorBuilder::kUint32DivIsSafe;
@@ skipping 21 matching lines @@
   Vector<MachineType> req_aligned = Vector<MachineType>::New(2);
   req_aligned[0] = MachineType::Float32();
   req_aligned[1] = MachineType::Float64();
   return MachineOperatorBuilder::AlignmentRequirements::
       SomeUnalignedAccessUnsupported(req_aligned, req_aligned);
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8