[Turbofan] Add more non-arithmetic SIMD operations.

src/compiler/arm/instruction-codes-arm.h

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
 
 namespace v8 {
 namespace internal {
 namespace compiler {
@@ skipping 135 matching lines @@
   V(ArmInt32x4Max)                 \
   V(ArmInt32x4Equal)               \
   V(ArmInt32x4NotEqual)            \
   V(ArmInt32x4GreaterThan)         \
   V(ArmInt32x4GreaterThanOrEqual)  \
   V(ArmUint32x4ShiftRightByScalar) \
   V(ArmUint32x4Min)                \
   V(ArmUint32x4Max)                \
   V(ArmUint32x4GreaterThan)        \
   V(ArmUint32x4GreaterThanOrEqual) \
-  V(ArmSimd32x4Select)             \
   V(ArmInt16x8Splat)               \
   V(ArmInt16x8ExtractLane)         \
   V(ArmInt16x8ReplaceLane)         \
   V(ArmInt16x8Neg)                 \
   V(ArmInt16x8ShiftLeftByScalar)   \
   V(ArmInt16x8ShiftRightByScalar)  \
   V(ArmInt16x8Add)                 \
   V(ArmInt16x8AddSaturate)         \
   V(ArmInt16x8Sub)                 \
   V(ArmInt16x8SubSaturate)         \
@@ skipping 27 matching lines @@
   V(ArmInt8x16Equal)               \
   V(ArmInt8x16NotEqual)            \
   V(ArmInt8x16GreaterThan)         \
   V(ArmInt8x16GreaterThanOrEqual)  \
   V(ArmUint8x16ShiftRightByScalar) \
   V(ArmUint8x16AddSaturate)        \
   V(ArmUint8x16SubSaturate)        \
   V(ArmUint8x16Min)                \
   V(ArmUint8x16Max)                \
   V(ArmUint8x16GreaterThan)        \
-  V(ArmUint8x16GreaterThanOrEqual)
+  V(ArmUint8x16GreaterThanOrEqual) \
+  V(ArmSimd128And)                 \
+  V(ArmSimd128Or)                  \
+  V(ArmSimd128Xor)                 \
+  V(ArmSimd128Not)                 \
+  V(ArmSimd32x4Select)             \
+  V(ArmSimd16x8Select)             \
+  V(ArmSimd8x16Select)
 
 // Addressing modes represent the "shape" of inputs to an instruction.
 // Many instructions support multiple addressing modes. Addressing modes
 // are encoded into the InstructionCode of the instruction and tell the
 // code generator after register allocation which assembler method to call.
 #define TARGET_ADDRESSING_MODE_LIST(V)  \
   V(Offset_RI)        /* [%r0 + K] */   \
   V(Offset_RR)        /* [%r0 + %r1] */ \
   V(Operand2_I)       /* K */           \
   V(Operand2_R)       /* %r0 */         \
   V(Operand2_R_ASR_I) /* %r0 ASR K */   \
   V(Operand2_R_LSL_I) /* %r0 LSL K */   \
   V(Operand2_R_LSR_I) /* %r0 LSR K */   \
   V(Operand2_R_ROR_I) /* %r0 ROR K */   \
   V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \
   V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \
   V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \
   V(Operand2_R_ROR_R) /* %r0 ROR %r1 */
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_