[SubZero] Generate spin-lock for atomic load store

tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll

 ; This tests each of the supported NaCl atomic instructions for every
 ; size allowed.
 
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
 ; RUN:   -allow-externally-defined-symbols | FileCheck %s
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
 ; RUN:   -allow-externally-defined-symbols | FileCheck --check-prefix=O2 %s
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
 ; RUN:   -allow-externally-defined-symbols | FileCheck %s
 
@@ skipping 71 matching lines @@
   %r = zext i8 %i2 to i32
   ret i32 %r
 }
 ; CHECK-LABEL: test_atomic_load_8
 ; CHECK: mov {{.*}},DWORD
 ; CHECK: mov {{.*}},BYTE
 ; ARM32-LABEL: test_atomic_load_8
 ; ARM32: ldrb r{{[0-9]+}}, [r{{[0-9]+}}
 ; ARM32: dmb
 ; MIPS32-LABEL: test_atomic_load_8
-; MIPS32: lb
+; MIPS32: sync
+; MIPS32: ll
+; MIPS32: sc
 ; MIPS32: sync
 
 define internal i32 @test_atomic_load_16(i32 %iptr) {
 entry:
   %ptr = inttoptr i32 %iptr to i16*
   %i = call i16 @llvm.nacl.atomic.load.i16(i16* %ptr, i32 6)
   %i2 = sub i16 %i, 0
   %r = zext i16 %i2 to i32
   ret i32 %r
 }
 ; CHECK-LABEL: test_atomic_load_16
 ; CHECK: mov {{.*}},DWORD
 ; CHECK: mov {{.*}},WORD
 ; ARM32-LABEL: test_atomic_load_16
 ; ARM32: ldrh r{{[0-9]+}}, [r{{[0-9]+}}
 ; ARM32: dmb
 ; MIPS32-LABEL: test_atomic_load_16
-; MIPS32: lh
+; MIPS32: sync
+; MIPS32: ll
+; MIPS32: sc
 ; MIPS32: sync
 
 define internal i32 @test_atomic_load_32(i32 %iptr) {
 entry:
   %ptr = inttoptr i32 %iptr to i32*
   %r = call i32 @llvm.nacl.atomic.load.i32(i32* %ptr, i32 6)
   ret i32 %r
 }
 ; CHECK-LABEL: test_atomic_load_32
 ; CHECK: mov {{.*}},DWORD
 ; CHECK: mov {{.*}},DWORD
 ; ARM32-LABEL: test_atomic_load_32
 ; ARM32: ldr r{{[0-9]+}}, [r{{[0-9]+}}
 ; ARM32: dmb
 ; MIPS32-LABEL: test_atomic_load_32
-; MIPS32: lw
+; MIPS32: sync
+; MIPS32: ll
+; MIPS32: sc
 ; MIPS32: sync
 
 define internal i64 @test_atomic_load_64(i32 %iptr) {
 entry:
   %ptr = inttoptr i32 %iptr to i64*
   %r = call i64 @llvm.nacl.atomic.load.i64(i64* %ptr, i32 6)
   ret i64 %r
 }
 ; CHECK-LABEL: test_atomic_load_64
 ; CHECK: movq x{{.*}},QWORD
 ; CHECK: movq QWORD {{.*}},x{{.*}}
 ; ARM32-LABEL: test_atomic_load_64
 ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}
 ; ARM32: dmb
 ; MIPS32-LABEL: test_atomic_load_64
-; MIPS32: lw
-; MIPS32: lw
+; MIPS32: jal __sync_val_compare_and_swap_8
 ; MIPS32: sync
 
 define internal i32 @test_atomic_load_32_with_arith(i32 %iptr) {
 entry:
   br label %next
 
 next:
   %ptr = inttoptr i32 %iptr to i32*
   %r = call i32 @llvm.nacl.atomic.load.i32(i32* %ptr, i32 6)
   %r2 = sub i32 32, %r
   ret i32 %r2
 }
 ; CHECK-LABEL: test_atomic_load_32_with_arith
 ; CHECK: mov {{.*}},DWORD
 ; The next instruction may be a separate load or folded into an add.
 ;
 ; In O2 mode, we know that the load and sub are going to be fused.
 ; O2-LABEL: test_atomic_load_32_with_arith
 ; O2: mov {{.*}},DWORD
 ; O2: sub {{.*}},DWORD
 ; ARM32-LABEL: test_atomic_load_32_with_arith
 ; ARM32: ldr r{{[0-9]+}}, [r{{[0-9]+}}
 ; ARM32: dmb
 ; MIPS32-LABEL: test_atomic_load_32_with_arith
-; MIPS32: lw
 ; MIPS32: sync
+; MIPS32: ll
+; MIPS32: sc
+; MIPS32: sync
+; MIPS32: subu
 
 define internal i32 @test_atomic_load_32_ignored(i32 %iptr) {
 entry:
   %ptr = inttoptr i32 %iptr to i32*
   %ignored = call i32 @llvm.nacl.atomic.load.i32(i32* %ptr, i32 6)
   ret i32 0
 }
 ; CHECK-LABEL: test_atomic_load_32_ignored
 ; CHECK: mov {{.*}},DWORD
 ; CHECK: mov {{.*}},DWORD
 ; O2-LABEL: test_atomic_load_32_ignored
 ; O2: mov {{.*}},DWORD
 ; O2: mov {{.*}},DWORD
 ; ARM32-LABEL: test_atomic_load_32_ignored
 ; ARM32: ldr r{{[0-9]+}}, [r{{[0-9]+}}
 ; ARM32: dmb
 ; MIPS32-LABEL: test_atomic_load_32_ignored
-; MIPS32: lw
+; MIPS32: sync
+; MIPS32: ll
+; MIPS32: sc
 ; MIPS32: sync
 
 define internal i64 @test_atomic_load_64_ignored(i32 %iptr) {
 entry:
   %ptr = inttoptr i32 %iptr to i64*
   %ignored = call i64 @llvm.nacl.atomic.load.i64(i64* %ptr, i32 6)
   ret i64 0
 }
 ; CHECK-LABEL: test_atomic_load_64_ignored
 ; CHECK: movq x{{.*}},QWORD
 ; CHECK: movq QWORD {{.*}},x{{.*}}
 ; ARM32-LABEL: test_atomic_load_64_ignored
 ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}
 ; ARM32: dmb
 ; MIPS32-LABEL: test_atomic_load_64_ignored
-; MIPS32: lw
-; MIPS32: lw
+; MIPS32: jal   __sync_val_compare_and_swap_8
 ; MIPS32: sync
 
 ;;; Store
 
 define internal void @test_atomic_store_8(i32 %iptr, i32 %v) {
 entry:
   %truncv = trunc i32 %v to i8
   %ptr = inttoptr i32 %iptr to i8*
   call void @llvm.nacl.atomic.store.i8(i8 %truncv, i8* %ptr, i32 6)
   ret void
 }
 ; CHECK-LABEL: test_atomic_store_8
 ; CHECK: mov BYTE
 ; CHECK: mfence
 ; ARM32-LABEL: test_atomic_store_8
 ; ARM32: dmb
 ; ARM32: strb r{{[0-9]+}}, [r{{[0-9]+}}
 ; ARM32: dmb
 ; MIPS32-LABEL: test_atomic_store_8
 ; MIPS32: sync
-; MIPS32: sb
+; MIPS32: ll
+; MIPS32: sc
 ; MIPS32: sync
 
 define internal void @test_atomic_store_16(i32 %iptr, i32 %v) {
 entry:
   %truncv = trunc i32 %v to i16
   %ptr = inttoptr i32 %iptr to i16*
   call void @llvm.nacl.atomic.store.i16(i16 %truncv, i16* %ptr, i32 6)
   ret void
 }
 ; CHECK-LABEL: test_atomic_store_16
 ; CHECK: mov WORD
 ; CHECK: mfence
 ; ARM32-LABEL: test_atomic_store_16
 ; ARM32: dmb
 ; ARM32: strh r{{[0-9]+}}, [r{{[0-9]+}}
 ; ARM32: dmb
 ; MIPS32-LABEL: test_atomic_store_16
 ; MIPS32: sync
-; MIPS32: sh
+; MIPS32: ll
+; MIPS32: sc
 ; MIPS32: sync
 
 define internal void @test_atomic_store_32(i32 %iptr, i32 %v) {
 entry:
   %ptr = inttoptr i32 %iptr to i32*
   call void @llvm.nacl.atomic.store.i32(i32 %v, i32* %ptr, i32 6)
   ret void
 }
 ; CHECK-LABEL: test_atomic_store_32
 ; CHECK: mov DWORD
 ; CHECK: mfence
 ; ARM32-LABEL: test_atomic_store_32
 ; ARM32: dmb
 ; ARM32: str r{{[0-9]+}}, [r{{[0-9]+}}
 ; ARM32: dmb
 ; MIPS32-LABEL: test_atomic_store_32
 ; MIPS32: sync
-; MIPS32: sw
+; MIPS32: ll
+; MIPS32: sc
 ; MIPS32: sync
 
 define internal void @test_atomic_store_64(i32 %iptr, i64 %v) {
 entry:
   %ptr = inttoptr i32 %iptr to i64*
   call void @llvm.nacl.atomic.store.i64(i64 %v, i64* %ptr, i32 6)
   ret void
 }
 ; CHECK-LABEL: test_atomic_store_64
 ; CHECK: movq x{{.*}},QWORD
 ; CHECK: movq QWORD {{.*}},x{{.*}}
 ; CHECK: mfence
 ; ARM32-LABEL: test_atomic_store_64
 ; ARM32: dmb
 ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [[MEM:.*]]
 ; ARM32: strexd [[S:r[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}}, [[MEM]]
 ; ARM32: cmp [[S]], #0
 ; ARM32: bne
 ; ARM32: dmb
 ; MIPS32-LABEL: test_atomic_store_64
 ; MIPS32: sync
-; MIPS32: sw
-; MIPS32: sw
+; MIPS32: jal   __sync_lock_test_and_set_8
 ; MIPS32: sync
 
 define internal void @test_atomic_store_64_const(i32 %iptr) {
 entry:
   %ptr = inttoptr i32 %iptr to i64*
   call void @llvm.nacl.atomic.store.i64(i64 12345678901234, i64* %ptr, i32 6)
   ret void
 }
 ; CHECK-LABEL: test_atomic_store_64_const
 ; CHECK: mov {{.*}},0x73ce2ff2
@@ skipping 10 matching lines @@
 ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [[MEM:.*]]
 ; ARM32: strexd [[S:r[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}}, [[MEM]]
 ; ARM32: cmp [[S]], #0
 ; ARM32: bne .L[[RETRY]]
 ; ARM32: dmb
 ; MIPS32-LABEL: test_atomic_store_64_const
 ; MIPS32: sync
 ; MIPS32: lui   {{.*}}, 29646
 ; MIPS32: ori   {{.*}},{{.*}}, 12274
 ; MIPS32: addiu {{.*}}, $zero, 2874
-; MIPS32: sw
-; MIPS32: sw
+; MIPS32: jal   __sync_lock_test_and_set_8
 ; MIPS32: sync
 
 ;;; RMW
 
 ;; add
 
 define internal i32 @test_atomic_rmw_add_8(i32 %iptr, i32 %v) {
 entry:
   %trunc = trunc i32 %v to i8
   %ptr = inttoptr i32 %iptr to i8*
@@ skipping 124 matching lines @@
 ; ARM32-LABEL: test_atomic_rmw_add_64
 ; ARM32: dmb
 ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: adds
 ; ARM32: adc
 ; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: bne
 ; ARM32: dmb
 ; MIPS32-LABEL: test_atomic_rmw_add_64
 ; MIPS32: sync
-; MIPS32: ll
-; MIPS32: addu
-; MIPS32: sltu
-; MIPS32: sc
-; MIPS32: beq   {{.*}}, $zero, {{.*}}
-; MIPS32: ll
-; MIPS32: addu
-; MIPS32: addu
-; MIPS32: sc
-; MIPS32: beq   {{.*}}, $zero, {{.*}}
+; MIPS32: jal   __sync_fetch_and_add_8
 ; MIPS32: sync
 
 ; Same test as above, but with a global address to test FakeUse issues.
 define internal i64 @test_atomic_rmw_add_64_global(i64 %v) {
 entry:
   %ptr = bitcast [8 x i8]* @SzGlobal64 to i64*
   %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 1, i64* %ptr, i64 %v, i32 6)
   ret i64 %a
 }
 ; CHECK-LABEL: test_atomic_rmw_add_64_global
 ; ARM32-LABEL: test_atomic_rmw_add_64_global
 ; ARM32: dmb
 ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: adds
 ; ARM32: adc
 ; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: bne
 ; ARM32: dmb
 ; MIPS32-LABEL: test_atomic_rmw_add_64_global
 ; MIPS32: sync
-; MIPS32: ll
-; MIPS32: addu
-; MIPS32: sltu
-; MIPS32: sc
-; MIPS32: beq   {{.*}}, $zero, {{.*}}
-; MIPS32: ll
-; MIPS32: addu
-; MIPS32: addu
-; MIPS32: sc
-; MIPS32: beq   {{.*}}, $zero, {{.*}}
+; MIPS32: jal   __sync_fetch_and_add_8
 ; MIPS32: sync
 
 ; Test with some more register pressure. When we have an alloca, ebp is
 ; used to manage the stack frame, so it cannot be used as a register either.
 declare void @use_ptr(i32 %iptr)
 
 define internal i64 @test_atomic_rmw_add_64_alloca(i32 %iptr, i64 %v) {
 entry:
   br label %eblock  ; Disable alloca optimization
 eblock:
@@ skipping 24 matching lines @@
 ; ARM32-LABEL: test_atomic_rmw_add_64_alloca
 ; ARM32: dmb
 ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: adds
 ; ARM32: adc
 ; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: bne
 ; ARM32: dmb
 ; MIPS32-LABEL: test_atomic_rmw_add_64_alloca
 ; MIPS32: sync
-; MIPS32: ll
-; MIPS32: addu
-; MIPS32: sltu
-; MIPS32: sc
-; MIPS32: beq   {{.*}}, $zero, {{.*}}
-; MIPS32: ll
-; MIPS32: addu
-; MIPS32: addu
-; MIPS32: sc
-; MIPS32: beq   {{.*}}, $zero, {{.*}}
+; MIPS32: jal   __sync_fetch_and_add_8
 ; MIPS32: sync
 
 define internal i32 @test_atomic_rmw_add_32_ignored(i32 %iptr, i32 %v) {
 entry:
   %ptr = inttoptr i32 %iptr to i32*
   %ignored = call i32 @llvm.nacl.atomic.rmw.i32(i32 1, i32* %ptr, i32 %v, i32 6)
   ret i32 %v
 }
 ; Technically this could use "lock add" instead of "lock xadd", if liveness
 ; tells us that the destination variable is dead.
@@ skipping 48 matching lines @@
 ; ARM32: dmb
 ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: adds
 ; ARM32: adc
 ; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: bne
 ; ARM32: dmb
 ; ARM32: b
 ; MIPS32-LABEL: test_atomic_rmw_add_64_loop
 ; MIPS32: sync
-; MIPS32: ll
-; MIPS32: addu
-; MIPS32: sltu
-; MIPS32: sc
-; MIPS32: beq   {{.*}}, $zero, {{.*}}
-; MIPS32: ll
-; MIPS32: addu
-; MIPS32: addu
-; MIPS32: sc
-; MIPS32: beq   {{.*}}, $zero, {{.*}}
+; MIPS32: jal   __sync_fetch_and_add_8
 ; MIPS32: sync
 
 ;; sub
 
 define internal i32 @test_atomic_rmw_sub_8(i32 %iptr, i32 %v) {
 entry:
   %trunc = trunc i32 %v to i8
   %ptr = inttoptr i32 %iptr to i8*
   %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 2, i8* %ptr, i8 %trunc, i32 6)
   %a_ext = zext i8 %a to i32
@@ skipping 119 matching lines @@
 ; ARM32-LABEL: test_atomic_rmw_sub_64
 ; ARM32: dmb
 ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: subs
 ; ARM32: sbc
 ; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: bne
 ; ARM32: dmb
 ; MIPS32-LABEL: test_atomic_rmw_sub_64
 ; MIPS32: sync
-; MIPS32: ll
-; MIPS32: subu
-; MIPS32: sltu
-; MIPS32: sc
-; MIPS32: beq   {{.*}}, $zero, {{.*}}
-; MIPS32: ll
-; MIPS32: addu
-; MIPS32: subu
-; MIPS32: sc
-; MIPS32: beq   {{.*}}, $zero, {{.*}}
+; MIPS32: jal   __sync_fetch_and_sub_8
 ; MIPS32: sync
 
 define internal i32 @test_atomic_rmw_sub_32_ignored(i32 %iptr, i32 %v) {
 entry:
   %ptr = inttoptr i32 %iptr to i32*
   %ignored = call i32 @llvm.nacl.atomic.rmw.i32(i32 2, i32* %ptr, i32 %v, i32 6)
   ret i32 %v
 }
 ; Could use "lock sub" instead of "neg; lock xadd"
 ; CHECK-LABEL: test_atomic_rmw_sub_32_ignored
@@ skipping 258 matching lines @@
 ; ARM32-LABEL: test_atomic_rmw_or_64
 ; ARM32: dmb
 ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: orr
 ; ARM32: orr
 ; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: bne
 ; ARM32: dmb
 ; MIPS32-LABEL: test_atomic_rmw_or_64
 ; MIPS32: sync
-; MIPS32: ll
-; MIPS32: or
-; MIPS32: sc
-; MIPS32: beq   {{.*}}, $zero, {{.*}}
-; MIPS32: ll
-; MIPS32: or
-; MIPS32: sc
-; MIPS32: beq   {{.*}}, $zero, {{.*}}
+; MIPS32: jal   __sync_fetch_and_or_8
 ; MIPS32: sync
 
 define internal i32 @test_atomic_rmw_or_32_ignored(i32 %iptr, i32 %v) {
 entry:
   %ptr = inttoptr i32 %iptr to i32*
   %ignored = call i32 @llvm.nacl.atomic.rmw.i32(i32 3, i32* %ptr, i32 %v, i32 6)
   ret i32 %v
 }
 ; CHECK-LABEL: test_atomic_rmw_or_32_ignored
 ; Could just "lock or", if we inspect the liveness information first.
@@ skipping 151 matching lines @@
 ; ARM32-LABEL: test_atomic_rmw_and_64
 ; ARM32: dmb
 ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: and
 ; ARM32: and
 ; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: bne
 ; ARM32: dmb
 ; MIPS32-LABEL: test_atomic_rmw_and_64
 ; MIPS32: sync
-; MIPS32: ll
-; MIPS32: and
-; MIPS32: sc
-; MIPS32: beq   {{.*}}, $zero, {{.*}}
-; MIPS32: ll
-; MIPS32: and
-; MIPS32: sc
-; MIPS32: beq   {{.*}}, $zero, {{.*}}
+; MIPS32: jal   __sync_fetch_and_and_8
 ; MIPS32: sync
 
 define internal i32 @test_atomic_rmw_and_32_ignored(i32 %iptr, i32 %v) {
 entry:
   %ptr = inttoptr i32 %iptr to i32*
   %ignored = call i32 @llvm.nacl.atomic.rmw.i32(i32 4, i32* %ptr, i32 %v, i32 6)
   ret i32 %v
 }
 ; CHECK-LABEL: test_atomic_rmw_and_32_ignored
 ; Could just "lock and"
@@ skipping 149 matching lines @@
 ; ARM32-LABEL: test_atomic_rmw_xor_64
 ; ARM32: dmb
 ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: eor
 ; ARM32: eor
 ; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
 ; ARM32: bne
 ; ARM32: dmb
 ; MIPS32-LABEL: test_atomic_rmw_xor_64
 ; MIPS32: sync
-; MIPS32: ll
-; MIPS32: xor
-; MIPS32: sc
-; MIPS32: beq   {{.*}}, $zero, {{.*}}
-; MIPS32: ll
-; MIPS32: xor
-; MIPS32: sc
-; MIPS32: beq   {{.*}}, $zero, {{.*}}
+; MIPS32: jal   __sync_fetch_and_xor_8
 ; MIPS32: sync
 
 define internal i32 @test_atomic_rmw_xor_32_ignored(i32 %iptr, i32 %v) {
 entry:
   %ptr = inttoptr i32 %iptr to i32*
   %ignored = call i32 @llvm.nacl.atomic.rmw.i32(i32 5, i32* %ptr, i32 %v, i32 6)
   ret i32 %v
 }
 ; CHECK-LABEL: test_atomic_rmw_xor_32_ignored
 ; CHECK: mov eax,DWORD PTR
@@ skipping 132 matching lines @@
 ; CHECK: jne
 ; ARM32-LABEL: test_atomic_rmw_xchg_64
 ; ARM32: dmb
 ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR:r[0-9]+]]{{[]]}}
 ; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}}
 ; ARM32: cmp
 ; ARM32: bne
 ; ARM32: dmb
 ; MIPS32-LABEL: test_atomic_rmw_xchg_64
 ; MIPS32: sync
-; MIPS32: ll
-; MIPS32: move
-; MIPS32: sc
-; MIPS32: beq   {{.*}}, $zero, {{.*}}
-; MIPS32: ll
-; MIPS32: move
-; MIPS32: sc
-; MIPS32: beq   {{.*}}, $zero, {{.*}}
+; MIPS32: jal   __sync_lock_test_and_set_8
 ; MIPS32: sync
 
 define internal i32 @test_atomic_rmw_xchg_32_ignored(i32 %iptr, i32 %v) {
 entry:
   %ptr = inttoptr i32 %iptr to i32*
   %ignored = call i32 @llvm.nacl.atomic.rmw.i32(i32 6, i32* %ptr, i32 %v, i32 6)
   ret i32 %v
 }
 ; In this case, ignoring the return value doesn't help. The xchg is
 ; used to do an atomic store.
@@ skipping 167 matching lines @@
 ; ARM32: ldrexd [[V0:r[0-9]+]], [[V1:r[0-9]+]], {{[[]}}[[A:r[0-9]+]]{{[]]}}
 ; ARM32: cmp [[V0]], {{r[0-9]+}}
 ; ARM32: cmpeq [[V1]], {{r[0-9]+}}
 ; ARM32: movne [[SUCCESS:r[0-9]+]],
 ; ARM32: strexdeq [[SUCCESS]], r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[A]]{{[]]}}
 ; ARM32: cmp [[SUCCESS]], #0
 ; ARM32: bne
 ; ARM32: dmb
 ; MIPS32-LABEL: test_atomic_cmpxchg_64
 ; MIPS32: sync
-; MIPS32: ll
-; MIPS32: bne
-; MIPS32: sc
-; MIPS32: beq
-; MIPS32: ll
-; MIPS32: bne
-; MIPS32: sc
-; MIPS32: beq
+; MIPS32: jal   __sync_val_compare_and_swap_8
 ; MIPS32: sync
 
 
 define internal i64 @test_atomic_cmpxchg_64_undef(i32 %iptr, i64 %desired) {
 entry:
   %ptr = inttoptr i32 %iptr to i64*
   %old = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 undef,
                                                i64 %desired, i32 6, i32 6)
   ret i64 %old
 }
 ; CHECK-LABEL: test_atomic_cmpxchg_64_undef
 ; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}+0x0]
 ; ARM32-LABEL: test_atomic_cmpxchg_64_undef
 ; ARM32: mov r{{[0-9]+}}, #0
 ; ARM32: mov r{{[0-9]+}}, #0
 ; ARM32: dmb
 ; ARM32: ldrexd [[V0:r[0-9]+]], [[V1:r[0-9]+]], {{[[]}}[[A:r[0-9]+]]{{[]]}}
 ; ARM32: cmp [[V0]], {{r[0-9]+}}
 ; ARM32: cmpeq [[V1]], {{r[0-9]+}}
 ; ARM32: movne [[SUCCESS:r[0-9]+]],
 ; ARM32: strexdeq [[SUCCESS]], r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[A]]{{[]]}}
 ; ARM32: cmp [[SUCCESS]], #0
 ; ARM32: bne
 ; ARM32: dmb
 ; MIPS32-LABEL: test_atomic_cmpxchg_64_undef
 ; MIPS32: sync
-; MIPS32: ll
-; MIPS32: bne
-; MIPS32: sc
-; MIPS32: beq
-; MIPS32: ll
-; MIPS32: bne
-; MIPS32: sc
-; MIPS32: beq
+; MIPS32: jal   __sync_val_compare_and_swap_8
 ; MIPS32: sync
 
 ; Test a case where %old really does need to be copied out of edx:eax.
 define internal void @test_atomic_cmpxchg_64_store(
     i32 %ret_iptr, i32 %iptr, i64 %expected, i64 %desired) {
 entry:
   %ptr = inttoptr i32 %iptr to i64*
   %old = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 %expected,
                                                 i64 %desired, i32 6, i32 6)
   %__6 = inttoptr i32 %ret_iptr to i64*
@@ skipping 16 matching lines @@
 ; ARM32: cmpeq [[V1]], {{r[0-9]+}}
 ; ARM32: movne [[SUCCESS:r[0-9]+]],
 ; ARM32: strexdeq [[SUCCESS]], r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[A]]{{[]]}}
 ; ARM32: cmp [[SUCCESS]], #0
 ; ARM32: bne
 ; ARM32: dmb
 ; ARM32: str
 ; ARM32: str
 ; MIPS32-LABEL: test_atomic_cmpxchg_64_store
 ; MIPS32: sync
-; MIPS32: ll
-; MIPS32: bne
-; MIPS32: sc
-; MIPS32: beq
-; MIPS32: ll
-; MIPS32: bne
-; MIPS32: sc
-; MIPS32: beq
+; MIPS32: jal   __sync_val_compare_and_swap_8
 ; MIPS32: sync
 
 
 ; Test with some more register pressure. When we have an alloca, ebp is
 ; used to manage the stack frame, so it cannot be used as a register either.
 define internal i64 @test_atomic_cmpxchg_64_alloca(i32 %iptr, i64 %expected,
                                                    i64 %desired) {
 entry:
   br label %eblock  ; Disable alloca optimization
 eblock:
@@ skipping 27 matching lines @@
 ; ARM32: ldrexd [[V0:r[0-9]+]], [[V1:r[0-9]+]], {{[[]}}[[A:r[0-9]+]]{{[]]}}
 ; ARM32: cmp [[V0]], {{r[0-9]+}}
 ; ARM32: cmpeq [[V1]], {{r[0-9]+}}
 ; ARM32: movne [[SUCCESS:r[0-9]+]],
 ; ARM32: strexdeq [[SUCCESS]], r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[A]]{{[]]}}
 ; ARM32: cmp [[SUCCESS]], #0
 ; ARM32: bne
 ; ARM32: dmb
 ; MIPS32-LABEL: test_atomic_cmpxchg_64_alloca
 ; MIPS32: sync
-; MIPS32: ll
-; MIPS32: bne
-; MIPS32: sc
-; MIPS32: beq
-; MIPS32: ll
-; MIPS32: bne
-; MIPS32: sc
-; MIPS32: beq
+; MIPS32: jal   __sync_val_compare_and_swap_8
 ; MIPS32: sync
 
 define internal i32 @test_atomic_cmpxchg_32_ignored(i32 %iptr, i32 %expected,
                                                     i32 %desired) {
 entry:
   %ptr = inttoptr i32 %iptr to i32*
   %ignored = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %expected,
                                                     i32 %desired, i32 6, i32 6)
   ret i32 0
 }
@@ skipping 37 matching lines @@
 ; ARM32: ldrexd [[V0:r[0-9]+]], [[V1:r[0-9]+]], {{[[]}}[[A:r[0-9]+]]{{[]]}}
 ; ARM32: cmp [[V0]], {{r[0-9]+}}
 ; ARM32: cmpeq [[V1]], {{r[0-9]+}}
 ; ARM32: movne [[SUCCESS:r[0-9]+]],
 ; ARM32: strexdeq [[SUCCESS]], r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}}
 ; ARM32: cmp [[SUCCESS]], #0
 ; ARM32: bne
 ; ARM32: dmb
 ; MIPS32-LABEL: test_atomic_cmpxchg_64_ignored
 ; MIPS32: sync
-; MIPS32: ll
-; MIPS32: bne
-; MIPS32: sc
-; MIPS32: beq
-; MIPS32: ll
-; MIPS32: bne
-; MIPS32: sc
-; MIPS32: beq
+; MIPS32: jal   __sync_val_compare_and_swap_8
 ; MIPS32: sync
 
 ;;;; Fence and is-lock-free.
 
 define internal void @test_atomic_fence() {
 entry:
   call void @llvm.nacl.atomic.fence(i32 6)
   ret void
 }
 ; CHECK-LABEL: test_atomic_fence
@@ skipping 167 matching lines @@
   br i1 %cmp, label %done, label %body
 done:
   ret void
 }
 ; O2-LABEL: test_cmpxchg8b_regalloc
 ;;; eax and some other register will be used in the cmpxchg instruction.
 ; O2: lock cmpxchg8b QWORD PTR
 ;;; Make sure eax/ecx/edx/ebx aren't used again, e.g. as the induction variable.
 ; O2-NOT: ,{{eax|ecx|edx|ebx}}
 ; O2: pop ebx