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Issue 2682673002:
[SubZero] Generate spin-lock for atomic load store (Closed)
| OLD | NEW |
|---|---|
| 1 //===- subzero/src/IceTargetLowering.def - Target X-macros ------*- C++ -*-===// | 1 //===- subzero/src/IceTargetLowering.def - Target X-macros ------*- C++ -*-===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 // | 9 // |
| 10 // This file defines certain platform independent patterns for lowering target | 10 // This file defines certain platform independent patterns for lowering target |
| (...skipping 27 matching lines...) Expand all Loading... | |
| 38 X(fptoui_f64_i32, "__Sz_fptoui_f64_i32") \ | 38 X(fptoui_f64_i32, "__Sz_fptoui_f64_i32") \ |
| 39 X(fptoui_f64_i64, "__Sz_fptoui_f64_i64") \ | 39 X(fptoui_f64_i64, "__Sz_fptoui_f64_i64") \ |
| 40 X(frem_f32, "fmodf") \ | 40 X(frem_f32, "fmodf") \ |
| 41 X(frem_f64, "fmod") \ | 41 X(frem_f64, "fmod") \ |
| 42 X(sdiv_i32, "__divsi3") \ | 42 X(sdiv_i32, "__divsi3") \ |
| 43 X(sdiv_i64, "__divdi3") \ | 43 X(sdiv_i64, "__divdi3") \ |
| 44 X(sitofp_i64_f32, "__Sz_sitofp_i64_f32") \ | 44 X(sitofp_i64_f32, "__Sz_sitofp_i64_f32") \ |
| 45 X(sitofp_i64_f64, "__Sz_sitofp_i64_f64") \ | 45 X(sitofp_i64_f64, "__Sz_sitofp_i64_f64") \ |
| 46 X(srem_i32, "__modsi3") \ | 46 X(srem_i32, "__modsi3") \ |
| 47 X(srem_i64, "__moddi3") \ | 47 X(srem_i64, "__moddi3") \ |
| 48 X(sync_f_n_add_8, "__sync_fetch_and_add_8") \ | |
|
Jim Stichnoth
2017/02/07 17:45:43
Sort these lines alphabetically, for consistency.
jaydeep.patil
2017/02/08 05:08:25
Done.
| |
| 49 X(sync_f_n_sub_8, "__sync_fetch_and_sub_8") \ | |
| 50 X(sync_f_n_or_8, "__sync_fetch_and_or_8") \ | |
| 51 X(sync_f_n_and_8, "__sync_fetch_and_and_8") \ | |
| 52 X(sync_f_n_xor_8, "__sync_fetch_and_xor_8") \ | |
| 53 X(sync_lock_tset_8, "__sync_lock_test_and_set_8") \ | |
| 54 X(sync_val_cx_8, "__sync_val_compare_and_swap_8") \ | |
| 48 X(udiv_i32, "__udivsi3") \ | 55 X(udiv_i32, "__udivsi3") \ |
| 49 X(udiv_i64, "__udivdi3") \ | 56 X(udiv_i64, "__udivdi3") \ |
| 50 X(uitofp_4xi32_4xf32, "__Sz_uitofp_4xi32_4xf32") \ | 57 X(uitofp_4xi32_4xf32, "__Sz_uitofp_4xi32_4xf32") \ |
| 51 X(uitofp_i32_f32, "__Sz_uitofp_i32_f32") \ | 58 X(uitofp_i32_f32, "__Sz_uitofp_i32_f32") \ |
| 52 X(uitofp_i32_f64, "__Sz_uitofp_i32_f64") \ | 59 X(uitofp_i32_f64, "__Sz_uitofp_i32_f64") \ |
| 53 X(uitofp_i64_f32, "__Sz_uitofp_i64_f32") \ | 60 X(uitofp_i64_f32, "__Sz_uitofp_i64_f32") \ |
| 54 X(uitofp_i64_f64, "__Sz_uitofp_i64_f64") \ | 61 X(uitofp_i64_f64, "__Sz_uitofp_i64_f64") \ |
| 55 X(urem_i32, "__umodsi3") \ | 62 X(urem_i32, "__umodsi3") \ |
| 56 X(urem_i64, "__umoddi3") | 63 X(urem_i64, "__umoddi3") |
| 57 //#define X(Tag, Name) | 64 //#define X(Tag, Name) |
| 58 | 65 |
| 59 #endif // SUBZERO_SRC_ICETARGETLOWERING_DEF | 66 #endif // SUBZERO_SRC_ICETARGETLOWERING_DEF |
| OLD | NEW |
