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Side by Side Diff: src/x64/assembler-x64.h

Issue 26780004: Introduce xchgl, orl, roll, subl, testl and xorl into X64 assembler (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 7 years, 2 months ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are 5 // modification, are permitted provided that the following conditions are
6 // met: 6 // met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
(...skipping 738 matching lines...) Expand 10 before | Expand all | Expand 10 after
749 void load_rax(void* ptr, RelocInfo::Mode rmode); 749 void load_rax(void* ptr, RelocInfo::Mode rmode);
750 void load_rax(ExternalReference ext); 750 void load_rax(ExternalReference ext);
751 751
752 // Conditional moves. 752 // Conditional moves.
753 void cmovq(Condition cc, Register dst, Register src); 753 void cmovq(Condition cc, Register dst, Register src);
754 void cmovq(Condition cc, Register dst, const Operand& src); 754 void cmovq(Condition cc, Register dst, const Operand& src);
755 void cmovl(Condition cc, Register dst, Register src); 755 void cmovl(Condition cc, Register dst, Register src);
756 void cmovl(Condition cc, Register dst, const Operand& src); 756 void cmovl(Condition cc, Register dst, const Operand& src);
757 757
758 // Exchange two registers 758 // Exchange two registers
759 void xchg(Register dst, Register src); 759 void xchgq(Register dst, Register src);
760 void xchgl(Register dst, Register src);
760 761
761 // Arithmetics 762 // Arithmetics
762 void addl(Register dst, Register src) { 763 void addl(Register dst, Register src) {
763 arithmetic_op_32(0x03, dst, src); 764 arithmetic_op_32(0x03, dst, src);
764 } 765 }
765 766
766 void addl(Register dst, Immediate src) { 767 void addl(Register dst, Immediate src) {
767 immediate_arithmetic_op_32(0x0, dst, src); 768 immediate_arithmetic_op_32(0x0, dst, src);
768 } 769 }
769 770
(...skipping 214 matching lines...) Expand 10 before | Expand all | Expand 10 after
984 } 985 }
985 986
986 void orl(Register dst, const Operand& src) { 987 void orl(Register dst, const Operand& src) {
987 arithmetic_op_32(0x0B, dst, src); 988 arithmetic_op_32(0x0B, dst, src);
988 } 989 }
989 990
990 void or_(const Operand& dst, Register src) { 991 void or_(const Operand& dst, Register src) {
991 arithmetic_op(0x09, src, dst); 992 arithmetic_op(0x09, src, dst);
992 } 993 }
993 994
995 void orl(const Operand& dst, Register src) {
996 arithmetic_op_32(0x09, src, dst);
997 }
998
994 void or_(Register dst, Immediate src) { 999 void or_(Register dst, Immediate src) {
995 immediate_arithmetic_op(0x1, dst, src); 1000 immediate_arithmetic_op(0x1, dst, src);
996 } 1001 }
997 1002
998 void orl(Register dst, Immediate src) { 1003 void orl(Register dst, Immediate src) {
999 immediate_arithmetic_op_32(0x1, dst, src); 1004 immediate_arithmetic_op_32(0x1, dst, src);
1000 } 1005 }
1001 1006
1002 void or_(const Operand& dst, Immediate src) { 1007 void or_(const Operand& dst, Immediate src) {
1003 immediate_arithmetic_op(0x1, dst, src); 1008 immediate_arithmetic_op(0x1, dst, src);
1004 } 1009 }
1005 1010
1006 void orl(const Operand& dst, Immediate src) { 1011 void orl(const Operand& dst, Immediate src) {
1007 immediate_arithmetic_op_32(0x1, dst, src); 1012 immediate_arithmetic_op_32(0x1, dst, src);
1008 } 1013 }
1009 1014
1010 1015
1011 void rcl(Register dst, Immediate imm8) { 1016 void rcl(Register dst, Immediate imm8) {
1012 shift(dst, imm8, 0x2); 1017 shift(dst, imm8, 0x2);
1013 } 1018 }
1014 1019
1015 void rol(Register dst, Immediate imm8) { 1020 void rol(Register dst, Immediate imm8) {
1016 shift(dst, imm8, 0x0); 1021 shift(dst, imm8, 0x0);
1017 } 1022 }
1018 1023
1024 void roll(Register dst, Immediate imm8) {
1025 shift_32(dst, imm8, 0x0);
1026 }
1027
1019 void rcr(Register dst, Immediate imm8) { 1028 void rcr(Register dst, Immediate imm8) {
1020 shift(dst, imm8, 0x3); 1029 shift(dst, imm8, 0x3);
1021 } 1030 }
1022 1031
1023 void ror(Register dst, Immediate imm8) { 1032 void ror(Register dst, Immediate imm8) {
1024 shift(dst, imm8, 0x1); 1033 shift(dst, imm8, 0x1);
1025 } 1034 }
1026 1035
1027 void rorl(Register dst, Immediate imm8) { 1036 void rorl(Register dst, Immediate imm8) {
1028 shift_32(dst, imm8, 0x1); 1037 shift_32(dst, imm8, 0x1);
(...skipping 87 matching lines...) Expand 10 before | Expand all | Expand 10 after
1116 } 1125 }
1117 1126
1118 void subl(Register dst, Register src) { 1127 void subl(Register dst, Register src) {
1119 arithmetic_op_32(0x2B, dst, src); 1128 arithmetic_op_32(0x2B, dst, src);
1120 } 1129 }
1121 1130
1122 void subl(Register dst, const Operand& src) { 1131 void subl(Register dst, const Operand& src) {
1123 arithmetic_op_32(0x2B, dst, src); 1132 arithmetic_op_32(0x2B, dst, src);
1124 } 1133 }
1125 1134
1135 void subl(const Operand& dst, Register src) {
1136 arithmetic_op_32(0x29, src, dst);
1137 }
1138
1126 void subl(const Operand& dst, Immediate src) { 1139 void subl(const Operand& dst, Immediate src) {
1127 immediate_arithmetic_op_32(0x5, dst, src); 1140 immediate_arithmetic_op_32(0x5, dst, src);
1128 } 1141 }
1129 1142
1130 void subl(Register dst, Immediate src) { 1143 void subl(Register dst, Immediate src) {
1131 immediate_arithmetic_op_32(0x5, dst, src); 1144 immediate_arithmetic_op_32(0x5, dst, src);
1132 } 1145 }
1133 1146
1134 void subb(Register dst, Immediate src) { 1147 void subb(Register dst, Immediate src) {
1135 immediate_arithmetic_op_8(0x5, dst, src); 1148 immediate_arithmetic_op_8(0x5, dst, src);
1136 } 1149 }
1137 1150
1138 void testb(Register dst, Register src); 1151 void testb(Register dst, Register src);
1139 void testb(Register reg, Immediate mask); 1152 void testb(Register reg, Immediate mask);
1140 void testb(const Operand& op, Immediate mask); 1153 void testb(const Operand& op, Immediate mask);
1141 void testb(const Operand& op, Register reg); 1154 void testb(const Operand& op, Register reg);
1142 void testl(Register dst, Register src); 1155 void testl(Register dst, Register src);
1143 void testl(Register reg, Immediate mask); 1156 void testl(Register reg, Immediate mask);
1157 void testl(const Operand& op, Register reg);
1144 void testl(const Operand& op, Immediate mask); 1158 void testl(const Operand& op, Immediate mask);
1145 void testq(const Operand& op, Register reg); 1159 void testq(const Operand& op, Register reg);
1146 void testq(Register dst, Register src); 1160 void testq(Register dst, Register src);
1147 void testq(Register dst, Immediate mask); 1161 void testq(Register dst, Immediate mask);
1148 1162
1149 void xor_(Register dst, Register src) { 1163 void xor_(Register dst, Register src) {
1150 if (dst.code() == src.code()) { 1164 if (dst.code() == src.code()) {
1151 arithmetic_op_32(0x33, dst, src); 1165 arithmetic_op_32(0x33, dst, src);
1152 } else { 1166 } else {
1153 arithmetic_op(0x33, dst, src); 1167 arithmetic_op(0x33, dst, src);
1154 } 1168 }
1155 } 1169 }
1156 1170
1157 void xorl(Register dst, Register src) { 1171 void xorl(Register dst, Register src) {
1158 arithmetic_op_32(0x33, dst, src); 1172 arithmetic_op_32(0x33, dst, src);
1159 } 1173 }
1160 1174
1161 void xorl(Register dst, const Operand& src) { 1175 void xorl(Register dst, const Operand& src) {
1162 arithmetic_op_32(0x33, dst, src); 1176 arithmetic_op_32(0x33, dst, src);
1163 } 1177 }
1164 1178
1165 void xorl(Register dst, Immediate src) { 1179 void xorl(Register dst, Immediate src) {
1166 immediate_arithmetic_op_32(0x6, dst, src); 1180 immediate_arithmetic_op_32(0x6, dst, src);
1167 } 1181 }
1168 1182
1183 void xorl(const Operand& dst, Register src) {
1184 arithmetic_op_32(0x31, src, dst);
1185 }
1186
1169 void xorl(const Operand& dst, Immediate src) { 1187 void xorl(const Operand& dst, Immediate src) {
1170 immediate_arithmetic_op_32(0x6, dst, src); 1188 immediate_arithmetic_op_32(0x6, dst, src);
1171 } 1189 }
1172 1190
1173 void xor_(Register dst, const Operand& src) { 1191 void xor_(Register dst, const Operand& src) {
1174 arithmetic_op(0x33, dst, src); 1192 arithmetic_op(0x33, dst, src);
1175 } 1193 }
1176 1194
1177 void xor_(const Operand& dst, Register src) { 1195 void xor_(const Operand& dst, Register src) {
1178 arithmetic_op(0x31, src, dst); 1196 arithmetic_op(0x31, src, dst);
(...skipping 502 matching lines...) Expand 10 before | Expand all | Expand 10 after
1681 private: 1699 private:
1682 Assembler* assembler_; 1700 Assembler* assembler_;
1683 #ifdef DEBUG 1701 #ifdef DEBUG
1684 int space_before_; 1702 int space_before_;
1685 #endif 1703 #endif
1686 }; 1704 };
1687 1705
1688 } } // namespace v8::internal 1706 } } // namespace v8::internal
1689 1707
1690 #endif // V8_X64_ASSEMBLER_X64_H_ 1708 #endif // V8_X64_ASSEMBLER_X64_H_
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