[arm64][turbofan] Fix add+shr for big shift values.

test/unittests/compiler/arm64/instruction-selector-arm64-unittest.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "test/unittests/compiler/instruction-selector-unittest.h"
 
 namespace v8 {
 namespace internal {
 namespace compiler {
 
@@ skipping 727 matching lines @@
             m.Int32Constant(0),
             (m.*shift.mi.constructor)(m.Parameter(1), m.Int32Constant(imm))));
         Stream s = m.Build();
 
         ASSERT_EQ(1U, s.size());
         EXPECT_EQ(kArm64Sub32, s[0]->arch_opcode());
         ASSERT_EQ(3U, s[0]->InputCount());
         EXPECT_TRUE(s[0]->InputAt(0)->IsImmediate());
         EXPECT_EQ(0, s.ToInt32(s[0]->InputAt(0)));
         EXPECT_EQ(shift.mode, s[0]->addressing_mode());
-        EXPECT_EQ(imm, s.ToInt32(s[0]->InputAt(2)));
+        EXPECT_EQ(0x3f & imm, 0x3f & s.ToInt32(s[0]->InputAt(2)));
         EXPECT_EQ(1U, s[0]->OutputCount());
       }
     }
     {
       // Test 64-bit operations. Ignore ROR shifts, as subtract does not
       // support them.
       if ((shift.mi.machine_type != MachineType::Int64()) ||
           (shift.mi.arch_opcode == kArm64Ror32) ||
           (shift.mi.arch_opcode == kArm64Ror))
         continue;
 
       TRACED_FORRANGE(int, imm, -32, 127) {
         StreamBuilder m(this, MachineType::Int64(), MachineType::Int64(),
                         MachineType::Int64());
         m.Return(m.Int64Sub(
             m.Int64Constant(0),
             (m.*shift.mi.constructor)(m.Parameter(1), m.Int64Constant(imm))));
         Stream s = m.Build();
 
         ASSERT_EQ(1U, s.size());
         EXPECT_EQ(kArm64Sub, s[0]->arch_opcode());
         ASSERT_EQ(3U, s[0]->InputCount());
         EXPECT_TRUE(s[0]->InputAt(0)->IsImmediate());
         EXPECT_EQ(0, s.ToInt32(s[0]->InputAt(0)));
         EXPECT_EQ(shift.mode, s[0]->addressing_mode());
-        EXPECT_EQ(imm, s.ToInt32(s[0]->InputAt(2)));
+        EXPECT_EQ(0x3f & imm, 0x3f & s.ToInt32(s[0]->InputAt(2)));
         EXPECT_EQ(1U, s[0]->OutputCount());
       }
     }
   }
 }
 
 
 TEST_F(InstructionSelectorTest, AddNegImmediateOnLeft) {
   {
     // 32-bit add.
@@ skipping 43 matching lines @@
       StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
                       MachineType::Int32());
       m.Return((m.Int32Add)(
           (m.*shift.mi.constructor)(m.Parameter(1), m.Int32Constant(imm)),
           m.Parameter(0)));
       Stream s = m.Build();
       ASSERT_EQ(1U, s.size());
       EXPECT_EQ(kArm64Add32, s[0]->arch_opcode());
       EXPECT_EQ(shift.mode, s[0]->addressing_mode());
       EXPECT_EQ(3U, s[0]->InputCount());
-      EXPECT_EQ(imm, s.ToInt64(s[0]->InputAt(2)));
+      EXPECT_EQ(0x3f & imm, 0x3f & s.ToInt64(s[0]->InputAt(2)));
       EXPECT_EQ(1U, s[0]->OutputCount());
     }
   }
 
   // 64-bit add.
   TRACED_FOREACH(Shift, shift, kShiftInstructions) {
     // Only test relevant shifted operands.
     if (shift.mi.machine_type != MachineType::Int64()) continue;
     if (shift.mi.arch_opcode == kArm64Ror) continue;
 
     // The available shift operand range is `0 <= imm < 64`, but we also test
     // that immediates outside this range are handled properly (modulo-64).
     TRACED_FORRANGE(int, imm, -64, 127) {
       StreamBuilder m(this, MachineType::Int64(), MachineType::Int64(),
                       MachineType::Int64());
       m.Return((m.Int64Add)(
           (m.*shift.mi.constructor)(m.Parameter(1), m.Int64Constant(imm)),
           m.Parameter(0)));
       Stream s = m.Build();
       ASSERT_EQ(1U, s.size());
       EXPECT_EQ(kArm64Add, s[0]->arch_opcode());
       EXPECT_EQ(shift.mode, s[0]->addressing_mode());
       EXPECT_EQ(3U, s[0]->InputCount());
-      EXPECT_EQ(imm, s.ToInt64(s[0]->InputAt(2)));
+      EXPECT_EQ(0x3f & imm, 0x3f & s.ToInt64(s[0]->InputAt(2)));
       EXPECT_EQ(1U, s[0]->OutputCount());
     }
   }
 }
 
 
 TEST_F(InstructionSelectorTest, AddUnsignedExtendByteOnLeft) {
   {
     StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
                     MachineType::Int32());
@@ skipping 2044 matching lines @@
       Node* const p1 = m.Parameter(1);
       Node* r = (m.*shift.mi.constructor)(p1, m.Int32Constant(imm));
       m.Return(m.Word32Equal(p0, r));
       Stream s = m.Build();
       ASSERT_EQ(1U, s.size());
       EXPECT_EQ(kArm64Cmp32, s[0]->arch_opcode());
       EXPECT_EQ(shift.mode, s[0]->addressing_mode());
       ASSERT_EQ(3U, s[0]->InputCount());
       EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
       EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
-      EXPECT_EQ(imm, s.ToInt32(s[0]->InputAt(2)));
+      EXPECT_EQ(0x3f & imm, 0x3f & s.ToInt32(s[0]->InputAt(2)));
       ASSERT_EQ(1U, s[0]->OutputCount());
     }
     TRACED_FORRANGE(int32_t, imm, -32, 63) {
       StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
                       MachineType::Int32());
       Node* const p0 = m.Parameter(0);
       Node* const p1 = m.Parameter(1);
       Node* r = (m.*shift.mi.constructor)(p1, m.Int32Constant(imm));
       m.Return(m.Word32Equal(r, p0));
       Stream s = m.Build();
       ASSERT_EQ(1U, s.size());
       EXPECT_EQ(kArm64Cmp32, s[0]->arch_opcode());
       EXPECT_EQ(shift.mode, s[0]->addressing_mode());
       ASSERT_EQ(3U, s[0]->InputCount());
       EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
       EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
-      EXPECT_EQ(imm, s.ToInt32(s[0]->InputAt(2)));
+      EXPECT_EQ(0x3f & imm, 0x3f & s.ToInt32(s[0]->InputAt(2)));
       ASSERT_EQ(1U, s[0]->OutputCount());
     }
   }
 }
 
 
 TEST_F(InstructionSelectorTest, Word32EqualWithUnsignedExtendByte) {
   {
     StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
                     MachineType::Int32());
@@ skipping 241 matching lines @@
         Node* const p0 = m.Parameter(0);
         Node* const p1 = m.Parameter(1);
         Node* r = (m.*shift.mi.constructor)(p1, m.Int32Constant(imm));
         m.Return(
             (m.*cmp.mi.constructor)(p0, m.Int32Sub(m.Int32Constant(0), r)));
         Stream s = m.Build();
         ASSERT_EQ(1U, s.size());
         EXPECT_EQ(kArm64Cmn32, s[0]->arch_opcode());
         EXPECT_EQ(3U, s[0]->InputCount());
         EXPECT_EQ(shift.mode, s[0]->addressing_mode());
-        EXPECT_EQ(imm, s.ToInt32(s[0]->InputAt(2)));
+        EXPECT_EQ(0x3f & imm, 0x3f & s.ToInt32(s[0]->InputAt(2)));
         EXPECT_EQ(1U, s[0]->OutputCount());
         EXPECT_EQ(kFlags_set, s[0]->flags_mode());
         EXPECT_EQ(cmp.cond, s[0]->flags_condition());
       }
     }
   }
 }
 
 TEST_F(InstructionSelectorTest, CmpWithImmediateOnLeft) {
   TRACED_FOREACH(IntegerCmp, cmp, kIntegerCmpInstructions) {
@@ skipping 87 matching lines @@
         Stream s = m.Build();
         // Cmp does not support ROR shifts.
         if (shift.mi.arch_opcode == kArm64Ror32) {
           ASSERT_EQ(2U, s.size());
           continue;
         }
         ASSERT_EQ(1U, s.size());
         EXPECT_EQ(kArm64Cmp32, s[0]->arch_opcode());
         EXPECT_EQ(shift.mode, s[0]->addressing_mode());
         EXPECT_EQ(3U, s[0]->InputCount());
-        EXPECT_EQ(imm, s.ToInt64(s[0]->InputAt(2)));
+        EXPECT_EQ(0x3f & imm, 0x3f & s.ToInt64(s[0]->InputAt(2)));
         EXPECT_EQ(1U, s[0]->OutputCount());
         EXPECT_EQ(kFlags_set, s[0]->flags_mode());
         EXPECT_EQ(cmp.commuted_cond, s[0]->flags_condition());
       }
     }
   }
 }
 
 TEST_F(InstructionSelectorTest, CmnShiftByImmediateOnLeft) {
   TRACED_FOREACH(IntegerCmp, cmp, kIntegerCmpEqualityInstructions) {
@@ skipping 13 matching lines @@
         Stream s = m.Build();
         // Cmn does not support ROR shifts.
         if (shift.mi.arch_opcode == kArm64Ror32) {
           ASSERT_EQ(2U, s.size());
           continue;
         }
         ASSERT_EQ(1U, s.size());
         EXPECT_EQ(kArm64Cmn32, s[0]->arch_opcode());
         EXPECT_EQ(shift.mode, s[0]->addressing_mode());
         EXPECT_EQ(3U, s[0]->InputCount());
-        EXPECT_EQ(imm, s.ToInt64(s[0]->InputAt(2)));
+        EXPECT_EQ(0x3f & imm, 0x3f & s.ToInt64(s[0]->InputAt(2)));
         EXPECT_EQ(1U, s[0]->OutputCount());
         EXPECT_EQ(kFlags_set, s[0]->flags_mode());
         EXPECT_EQ(cmp.cond, s[0]->flags_condition());
       }
     }
   }
 }
 
 // -----------------------------------------------------------------------------
 // Flag-setting add and and instructions.
@@ skipping 1016 matching lines @@
   EXPECT_EQ(kArm64TestAndBranch, s[1]->arch_opcode());
   EXPECT_EQ(kEqual, s[1]->flags_condition());
   EXPECT_EQ(4U, s[1]->InputCount());
   EXPECT_EQ(InstructionOperand::IMMEDIATE, s[1]->InputAt(1)->kind());
   EXPECT_EQ(63, s.ToInt32(s[1]->InputAt(1)));
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8