[Turbofan] Add more integer SIMD operations for ARM.

src/compiler/arm/instruction-selector-arm.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/base/adapters.h"
 #include "src/base/bits.h"
 #include "src/compiler/instruction-selector-impl.h"
 #include "src/compiler/node-matchers.h"
 #include "src/compiler/node-properties.h"
 
@@ skipping 2172 matching lines @@
   V(Float32x4NotEqual)          \
   V(Int32x4Add)                 \
   V(Int32x4Sub)                 \
   V(Int32x4Mul)                 \
   V(Int32x4Min)                 \
   V(Int32x4Max)                 \
   V(Int32x4Equal)               \
   V(Int32x4NotEqual)            \
   V(Int32x4GreaterThan)         \
   V(Int32x4GreaterThanOrEqual)  \
+  V(Uint32x4Min)                \
+  V(Uint32x4Max)                \
   V(Uint32x4GreaterThan)        \
   V(Uint32x4GreaterThanOrEqual) \
   V(Int16x8Add)                 \
+  V(Int16x8AddSaturate)         \
   V(Int16x8Sub)                 \
+  V(Int16x8SubSaturate)         \
   V(Int16x8Mul)                 \
   V(Int16x8Min)                 \
   V(Int16x8Max)                 \
   V(Int16x8Equal)               \
   V(Int16x8NotEqual)            \
   V(Int16x8GreaterThan)         \
   V(Int16x8GreaterThanOrEqual)  \
+  V(Uint16x8AddSaturate)        \
+  V(Uint16x8SubSaturate)        \
+  V(Uint16x8Min)                \
+  V(Uint16x8Max)                \
   V(Uint16x8GreaterThan)        \
   V(Uint16x8GreaterThanOrEqual) \
   V(Int8x16Add)                 \
+  V(Int8x16AddSaturate)         \
   V(Int8x16Sub)                 \
+  V(Int8x16SubSaturate)         \
   V(Int8x16Mul)                 \
   V(Int8x16Min)                 \
   V(Int8x16Max)                 \
   V(Int8x16Equal)               \
   V(Int8x16NotEqual)            \
   V(Int8x16GreaterThan)         \
   V(Int8x16GreaterThanOrEqual)  \
+  V(Uint8x16AddSaturate)        \
+  V(Uint8x16SubSaturate)        \
+  V(Uint8x16Min)                \
+  V(Uint8x16Max)                \
   V(Uint8x16GreaterThan)        \
   V(Uint8x16GreaterThanOrEqual)
 
+#define SIMD_SHIFT_OP_LIST(V)   \
+  V(Int32x4ShiftLeftByScalar)   \
+  V(Int32x4ShiftRightByScalar)  \
+  V(Uint32x4ShiftRightByScalar) \
+  V(Int16x8ShiftLeftByScalar)   \
+  V(Int16x8ShiftRightByScalar)  \
+  V(Uint16x8ShiftRightByScalar) \
+  V(Int8x16ShiftLeftByScalar)   \
+  V(Int8x16ShiftRightByScalar)  \
+  V(Uint8x16ShiftRightByScalar)
+
 #define SIMD_VISIT_SPLAT(Type)                              \
   void InstructionSelector::VisitCreate##Type(Node* node) { \
     VisitRR(this, kArm##Type##Splat, node);                 \
   }
 SIMD_TYPE_LIST(SIMD_VISIT_SPLAT)
 #undef SIMD_VISIT_SPLAT
 
 #define SIMD_VISIT_EXTRACT_LANE(Type)                              \
   void InstructionSelector::Visit##Type##ExtractLane(Node* node) { \
     VisitRRI(this, kArm##Type##ExtractLane, node);                 \
@@ skipping 15 matching lines @@
 SIMD_UNOP_LIST(SIMD_VISIT_UNOP)
 #undef SIMD_VISIT_UNOP
 
 #define SIMD_VISIT_BINOP(Name)                        \
   void InstructionSelector::Visit##Name(Node* node) { \
     VisitRRR(this, kArm##Name, node);                 \
   }
 SIMD_BINOP_LIST(SIMD_VISIT_BINOP)
 #undef SIMD_VISIT_BINOP
 
+#define SIMD_VISIT_SHIFT_OP(Name)                     \
+  void InstructionSelector::Visit##Name(Node* node) { \
+    VisitRRI(this, kArm##Name, node);                 \
+  }
+SIMD_SHIFT_OP_LIST(SIMD_VISIT_SHIFT_OP)
+#undef SIMD_VISIT_SHIFT_OP
+
 void InstructionSelector::VisitSimd32x4Select(Node* node) {
   ArmOperandGenerator g(this);
   Emit(kArmSimd32x4Select, g.DefineAsRegister(node),
        g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)),
        g.UseRegister(node->InputAt(2)));
 }
 
 // static
 MachineOperatorBuilder::Flags
 InstructionSelector::SupportedMachineOperatorFlags() {
@@ skipping 27 matching lines @@
   Vector<MachineType> req_aligned = Vector<MachineType>::New(2);
   req_aligned[0] = MachineType::Float32();
   req_aligned[1] = MachineType::Float64();
   return MachineOperatorBuilder::AlignmentRequirements::
       SomeUnalignedAccessUnsupported(req_aligned, req_aligned);
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8