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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ | 5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ |
6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ | 6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ |
7 | 7 |
8 namespace v8 { | 8 namespace v8 { |
9 namespace internal { | 9 namespace internal { |
10 namespace compiler { | 10 namespace compiler { |
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130 V(ArmFloat32x4Add) \ | 130 V(ArmFloat32x4Add) \ |
131 V(ArmFloat32x4Sub) \ | 131 V(ArmFloat32x4Sub) \ |
132 V(ArmFloat32x4Equal) \ | 132 V(ArmFloat32x4Equal) \ |
133 V(ArmFloat32x4NotEqual) \ | 133 V(ArmFloat32x4NotEqual) \ |
134 V(ArmInt32x4Splat) \ | 134 V(ArmInt32x4Splat) \ |
135 V(ArmInt32x4ExtractLane) \ | 135 V(ArmInt32x4ExtractLane) \ |
136 V(ArmInt32x4ReplaceLane) \ | 136 V(ArmInt32x4ReplaceLane) \ |
137 V(ArmInt32x4FromFloat32x4) \ | 137 V(ArmInt32x4FromFloat32x4) \ |
138 V(ArmUint32x4FromFloat32x4) \ | 138 V(ArmUint32x4FromFloat32x4) \ |
139 V(ArmInt32x4Neg) \ | 139 V(ArmInt32x4Neg) \ |
| 140 V(ArmInt32x4ShiftLeftByScalar) \ |
| 141 V(ArmInt32x4ShiftRightByScalar) \ |
140 V(ArmInt32x4Add) \ | 142 V(ArmInt32x4Add) \ |
141 V(ArmInt32x4Sub) \ | 143 V(ArmInt32x4Sub) \ |
142 V(ArmInt32x4Mul) \ | 144 V(ArmInt32x4Mul) \ |
143 V(ArmInt32x4Min) \ | 145 V(ArmInt32x4Min) \ |
144 V(ArmInt32x4Max) \ | 146 V(ArmInt32x4Max) \ |
145 V(ArmInt32x4Equal) \ | 147 V(ArmInt32x4Equal) \ |
146 V(ArmInt32x4NotEqual) \ | 148 V(ArmInt32x4NotEqual) \ |
147 V(ArmInt32x4GreaterThan) \ | 149 V(ArmInt32x4GreaterThan) \ |
148 V(ArmInt32x4GreaterThanOrEqual) \ | 150 V(ArmInt32x4GreaterThanOrEqual) \ |
| 151 V(ArmUint32x4ShiftRightByScalar) \ |
| 152 V(ArmUint32x4Min) \ |
| 153 V(ArmUint32x4Max) \ |
149 V(ArmUint32x4GreaterThan) \ | 154 V(ArmUint32x4GreaterThan) \ |
150 V(ArmUint32x4GreaterThanOrEqual) \ | 155 V(ArmUint32x4GreaterThanOrEqual) \ |
151 V(ArmSimd32x4Select) \ | 156 V(ArmSimd32x4Select) \ |
152 V(ArmInt16x8Splat) \ | 157 V(ArmInt16x8Splat) \ |
153 V(ArmInt16x8ExtractLane) \ | 158 V(ArmInt16x8ExtractLane) \ |
154 V(ArmInt16x8ReplaceLane) \ | 159 V(ArmInt16x8ReplaceLane) \ |
155 V(ArmInt16x8Neg) \ | 160 V(ArmInt16x8Neg) \ |
| 161 V(ArmInt16x8ShiftLeftByScalar) \ |
| 162 V(ArmInt16x8ShiftRightByScalar) \ |
156 V(ArmInt16x8Add) \ | 163 V(ArmInt16x8Add) \ |
| 164 V(ArmInt16x8AddSaturate) \ |
157 V(ArmInt16x8Sub) \ | 165 V(ArmInt16x8Sub) \ |
| 166 V(ArmInt16x8SubSaturate) \ |
158 V(ArmInt16x8Mul) \ | 167 V(ArmInt16x8Mul) \ |
159 V(ArmInt16x8Min) \ | 168 V(ArmInt16x8Min) \ |
160 V(ArmInt16x8Max) \ | 169 V(ArmInt16x8Max) \ |
161 V(ArmInt16x8Equal) \ | 170 V(ArmInt16x8Equal) \ |
162 V(ArmInt16x8NotEqual) \ | 171 V(ArmInt16x8NotEqual) \ |
163 V(ArmInt16x8GreaterThan) \ | 172 V(ArmInt16x8GreaterThan) \ |
164 V(ArmInt16x8GreaterThanOrEqual) \ | 173 V(ArmInt16x8GreaterThanOrEqual) \ |
| 174 V(ArmUint16x8ShiftRightByScalar) \ |
| 175 V(ArmUint16x8AddSaturate) \ |
| 176 V(ArmUint16x8SubSaturate) \ |
| 177 V(ArmUint16x8Min) \ |
| 178 V(ArmUint16x8Max) \ |
165 V(ArmUint16x8GreaterThan) \ | 179 V(ArmUint16x8GreaterThan) \ |
166 V(ArmUint16x8GreaterThanOrEqual) \ | 180 V(ArmUint16x8GreaterThanOrEqual) \ |
167 V(ArmInt8x16Splat) \ | 181 V(ArmInt8x16Splat) \ |
168 V(ArmInt8x16ExtractLane) \ | 182 V(ArmInt8x16ExtractLane) \ |
169 V(ArmInt8x16ReplaceLane) \ | 183 V(ArmInt8x16ReplaceLane) \ |
170 V(ArmInt8x16Neg) \ | 184 V(ArmInt8x16Neg) \ |
| 185 V(ArmInt8x16ShiftLeftByScalar) \ |
| 186 V(ArmInt8x16ShiftRightByScalar) \ |
171 V(ArmInt8x16Add) \ | 187 V(ArmInt8x16Add) \ |
| 188 V(ArmInt8x16AddSaturate) \ |
172 V(ArmInt8x16Sub) \ | 189 V(ArmInt8x16Sub) \ |
| 190 V(ArmInt8x16SubSaturate) \ |
173 V(ArmInt8x16Mul) \ | 191 V(ArmInt8x16Mul) \ |
174 V(ArmInt8x16Min) \ | 192 V(ArmInt8x16Min) \ |
175 V(ArmInt8x16Max) \ | 193 V(ArmInt8x16Max) \ |
176 V(ArmInt8x16Equal) \ | 194 V(ArmInt8x16Equal) \ |
177 V(ArmInt8x16NotEqual) \ | 195 V(ArmInt8x16NotEqual) \ |
178 V(ArmInt8x16GreaterThan) \ | 196 V(ArmInt8x16GreaterThan) \ |
179 V(ArmInt8x16GreaterThanOrEqual) \ | 197 V(ArmInt8x16GreaterThanOrEqual) \ |
| 198 V(ArmUint8x16ShiftRightByScalar) \ |
| 199 V(ArmUint8x16AddSaturate) \ |
| 200 V(ArmUint8x16SubSaturate) \ |
| 201 V(ArmUint8x16Min) \ |
| 202 V(ArmUint8x16Max) \ |
180 V(ArmUint8x16GreaterThan) \ | 203 V(ArmUint8x16GreaterThan) \ |
181 V(ArmUint8x16GreaterThanOrEqual) | 204 V(ArmUint8x16GreaterThanOrEqual) |
182 | 205 |
183 // Addressing modes represent the "shape" of inputs to an instruction. | 206 // Addressing modes represent the "shape" of inputs to an instruction. |
184 // Many instructions support multiple addressing modes. Addressing modes | 207 // Many instructions support multiple addressing modes. Addressing modes |
185 // are encoded into the InstructionCode of the instruction and tell the | 208 // are encoded into the InstructionCode of the instruction and tell the |
186 // code generator after register allocation which assembler method to call. | 209 // code generator after register allocation which assembler method to call. |
187 #define TARGET_ADDRESSING_MODE_LIST(V) \ | 210 #define TARGET_ADDRESSING_MODE_LIST(V) \ |
188 V(Offset_RI) /* [%r0 + K] */ \ | 211 V(Offset_RI) /* [%r0 + K] */ \ |
189 V(Offset_RR) /* [%r0 + %r1] */ \ | 212 V(Offset_RR) /* [%r0 + %r1] */ \ |
190 V(Operand2_I) /* K */ \ | 213 V(Operand2_I) /* K */ \ |
191 V(Operand2_R) /* %r0 */ \ | 214 V(Operand2_R) /* %r0 */ \ |
192 V(Operand2_R_ASR_I) /* %r0 ASR K */ \ | 215 V(Operand2_R_ASR_I) /* %r0 ASR K */ \ |
193 V(Operand2_R_LSL_I) /* %r0 LSL K */ \ | 216 V(Operand2_R_LSL_I) /* %r0 LSL K */ \ |
194 V(Operand2_R_LSR_I) /* %r0 LSR K */ \ | 217 V(Operand2_R_LSR_I) /* %r0 LSR K */ \ |
195 V(Operand2_R_ROR_I) /* %r0 ROR K */ \ | 218 V(Operand2_R_ROR_I) /* %r0 ROR K */ \ |
196 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \ | 219 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \ |
197 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \ | 220 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \ |
198 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \ | 221 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \ |
199 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */ | 222 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */ |
200 | 223 |
201 } // namespace compiler | 224 } // namespace compiler |
202 } // namespace internal | 225 } // namespace internal |
203 } // namespace v8 | 226 } // namespace v8 |
204 | 227 |
205 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ | 228 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ |
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