S390: Use macro to declare rx format assember function

src/s390/assembler-s390.h

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 684 matching lines @@
   void lzdr(DoubleRegister r1) { rre_format(LZDR, r1.code(), 0); }
 #undef DECLARE_S390_RRE_INSTRUCTIONS
 
   inline void rrf_format(Opcode opcode, int f1, int f2, int f3, int f4) {
     emit4bytes(
         getfield<uint32_t, 4, 0, 16>(opcode) |
         getfield<uint32_t, 4, 16, 20>(f1) | getfield<uint32_t, 4, 20, 24>(f2) |
         getfield<uint32_t, 4, 24, 28>(f3) | getfield<uint32_t, 4, 28, 32>(f4));
   }
 
+#define DECLARE_S390_RX_INSTRUCTIONS(name, op_name, op_value)        \
+  template <class R1>                                                \
+  inline void name(R1 r1, Register x2, Register b2, Disp d2) {       \
+    rx_format(op_name, r1.code(), x2.code(), b2.code(), d2);         \
+  }                                                                  \
+  template <class R1>                                                \
+  inline void name(R1 r1, const MemOperand& opnd) {                  \
+    name(r1, opnd.getIndexRegister(),                                \
+         opnd.getBaseRegister(), opnd.getDisplacement());            \
+  }
+
+  inline void rx_format(Opcode opcode, int f1, int f2, int f3, int f4) {
+    DCHECK(is_uint8(opcode));
+    DCHECK(is_uint12(f4));
+    emit4bytes(getfield<uint32_t, 4, 0, 8>(opcode) |
+               getfield<uint32_t, 4, 8, 12>(f1) |
+               getfield<uint32_t, 4, 12, 16>(f2) |
+               getfield<uint32_t, 4, 16, 20>(f3) |
+               getfield<uint32_t, 4, 20, 32>(f4));
+  }
+  S390_RX_A_OPCODE_LIST(DECLARE_S390_RX_INSTRUCTIONS)
+
+  void bc(Condition cond, const MemOperand& opnd) {
+    bc(cond, opnd.getIndexRegister(),
+       opnd.getBaseRegister(), opnd.getDisplacement());
+  }
+  void bc(Condition cond, Register x2, Register b2, Disp d2) {
+    rx_format(BC, cond, x2.code(), b2.code(), d2);
+  }
+#undef DECLARE_S390_RX_INSTRUCTIONS
+
   // Helper for unconditional branch to Label with update to save register
   void b(Register r, Label* l) {
     int32_t halfwords = branch_offset(l) / 2;
     brasl(r, Operand(halfwords));
   }
 
   // Conditional Branch Instruction - Generates either BRC / BRCL
   void branchOnCond(Condition c, int branch_offset, bool is_bound = false);
 
   // Helpers for conditional branch to Label
@@ skipping 68 matching lines @@
             TypeFeedbackId ast_id = TypeFeedbackId::None());
   void jump(Handle<Code> target, RelocInfo::Mode rmode, Condition cond);
 
 // S390 instruction generation
 #define I_FORM(name) void name(const Operand& i)
 
 #define RR_FORM(name) void name(Register r1, Register r2)
 
 #define RR2_FORM(name) void name(Condition m1, Register r2)
 
-#define RX_FORM(name)                                        \
-  void name(Register r1, Register x2, Register b2, Disp d2); \
-  void name(Register r1, const MemOperand& opnd)
-
 #define RI1_FORM(name) void name(Register r, const Operand& i)
 
 #define RI2_FORM(name) void name(Condition m, const Operand& i)
 
 #define RIE_FORM(name) void name(Register r1, Register R3, const Operand& i)
 
 #define RIE_F_FORM(name)                                                    \
   void name(Register r1, Register r2, const Operand& i3, const Operand& i4, \
             const Operand& i5)
 
@@ skipping 143 matching lines @@
   void vfm(DoubleRegister v1, DoubleRegister v2, DoubleRegister v3) {
     vfm(v1, v2, v3, static_cast<Condition>(0), static_cast<Condition>(8),
         static_cast<Condition>(3));
   }
   void vfd(DoubleRegister v1, DoubleRegister v2, DoubleRegister v3) {
     vfd(v1, v2, v3, static_cast<Condition>(0), static_cast<Condition>(8),
         static_cast<Condition>(3));
   }
 
   // S390 instruction sets
-  RX_FORM(bc);
-  RX_FORM(cd);
   RXE_FORM(cdb);
   RXE_FORM(ceb);
   RXE_FORM(ddb);
   SS1_FORM(ed);
-  RX_FORM(ex);
   RRF2_FORM(fidbr);
-  RX_FORM(ic_z);
   RXY_FORM(icy);
   RI1_FORM(iihh);
   RI1_FORM(iihl);
   RI1_FORM(iilh);
   RI1_FORM(iill);
-  RX_FORM(le_z);
   RXY_FORM(ley);
   RSY1_FORM(loc);
   RXY_FORM(lrv);
   RXY_FORM(lrvh);
   RXY_FORM(lrvg);
   RXE_FORM(mdb);
   SS4_FORM(mvck);
   SSF_FORM(mvcos);
   SS4_FORM(mvcs);
   SS1_FORM(mvn);
   SS1_FORM(nc);
   SI_FORM(ni);
   RI1_FORM(nilh);
   RI1_FORM(nill);
   RI1_FORM(oill);
   RXY_FORM(pfd);
   RXY_FORM(dsgf);
   RXY_FORM(msgf);
   RXY_FORM(dsg);
   RXE_FORM(sdb);
   RXY_FORM(slgf);
   RS1_FORM(srdl);
-  RX_FORM(ste);
   RXY_FORM(stey);
   RXY_FORM(strv);
   RXY_FORM(strvh);
   RXY_FORM(strvg);
   RI1_FORM(tmll);
   SS1_FORM(tr);
   S_FORM(ts);
 
   // Load Address Instructions
-  void la(Register r, const MemOperand& opnd);
   void lay(Register r, const MemOperand& opnd);
   void larl(Register r, Label* l);
 
   // Load Instructions
   void lb(Register r, const MemOperand& src);
   void lgb(Register r, const MemOperand& src);
-  void lh(Register r, const MemOperand& src);
   void lhy(Register r, const MemOperand& src);
   void lgh(Register r, const MemOperand& src);
-  void l(Register r, const MemOperand& src);
   void ly(Register r, const MemOperand& src);
   void lg(Register r, const MemOperand& src);
   void lgf(Register r, const MemOperand& src);
   void lhi(Register r, const Operand& imm);
   void lghi(Register r, const Operand& imm);
 
   // Load And Test Instructions
   void lt_z(Register r, const MemOperand& src);
   void ltg(Register r, const MemOperand& src);
 
   // Load Logical Instructions
   void llc(Register r, const MemOperand& src);
   void llgc(Register r, const MemOperand& src);
   void llgf(Register r, const MemOperand& src);
   void llh(Register r, const MemOperand& src);
   void llgh(Register r, const MemOperand& src);
 
   // Load Multiple Instructions
   void lm(Register r1, Register r2, const MemOperand& src);
   void lmy(Register r1, Register r2, const MemOperand& src);
   void lmg(Register r1, Register r2, const MemOperand& src);
 
   // Load On Condition Instructions
   void locr(Condition m3, Register r1, Register r2);
   void locgr(Condition m3, Register r1, Register r2);
   void loc(Condition m3, Register r1, const MemOperand& src);
   void locg(Condition m3, Register r1, const MemOperand& src);
 
   // Store Instructions
-  void st(Register r, const MemOperand& src);
-  void stc(Register r, const MemOperand& src);
   void stcy(Register r, const MemOperand& src);
   void stg(Register r, const MemOperand& src);
-  void sth(Register r, const MemOperand& src);
   void sthy(Register r, const MemOperand& src);
   void sty(Register r, const MemOperand& src);
 
   // Store Multiple Instructions
   void stm(Register r1, Register r2, const MemOperand& src);
   void stmy(Register r1, Register r2, const MemOperand& src);
   void stmg(Register r1, Register r2, const MemOperand& src);
 
   // Compare Instructions
-  void c(Register r, const MemOperand& opnd);
   void cy(Register r, const MemOperand& opnd);
   void cg(Register r, const MemOperand& opnd);
-  void ch(Register r, const MemOperand& opnd);
   void chy(Register r, const MemOperand& opnd);
   void chi(Register r, const Operand& opnd);
   void cghi(Register r, const Operand& opnd);
 
   // Compare Logical Instructions
-  void cl(Register r, const MemOperand& opnd);
   void cly(Register r, const MemOperand& opnd);
   void clg(Register r, const MemOperand& opnd);
   void cli(const MemOperand& mem, const Operand& imm);
   void cliy(const MemOperand& mem, const Operand& imm);
   void clc(const MemOperand& opnd1, const MemOperand& opnd2, Length length);
 
   // Test Under Mask Instructions
   void tm(const MemOperand& mem, const Operand& imm);
   void tmy(const MemOperand& mem, const Operand& imm);
 
@@ skipping 43 matching lines @@
              const Operand& endBit, const Operand& shiftAmt,
              bool zeroBits = true);
   void risbgn(Register dst, Register src, const Operand& startBit,
               const Operand& endBit, const Operand& shiftAmt,
               bool zeroBits = true);
 
   // Move Character (Mem to Mem)
   void mvc(const MemOperand& opnd1, const MemOperand& opnd2, uint32_t length);
 
   // Branch Instructions
-  void bct(Register r, const MemOperand& opnd);
   void bctg(Register r, const MemOperand& opnd);
   void bras(Register r, const Operand& opnd);
   void brc(Condition c, const Operand& opnd);
   void brct(Register r1, const Operand& opnd);
   void brctg(Register r1, const Operand& opnd);
 
   // 32-bit Add Instructions
-  void a(Register r1, const MemOperand& opnd);
   void ay(Register r1, const MemOperand& opnd);
-  void ah(Register r1, const MemOperand& opnd);
   void ahy(Register r1, const MemOperand& opnd);
   void ahi(Register r1, const Operand& opnd);
   void ahik(Register r1, Register r3, const Operand& opnd);
   void ark(Register r1, Register r2, Register r3);
   void asi(const MemOperand&, const Operand&);
 
   // 64-bit Add Instructions
   void ag(Register r1, const MemOperand& opnd);
   void agf(Register r1, const MemOperand& opnd);
   void aghi(Register r1, const Operand& opnd);
   void aghik(Register r1, Register r3, const Operand& opnd);
   void agrk(Register r1, Register r2, Register r3);
   void agsi(const MemOperand&, const Operand&);
 
   // 32-bit Add Logical Instructions
-  void al_z(Register r1, const MemOperand& opnd);
   void aly(Register r1, const MemOperand& opnd);
   void alrk(Register r1, Register r2, Register r3);
 
   // 64-bit Add Logical Instructions
   void alg(Register r1, const MemOperand& opnd);
   void algrk(Register r1, Register r2, Register r3);
 
   // 32-bit Subtract Instructions
-  void s(Register r1, const MemOperand& opnd);
   void sy(Register r1, const MemOperand& opnd);
-  void sh(Register r1, const MemOperand& opnd);
   void shy(Register r1, const MemOperand& opnd);
   void srk(Register r1, Register r2, Register r3);
 
   // 64-bit Subtract Instructions
   void sg(Register r1, const MemOperand& opnd);
   void sgf(Register r1, const MemOperand& opnd);
   void sgrk(Register r1, Register r2, Register r3);
 
   // 32-bit Subtract Logical Instructions
-  void sl(Register r1, const MemOperand& opnd);
   void sly(Register r1, const MemOperand& opnd);
   void slrk(Register r1, Register r2, Register r3);
 
   // 64-bit Subtract Logical Instructions
   void slg(Register r1, const MemOperand& opnd);
   void slgrk(Register r1, Register r2, Register r3);
 
   // 32-bit Multiply Instructions
-  void m(Register r1, const MemOperand& opnd);
   void mfy(Register r1, const MemOperand& opnd);
   void ml(Register r1, const MemOperand& opnd);
-  void ms(Register r1, const MemOperand& opnd);
   void msy(Register r1, const MemOperand& opnd);
-  void mh(Register r1, const MemOperand& opnd);
   void mhy(Register r1, const MemOperand& opnd);
   void mhi(Register r1, const Operand& opnd);
 
   // 64-bit Multiply Instructions
   void mlg(Register r1, const MemOperand& opnd);
   void mghi(Register r1, const Operand& opnd);
   void msg(Register r1, const MemOperand& opnd);
 
   // 32-bit Divide Instructions
-  void d(Register r1, const MemOperand& opnd);
   void dl(Register r1, const MemOperand& opnd);
 
   // Bitwise Instructions (AND / OR / XOR)
-  void n(Register r1, const MemOperand& opnd);
   void ny(Register r1, const MemOperand& opnd);
   void nrk(Register r1, Register r2, Register r3);
   void ng(Register r1, const MemOperand& opnd);
   void ngrk(Register r1, Register r2, Register r3);
-  void o(Register r1, const MemOperand& opnd);
   void oy(Register r1, const MemOperand& opnd);
   void ork(Register r1, Register r2, Register r3);
   void og(Register r1, const MemOperand& opnd);
   void ogrk(Register r1, Register r2, Register r3);
-  void x(Register r1, const MemOperand& opnd);
   void xy(Register r1, const MemOperand& opnd);
   void xrk(Register r1, Register r2, Register r3);
   void xg(Register r1, const MemOperand& opnd);
   void xgrk(Register r1, Register r2, Register r3);
   void xc(const MemOperand& opnd1, const MemOperand& opnd2, Length length);
 
   // Floating Point Load / Store Instructions
-  void ld(DoubleRegister r1, const MemOperand& opnd);
   void ldy(DoubleRegister r1, const MemOperand& opnd);
-  void le_z(DoubleRegister r1, const MemOperand& opnd);
   void ley(DoubleRegister r1, const MemOperand& opnd);
-  void std(DoubleRegister r1, const MemOperand& opnd);
   void stdy(DoubleRegister r1, const MemOperand& opnd);
-  void ste(DoubleRegister r1, const MemOperand& opnd);
   void stey(DoubleRegister r1, const MemOperand& opnd);
 
   // Floating <-> Fixed Point Conversion Instructions
   void cdlfbr(Condition m3, Condition m4, DoubleRegister fltReg,
               Register fixReg);
   void cdlgbr(Condition m3, Condition m4, DoubleRegister fltReg,
               Register fixReg);
   void celgbr(Condition m3, Condition m4, DoubleRegister fltReg,
               Register fixReg);
   void celfbr(Condition m3, Condition m4, DoubleRegister fltReg,
@@ skipping 198 matching lines @@
 
   // Helpers to emit binary encoding of 2/4/6 byte instructions.
   inline void emit2bytes(uint16_t x);
   inline void emit4bytes(uint32_t x);
   inline void emit6bytes(uint64_t x);
 
   // Helpers to emit binary encoding for various instruction formats.
 
   inline void rr2_form(uint8_t op, Condition m1, Register r2);
 
-  inline void rx_form(Opcode op, Register r1, Register x2, Register b2,
-                      Disp d2);
-  inline void rx_form(Opcode op, DoubleRegister r1, Register x2, Register b2,
-                      Disp d2);
-
   inline void ri_form(Opcode op, Register r1, const Operand& i2);
   inline void ri_form(Opcode op, Condition m1, const Operand& i2);
 
   inline void rie_form(Opcode op, Register r1, Register r3, const Operand& i2);
   inline void rie_f_form(Opcode op, Register r1, Register r2, const Operand& i3,
                          const Operand& i4, const Operand& i5);
 
   inline void ris_form(Opcode op, Register r1, Condition m3, Register b4,
                        Disp d4, const Operand& i2);
 
@@ skipping 68 matching lines @@
 
 class EnsureSpace BASE_EMBEDDED {
  public:
   explicit EnsureSpace(Assembler* assembler) { assembler->CheckBuffer(); }
 };
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_S390_ASSEMBLER_S390_H_