OLD | NEW |
1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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585 break; | 585 break; |
586 case DEBUG_BREAK_NOP: | 586 case DEBUG_BREAK_NOP: |
587 // TODO(john.yan): Use a better NOP break | 587 // TODO(john.yan): Use a better NOP break |
588 oill(r3, Operand::Zero()); | 588 oill(r3, Operand::Zero()); |
589 break; | 589 break; |
590 default: | 590 default: |
591 UNIMPLEMENTED(); | 591 UNIMPLEMENTED(); |
592 } | 592 } |
593 } | 593 } |
594 | 594 |
595 // RX format: <insn> R1,D2(X2,B2) | |
596 // +--------+----+----+----+-------------+ | |
597 // | OpCode | R1 | X2 | B2 | D2 | | |
598 // +--------+----+----+----+-------------+ | |
599 // 0 8 12 16 20 31 | |
600 #define RX_FORM_EMIT(name, op) \ | |
601 void Assembler::name(Register r, const MemOperand& opnd) { \ | |
602 name(r, opnd.getIndexRegister(), opnd.getBaseRegister(), \ | |
603 opnd.getDisplacement()); \ | |
604 } \ | |
605 void Assembler::name(Register r1, Register x2, Register b2, Disp d2) { \ | |
606 rx_form(op, r1, x2, b2, d2); \ | |
607 } | |
608 void Assembler::rx_form(Opcode op, Register r1, Register x2, Register b2, | |
609 Disp d2) { | |
610 DCHECK(is_uint8(op)); | |
611 DCHECK(is_uint12(d2)); | |
612 emit4bytes(op * B24 | r1.code() * B20 | x2.code() * B16 | b2.code() * B12 | | |
613 d2); | |
614 } | |
615 | 595 |
616 void Assembler::rx_form(Opcode op, DoubleRegister r1, Register x2, Register b2, | |
617 Disp d2) { | |
618 DCHECK(is_uint8(op)); | |
619 DCHECK(is_uint12(d2)); | |
620 emit4bytes(op * B24 | r1.code() * B20 | x2.code() * B16 | b2.code() * B12 | | |
621 d2); | |
622 } | |
623 | 596 |
624 // RI1 format: <insn> R1,I2 | 597 // RI1 format: <insn> R1,I2 |
625 // +--------+----+----+------------------+ | 598 // +--------+----+----+------------------+ |
626 // | OpCode | R1 |OpCd| I2 | | 599 // | OpCode | R1 |OpCd| I2 | |
627 // +--------+----+----+------------------+ | 600 // +--------+----+----+------------------+ |
628 // 0 8 12 16 31 | 601 // 0 8 12 16 31 |
629 #define RI1_FORM_EMIT(name, op) \ | 602 #define RI1_FORM_EMIT(name, op) \ |
630 void Assembler::name(Register r, const Operand& i2) { ri_form(op, r, i2); } | 603 void Assembler::name(Register r, const Operand& i2) { ri_form(op, r, i2); } |
631 | 604 |
632 void Assembler::ri_form(Opcode op, Register r1, const Operand& i2) { | 605 void Assembler::ri_form(Opcode op, Register r1, const Operand& i2) { |
(...skipping 688 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1321 // 0 16 20 24 28 31 | 1294 // 0 16 20 24 28 31 |
1322 void Assembler::rrfe_form(Opcode op, Condition m3, Condition m4, Register r1, | 1295 void Assembler::rrfe_form(Opcode op, Condition m3, Condition m4, Register r1, |
1323 Register r2) { | 1296 Register r2) { |
1324 uint32_t code = op << 16 | m3 * B12 | m4 * B8 | r1.code() * B4 | r2.code(); | 1297 uint32_t code = op << 16 | m3 * B12 | m4 * B8 | r1.code() * B4 | r2.code(); |
1325 emit4bytes(code); | 1298 emit4bytes(code); |
1326 } | 1299 } |
1327 | 1300 |
1328 // end of S390 Instruction generation | 1301 // end of S390 Instruction generation |
1329 | 1302 |
1330 // start of S390 instruction | 1303 // start of S390 instruction |
1331 RX_FORM_EMIT(bc, BC) | |
1332 RXE_FORM_EMIT(ceb, CEB) | 1304 RXE_FORM_EMIT(ceb, CEB) |
1333 SS1_FORM_EMIT(ed, ED) | 1305 SS1_FORM_EMIT(ed, ED) |
1334 RX_FORM_EMIT(ex, EX) | |
1335 RX_FORM_EMIT(le_z, LE) | |
1336 RXY_FORM_EMIT(ley, LEY) | 1306 RXY_FORM_EMIT(ley, LEY) |
1337 RXY_FORM_EMIT(lrv, LRV) | 1307 RXY_FORM_EMIT(lrv, LRV) |
1338 RXY_FORM_EMIT(lrvg, LRVG) | 1308 RXY_FORM_EMIT(lrvg, LRVG) |
1339 RXY_FORM_EMIT(lrvh, LRVH) | 1309 RXY_FORM_EMIT(lrvh, LRVH) |
1340 SS1_FORM_EMIT(mvn, MVN) | 1310 SS1_FORM_EMIT(mvn, MVN) |
1341 SS1_FORM_EMIT(nc, NC) | 1311 SS1_FORM_EMIT(nc, NC) |
1342 SI_FORM_EMIT(ni, NI) | 1312 SI_FORM_EMIT(ni, NI) |
1343 RI1_FORM_EMIT(nilh, NILH) | 1313 RI1_FORM_EMIT(nilh, NILH) |
1344 RI1_FORM_EMIT(nill, NILL) | 1314 RI1_FORM_EMIT(nill, NILL) |
1345 RI1_FORM_EMIT(oill, OILL) | 1315 RI1_FORM_EMIT(oill, OILL) |
1346 RXY_FORM_EMIT(pfd, PFD) | 1316 RXY_FORM_EMIT(pfd, PFD) |
1347 RXY_FORM_EMIT(slgf, SLGF) | 1317 RXY_FORM_EMIT(slgf, SLGF) |
1348 RXY_FORM_EMIT(strvh, STRVH) | 1318 RXY_FORM_EMIT(strvh, STRVH) |
1349 RXY_FORM_EMIT(strv, STRV) | 1319 RXY_FORM_EMIT(strv, STRV) |
1350 RXY_FORM_EMIT(strvg, STRVG) | 1320 RXY_FORM_EMIT(strvg, STRVG) |
1351 RI1_FORM_EMIT(tmll, TMLL) | 1321 RI1_FORM_EMIT(tmll, TMLL) |
1352 SS1_FORM_EMIT(tr, TR) | 1322 SS1_FORM_EMIT(tr, TR) |
1353 S_FORM_EMIT(ts, TS) | 1323 S_FORM_EMIT(ts, TS) |
1354 | 1324 |
1355 // ------------------------- | 1325 // ------------------------- |
1356 // Load Address Instructions | 1326 // Load Address Instructions |
1357 // ------------------------- | 1327 // ------------------------- |
1358 // Load Address Register-Storage | 1328 // Load Address Register-Storage |
1359 void Assembler::la(Register r1, const MemOperand& opnd) { | |
1360 rx_form(LA, r1, opnd.rx(), opnd.rb(), opnd.offset()); | |
1361 } | |
1362 | |
1363 // Load Address Register-Storage | |
1364 void Assembler::lay(Register r1, const MemOperand& opnd) { | 1329 void Assembler::lay(Register r1, const MemOperand& opnd) { |
1365 rxy_form(LAY, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 1330 rxy_form(LAY, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
1366 } | 1331 } |
1367 | 1332 |
1368 // Load Address Relative Long | 1333 // Load Address Relative Long |
1369 void Assembler::larl(Register r1, Label* l) { | 1334 void Assembler::larl(Register r1, Label* l) { |
1370 larl(r1, Operand(branch_offset(l))); | 1335 larl(r1, Operand(branch_offset(l))); |
1371 } | 1336 } |
1372 | 1337 |
1373 // ----------------- | 1338 // ----------------- |
1374 // Load Instructions | 1339 // Load Instructions |
1375 // ----------------- | 1340 // ----------------- |
1376 // Load Byte Register-Storage (32<-8) | 1341 // Load Byte Register-Storage (32<-8) |
1377 void Assembler::lb(Register r, const MemOperand& src) { | 1342 void Assembler::lb(Register r, const MemOperand& src) { |
1378 rxy_form(LB, r, src.rx(), src.rb(), src.offset()); | 1343 rxy_form(LB, r, src.rx(), src.rb(), src.offset()); |
1379 } | 1344 } |
1380 | 1345 |
1381 // Load Byte Register-Storage (64<-8) | 1346 // Load Byte Register-Storage (64<-8) |
1382 void Assembler::lgb(Register r, const MemOperand& src) { | 1347 void Assembler::lgb(Register r, const MemOperand& src) { |
1383 rxy_form(LGB, r, src.rx(), src.rb(), src.offset()); | 1348 rxy_form(LGB, r, src.rx(), src.rb(), src.offset()); |
1384 } | 1349 } |
1385 | 1350 |
1386 // Load Halfword Register-Storage (32<-16) | 1351 // Load Halfword Register-Storage (32<-16) |
1387 void Assembler::lh(Register r, const MemOperand& src) { | |
1388 rx_form(LH, r, src.rx(), src.rb(), src.offset()); | |
1389 } | |
1390 | |
1391 // Load Halfword Register-Storage (32<-16) | |
1392 void Assembler::lhy(Register r, const MemOperand& src) { | 1352 void Assembler::lhy(Register r, const MemOperand& src) { |
1393 rxy_form(LHY, r, src.rx(), src.rb(), src.offset()); | 1353 rxy_form(LHY, r, src.rx(), src.rb(), src.offset()); |
1394 } | 1354 } |
1395 | 1355 |
1396 // Load Halfword Register-Storage (64<-16) | 1356 // Load Halfword Register-Storage (64<-16) |
1397 void Assembler::lgh(Register r, const MemOperand& src) { | 1357 void Assembler::lgh(Register r, const MemOperand& src) { |
1398 rxy_form(LGH, r, src.rx(), src.rb(), src.offset()); | 1358 rxy_form(LGH, r, src.rx(), src.rb(), src.offset()); |
1399 } | 1359 } |
1400 | 1360 |
1401 // Load Register-Storage (32) | 1361 // Load Register-Storage (32) |
1402 void Assembler::l(Register r, const MemOperand& src) { | |
1403 rx_form(L, r, src.rx(), src.rb(), src.offset()); | |
1404 } | |
1405 | |
1406 // Load Register-Storage (32) | |
1407 void Assembler::ly(Register r, const MemOperand& src) { | 1362 void Assembler::ly(Register r, const MemOperand& src) { |
1408 rxy_form(LY, r, src.rx(), src.rb(), src.offset()); | 1363 rxy_form(LY, r, src.rx(), src.rb(), src.offset()); |
1409 } | 1364 } |
1410 | 1365 |
1411 // Load Register-Storage (64) | 1366 // Load Register-Storage (64) |
1412 void Assembler::lg(Register r, const MemOperand& src) { | 1367 void Assembler::lg(Register r, const MemOperand& src) { |
1413 rxy_form(LG, r, src.rx(), src.rb(), src.offset()); | 1368 rxy_form(LG, r, src.rx(), src.rb(), src.offset()); |
1414 } | 1369 } |
1415 | 1370 |
1416 // Load Register-Storage (64<-32) | 1371 // Load Register-Storage (64<-32) |
(...skipping 64 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1481 } | 1436 } |
1482 | 1437 |
1483 // Load On Condition R-M (64) | 1438 // Load On Condition R-M (64) |
1484 void Assembler::locg(Condition m3, Register r1, const MemOperand& src) { | 1439 void Assembler::locg(Condition m3, Register r1, const MemOperand& src) { |
1485 rxy_form(LOCG, r1, m3, src.rb(), src.offset()); | 1440 rxy_form(LOCG, r1, m3, src.rb(), src.offset()); |
1486 } | 1441 } |
1487 | 1442 |
1488 // ------------------- | 1443 // ------------------- |
1489 // Branch Instructions | 1444 // Branch Instructions |
1490 // ------------------- | 1445 // ------------------- |
1491 | |
1492 // Branch on Count (32) | |
1493 void Assembler::bct(Register r, const MemOperand& opnd) { | |
1494 rx_form(BCT, r, opnd.rx(), opnd.rb(), opnd.offset()); | |
1495 } | |
1496 | |
1497 // Branch on Count (64) | 1446 // Branch on Count (64) |
1498 void Assembler::bctg(Register r, const MemOperand& opnd) { | 1447 void Assembler::bctg(Register r, const MemOperand& opnd) { |
1499 rxy_form(BCTG, r, opnd.rx(), opnd.rb(), opnd.offset()); | 1448 rxy_form(BCTG, r, opnd.rx(), opnd.rb(), opnd.offset()); |
1500 } | 1449 } |
1501 | 1450 |
1502 // Branch Relative and Save (32) | 1451 // Branch Relative and Save (32) |
1503 void Assembler::bras(Register r, const Operand& opnd) { | 1452 void Assembler::bras(Register r, const Operand& opnd) { |
1504 ri_form(BRAS, r, opnd); | 1453 ri_form(BRAS, r, opnd); |
1505 } | 1454 } |
1506 | 1455 |
(...skipping 15 matching lines...) Expand all Loading... |
1522 int16_t numHalfwords = static_cast<int16_t>(imm.immediate()) / 2; | 1471 int16_t numHalfwords = static_cast<int16_t>(imm.immediate()) / 2; |
1523 Operand halfwordOp = Operand(numHalfwords); | 1472 Operand halfwordOp = Operand(numHalfwords); |
1524 halfwordOp.setBits(16); | 1473 halfwordOp.setBits(16); |
1525 ri_form(BRCTG, r1, halfwordOp); | 1474 ri_form(BRCTG, r1, halfwordOp); |
1526 } | 1475 } |
1527 | 1476 |
1528 // -------------------- | 1477 // -------------------- |
1529 // Compare Instructions | 1478 // Compare Instructions |
1530 // -------------------- | 1479 // -------------------- |
1531 // Compare Register-Storage (32) | 1480 // Compare Register-Storage (32) |
1532 void Assembler::c(Register r, const MemOperand& opnd) { | |
1533 rx_form(C, r, opnd.rx(), opnd.rb(), opnd.offset()); | |
1534 } | |
1535 | |
1536 // Compare Register-Storage (32) | |
1537 void Assembler::cy(Register r, const MemOperand& opnd) { | 1481 void Assembler::cy(Register r, const MemOperand& opnd) { |
1538 rxy_form(CY, r, opnd.rx(), opnd.rb(), opnd.offset()); | 1482 rxy_form(CY, r, opnd.rx(), opnd.rb(), opnd.offset()); |
1539 } | 1483 } |
1540 | 1484 |
1541 // Compare Register-Storage (64) | 1485 // Compare Register-Storage (64) |
1542 void Assembler::cg(Register r, const MemOperand& opnd) { | 1486 void Assembler::cg(Register r, const MemOperand& opnd) { |
1543 rxy_form(CG, r, opnd.rx(), opnd.rb(), opnd.offset()); | 1487 rxy_form(CG, r, opnd.rx(), opnd.rb(), opnd.offset()); |
1544 } | 1488 } |
1545 | 1489 |
1546 // Compare Halfword Register-Storage (32) | 1490 // Compare Halfword Register-Storage (32) |
1547 void Assembler::ch(Register r, const MemOperand& opnd) { | |
1548 rx_form(CH, r, opnd.rx(), opnd.rb(), opnd.offset()); | |
1549 } | |
1550 | |
1551 // Compare Halfword Register-Storage (32) | |
1552 void Assembler::chy(Register r, const MemOperand& opnd) { | 1491 void Assembler::chy(Register r, const MemOperand& opnd) { |
1553 rxy_form(CHY, r, opnd.rx(), opnd.rb(), opnd.offset()); | 1492 rxy_form(CHY, r, opnd.rx(), opnd.rb(), opnd.offset()); |
1554 } | 1493 } |
1555 | 1494 |
1556 // Compare Halfword Immediate (32) | 1495 // Compare Halfword Immediate (32) |
1557 void Assembler::chi(Register r, const Operand& opnd) { ri_form(CHI, r, opnd); } | 1496 void Assembler::chi(Register r, const Operand& opnd) { ri_form(CHI, r, opnd); } |
1558 | 1497 |
1559 // Compare Halfword Immediate (64) | 1498 // Compare Halfword Immediate (64) |
1560 void Assembler::cghi(Register r, const Operand& opnd) { | 1499 void Assembler::cghi(Register r, const Operand& opnd) { |
1561 ri_form(CGHI, r, opnd); | 1500 ri_form(CGHI, r, opnd); |
1562 } | 1501 } |
1563 | 1502 |
1564 // ---------------------------- | 1503 // ---------------------------- |
1565 // Compare Logical Instructions | 1504 // Compare Logical Instructions |
1566 // ---------------------------- | 1505 // ---------------------------- |
1567 // Compare Logical Register-Storage (32) | 1506 // Compare Logical Register-Storage (32) |
1568 void Assembler::cl(Register r, const MemOperand& opnd) { | |
1569 rx_form(CL, r, opnd.rx(), opnd.rb(), opnd.offset()); | |
1570 } | |
1571 | |
1572 // Compare Logical Register-Storage (32) | |
1573 void Assembler::cly(Register r, const MemOperand& opnd) { | 1507 void Assembler::cly(Register r, const MemOperand& opnd) { |
1574 rxy_form(CLY, r, opnd.rx(), opnd.rb(), opnd.offset()); | 1508 rxy_form(CLY, r, opnd.rx(), opnd.rb(), opnd.offset()); |
1575 } | 1509 } |
1576 | 1510 |
1577 // Compare Logical Register-Storage (64) | 1511 // Compare Logical Register-Storage (64) |
1578 void Assembler::clg(Register r, const MemOperand& opnd) { | 1512 void Assembler::clg(Register r, const MemOperand& opnd) { |
1579 rxy_form(CLG, r, opnd.rx(), opnd.rb(), opnd.offset()); | 1513 rxy_form(CLG, r, opnd.rx(), opnd.rb(), opnd.offset()); |
1580 } | 1514 } |
1581 | 1515 |
1582 // Compare Immediate (Mem - Imm) (8) | 1516 // Compare Immediate (Mem - Imm) (8) |
(...skipping 60 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1643 void Assembler::mvc(const MemOperand& opnd1, const MemOperand& opnd2, | 1577 void Assembler::mvc(const MemOperand& opnd1, const MemOperand& opnd2, |
1644 uint32_t length) { | 1578 uint32_t length) { |
1645 ss_form(MVC, length - 1, opnd1.getBaseRegister(), opnd1.getDisplacement(), | 1579 ss_form(MVC, length - 1, opnd1.getBaseRegister(), opnd1.getDisplacement(), |
1646 opnd2.getBaseRegister(), opnd2.getDisplacement()); | 1580 opnd2.getBaseRegister(), opnd2.getDisplacement()); |
1647 } | 1581 } |
1648 | 1582 |
1649 // ----------------------- | 1583 // ----------------------- |
1650 // 32-bit Add Instructions | 1584 // 32-bit Add Instructions |
1651 // ----------------------- | 1585 // ----------------------- |
1652 // Add Register-Storage (32) | 1586 // Add Register-Storage (32) |
1653 void Assembler::a(Register r1, const MemOperand& opnd) { | |
1654 rx_form(A, r1, opnd.rx(), opnd.rb(), opnd.offset()); | |
1655 } | |
1656 | |
1657 // Add Register-Storage (32) | |
1658 void Assembler::ay(Register r1, const MemOperand& opnd) { | 1587 void Assembler::ay(Register r1, const MemOperand& opnd) { |
1659 rxy_form(AY, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 1588 rxy_form(AY, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
1660 } | 1589 } |
1661 | 1590 |
1662 // Add Halfword Register-Storage (32) | 1591 // Add Halfword Register-Storage (32) |
1663 void Assembler::ah(Register r1, const MemOperand& opnd) { | |
1664 rx_form(AH, r1, opnd.rx(), opnd.rb(), opnd.offset()); | |
1665 } | |
1666 | |
1667 // Add Halfword Register-Storage (32) | |
1668 void Assembler::ahy(Register r1, const MemOperand& opnd) { | 1592 void Assembler::ahy(Register r1, const MemOperand& opnd) { |
1669 rxy_form(AHY, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 1593 rxy_form(AHY, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
1670 } | 1594 } |
1671 | 1595 |
1672 // Add Halfword Immediate (32) | 1596 // Add Halfword Immediate (32) |
1673 void Assembler::ahi(Register r1, const Operand& i2) { ri_form(AHI, r1, i2); } | 1597 void Assembler::ahi(Register r1, const Operand& i2) { ri_form(AHI, r1, i2); } |
1674 | 1598 |
1675 // Add Halfword Immediate (32) | 1599 // Add Halfword Immediate (32) |
1676 void Assembler::ahik(Register r1, Register r3, const Operand& i2) { | 1600 void Assembler::ahik(Register r1, Register r3, const Operand& i2) { |
1677 rie_form(AHIK, r1, r3, i2); | 1601 rie_form(AHIK, r1, r3, i2); |
(...skipping 41 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1719 void Assembler::agsi(const MemOperand& opnd, const Operand& imm) { | 1643 void Assembler::agsi(const MemOperand& opnd, const Operand& imm) { |
1720 DCHECK(is_int8(imm.imm_)); | 1644 DCHECK(is_int8(imm.imm_)); |
1721 DCHECK(is_int20(opnd.offset())); | 1645 DCHECK(is_int20(opnd.offset())); |
1722 siy_form(AGSI, Operand(0xff & imm.imm_), opnd.rb(), 0xfffff & opnd.offset()); | 1646 siy_form(AGSI, Operand(0xff & imm.imm_), opnd.rb(), 0xfffff & opnd.offset()); |
1723 } | 1647 } |
1724 | 1648 |
1725 // ------------------------------- | 1649 // ------------------------------- |
1726 // 32-bit Add Logical Instructions | 1650 // 32-bit Add Logical Instructions |
1727 // ------------------------------- | 1651 // ------------------------------- |
1728 // Add Logical Register-Storage (32) | 1652 // Add Logical Register-Storage (32) |
1729 void Assembler::al_z(Register r1, const MemOperand& opnd) { | |
1730 rx_form(AL, r1, opnd.rx(), opnd.rb(), opnd.offset()); | |
1731 } | |
1732 | |
1733 // Add Logical Register-Storage (32) | |
1734 void Assembler::aly(Register r1, const MemOperand& opnd) { | 1653 void Assembler::aly(Register r1, const MemOperand& opnd) { |
1735 rxy_form(ALY, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 1654 rxy_form(ALY, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
1736 } | 1655 } |
1737 | 1656 |
1738 // Add Logical Register-Register-Register (32) | 1657 // Add Logical Register-Register-Register (32) |
1739 void Assembler::alrk(Register r1, Register r2, Register r3) { | 1658 void Assembler::alrk(Register r1, Register r2, Register r3) { |
1740 rrf1_form(ALRK, r1, r2, r3); | 1659 rrf1_form(ALRK, r1, r2, r3); |
1741 } | 1660 } |
1742 | 1661 |
1743 // ------------------------------- | 1662 // ------------------------------- |
1744 // 64-bit Add Logical Instructions | 1663 // 64-bit Add Logical Instructions |
1745 // ------------------------------- | 1664 // ------------------------------- |
1746 // Add Logical Register-Storage (64) | 1665 // Add Logical Register-Storage (64) |
1747 void Assembler::alg(Register r1, const MemOperand& opnd) { | 1666 void Assembler::alg(Register r1, const MemOperand& opnd) { |
1748 rxy_form(ALG, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 1667 rxy_form(ALG, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
1749 } | 1668 } |
1750 | 1669 |
1751 // Add Logical Register-Register-Register (64) | 1670 // Add Logical Register-Register-Register (64) |
1752 void Assembler::algrk(Register r1, Register r2, Register r3) { | 1671 void Assembler::algrk(Register r1, Register r2, Register r3) { |
1753 rrf1_form(ALGRK, r1, r2, r3); | 1672 rrf1_form(ALGRK, r1, r2, r3); |
1754 } | 1673 } |
1755 | 1674 |
1756 // ---------------------------- | 1675 // ---------------------------- |
1757 // 32-bit Subtract Instructions | 1676 // 32-bit Subtract Instructions |
1758 // ---------------------------- | 1677 // ---------------------------- |
1759 // Subtract Register-Storage (32) | 1678 // Subtract Register-Storage (32) |
1760 void Assembler::s(Register r1, const MemOperand& opnd) { | |
1761 rx_form(S, r1, opnd.rx(), opnd.rb(), opnd.offset()); | |
1762 } | |
1763 | |
1764 // Subtract Register-Storage (32) | |
1765 void Assembler::sy(Register r1, const MemOperand& opnd) { | 1679 void Assembler::sy(Register r1, const MemOperand& opnd) { |
1766 rxy_form(SY, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 1680 rxy_form(SY, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
1767 } | 1681 } |
1768 | 1682 |
1769 // Subtract Halfword Register-Storage (32) | 1683 // Subtract Halfword Register-Storage (32) |
1770 void Assembler::sh(Register r1, const MemOperand& opnd) { | |
1771 rx_form(SH, r1, opnd.rx(), opnd.rb(), opnd.offset()); | |
1772 } | |
1773 | |
1774 // Subtract Halfword Register-Storage (32) | |
1775 void Assembler::shy(Register r1, const MemOperand& opnd) { | 1684 void Assembler::shy(Register r1, const MemOperand& opnd) { |
1776 rxy_form(SHY, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 1685 rxy_form(SHY, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
1777 } | 1686 } |
1778 | 1687 |
1779 // Subtract Register-Register-Register (32) | 1688 // Subtract Register-Register-Register (32) |
1780 void Assembler::srk(Register r1, Register r2, Register r3) { | 1689 void Assembler::srk(Register r1, Register r2, Register r3) { |
1781 rrf1_form(SRK, r1, r2, r3); | 1690 rrf1_form(SRK, r1, r2, r3); |
1782 } | 1691 } |
1783 | 1692 |
1784 // ---------------------------- | 1693 // ---------------------------- |
(...skipping 11 matching lines...) Expand all Loading... |
1796 | 1705 |
1797 // Subtract Register-Register-Register (64) | 1706 // Subtract Register-Register-Register (64) |
1798 void Assembler::sgrk(Register r1, Register r2, Register r3) { | 1707 void Assembler::sgrk(Register r1, Register r2, Register r3) { |
1799 rrf1_form(SGRK, r1, r2, r3); | 1708 rrf1_form(SGRK, r1, r2, r3); |
1800 } | 1709 } |
1801 | 1710 |
1802 // ------------------------------------ | 1711 // ------------------------------------ |
1803 // 32-bit Subtract Logical Instructions | 1712 // 32-bit Subtract Logical Instructions |
1804 // ------------------------------------ | 1713 // ------------------------------------ |
1805 // Subtract Logical Register-Storage (32) | 1714 // Subtract Logical Register-Storage (32) |
1806 void Assembler::sl(Register r1, const MemOperand& opnd) { | |
1807 rx_form(SL, r1, opnd.rx(), opnd.rb(), opnd.offset()); | |
1808 } | |
1809 | |
1810 // Subtract Logical Register-Storage (32) | |
1811 void Assembler::sly(Register r1, const MemOperand& opnd) { | 1715 void Assembler::sly(Register r1, const MemOperand& opnd) { |
1812 rxy_form(SLY, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 1716 rxy_form(SLY, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
1813 } | 1717 } |
1814 | 1718 |
1815 // Subtract Logical Register-Register-Register (32) | 1719 // Subtract Logical Register-Register-Register (32) |
1816 void Assembler::slrk(Register r1, Register r2, Register r3) { | 1720 void Assembler::slrk(Register r1, Register r2, Register r3) { |
1817 rrf1_form(SLRK, r1, r2, r3); | 1721 rrf1_form(SLRK, r1, r2, r3); |
1818 } | 1722 } |
1819 | 1723 |
1820 // ------------------------------------ | 1724 // ------------------------------------ |
1821 // 64-bit Subtract Logical Instructions | 1725 // 64-bit Subtract Logical Instructions |
1822 // ------------------------------------ | 1726 // ------------------------------------ |
1823 // Subtract Logical Register-Storage (64) | 1727 // Subtract Logical Register-Storage (64) |
1824 void Assembler::slg(Register r1, const MemOperand& opnd) { | 1728 void Assembler::slg(Register r1, const MemOperand& opnd) { |
1825 rxy_form(SLG, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 1729 rxy_form(SLG, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
1826 } | 1730 } |
1827 | 1731 |
1828 // Subtract Logical Register-Register-Register (64) | 1732 // Subtract Logical Register-Register-Register (64) |
1829 void Assembler::slgrk(Register r1, Register r2, Register r3) { | 1733 void Assembler::slgrk(Register r1, Register r2, Register r3) { |
1830 rrf1_form(SLGRK, r1, r2, r3); | 1734 rrf1_form(SLGRK, r1, r2, r3); |
1831 } | 1735 } |
1832 | 1736 |
1833 // ---------------------------- | 1737 // ---------------------------- |
1834 // 32-bit Multiply Instructions | 1738 // 32-bit Multiply Instructions |
1835 // ---------------------------- | 1739 // ---------------------------- |
1836 // Multiply Register-Storage (64<32) | |
1837 void Assembler::m(Register r1, const MemOperand& opnd) { | |
1838 DCHECK(r1.code() % 2 == 0); | |
1839 rx_form(M, r1, opnd.rx(), opnd.rb(), opnd.offset()); | |
1840 } | |
1841 | |
1842 void Assembler::mfy(Register r1, const MemOperand& opnd) { | 1740 void Assembler::mfy(Register r1, const MemOperand& opnd) { |
1843 DCHECK(r1.code() % 2 == 0); | 1741 DCHECK(r1.code() % 2 == 0); |
1844 rxy_form(MFY, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 1742 rxy_form(MFY, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
1845 } | 1743 } |
1846 | 1744 |
1847 // Multiply Logical Register-Storage (64<32) | 1745 // Multiply Logical Register-Storage (64<32) |
1848 void Assembler::ml(Register r1, const MemOperand& opnd) { | 1746 void Assembler::ml(Register r1, const MemOperand& opnd) { |
1849 rxy_form(ML, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 1747 rxy_form(ML, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
1850 } | 1748 } |
1851 | 1749 |
1852 // Multiply Single Register-Storage (32) | 1750 // Multiply Single Register-Storage (32) |
1853 void Assembler::ms(Register r1, const MemOperand& opnd) { | |
1854 rx_form(MS, r1, opnd.rx(), opnd.rb(), opnd.offset()); | |
1855 } | |
1856 | |
1857 // Multiply Single Register-Storage (32) | |
1858 void Assembler::msy(Register r1, const MemOperand& opnd) { | 1751 void Assembler::msy(Register r1, const MemOperand& opnd) { |
1859 rxy_form(MSY, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 1752 rxy_form(MSY, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
1860 } | 1753 } |
1861 | 1754 |
1862 // Multiply Halfword Register-Storage (32) | 1755 // Multiply Halfword Register-Storage (32) |
1863 void Assembler::mh(Register r1, const MemOperand& opnd) { | |
1864 rx_form(MH, r1, opnd.rx(), opnd.rb(), opnd.offset()); | |
1865 } | |
1866 | |
1867 // Multiply Halfword Register-Storage (32) | |
1868 void Assembler::mhy(Register r1, const MemOperand& opnd) { | 1756 void Assembler::mhy(Register r1, const MemOperand& opnd) { |
1869 rxy_form(MHY, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 1757 rxy_form(MHY, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
1870 } | 1758 } |
1871 | 1759 |
1872 // Multiply Halfword Immediate (32) | 1760 // Multiply Halfword Immediate (32) |
1873 void Assembler::mhi(Register r1, const Operand& opnd) { | 1761 void Assembler::mhi(Register r1, const Operand& opnd) { |
1874 ri_form(MHI, r1, opnd); | 1762 ri_form(MHI, r1, opnd); |
1875 } | 1763 } |
1876 | 1764 |
1877 // ---------------------------- | 1765 // ---------------------------- |
(...skipping 14 matching lines...) Expand all Loading... |
1892 rxy_form(MSG, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 1780 rxy_form(MSG, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
1893 } | 1781 } |
1894 | 1782 |
1895 void Assembler::msgf(Register r1, const MemOperand& opnd) { | 1783 void Assembler::msgf(Register r1, const MemOperand& opnd) { |
1896 rxy_form(MSGF, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 1784 rxy_form(MSGF, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
1897 } | 1785 } |
1898 | 1786 |
1899 // -------------------------- | 1787 // -------------------------- |
1900 // 32-bit Divide Instructions | 1788 // 32-bit Divide Instructions |
1901 // -------------------------- | 1789 // -------------------------- |
1902 // Divide Register-Storage (32<-64) | |
1903 void Assembler::d(Register r1, const MemOperand& opnd) { | |
1904 rx_form(D, r1, opnd.rx(), opnd.rb(), opnd.offset()); | |
1905 } | |
1906 | |
1907 // Divide Logical Register-Storage (32<-64) | 1790 // Divide Logical Register-Storage (32<-64) |
1908 void Assembler::dl(Register r1, const MemOperand& opnd) { | 1791 void Assembler::dl(Register r1, const MemOperand& opnd) { |
1909 rxy_form(DL, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 1792 rxy_form(DL, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
1910 } | 1793 } |
1911 | 1794 |
1912 void Assembler::dsg(Register r1, const MemOperand& opnd) { | 1795 void Assembler::dsg(Register r1, const MemOperand& opnd) { |
1913 rxy_form(DSG, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 1796 rxy_form(DSG, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
1914 } | 1797 } |
1915 | 1798 |
1916 void Assembler::dsgf(Register r1, const MemOperand& opnd) { | 1799 void Assembler::dsgf(Register r1, const MemOperand& opnd) { |
1917 rxy_form(DSGF, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 1800 rxy_form(DSGF, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
1918 } | 1801 } |
1919 | 1802 |
1920 // -------------------- | 1803 // -------------------- |
1921 // Bitwise Instructions | 1804 // Bitwise Instructions |
1922 // -------------------- | 1805 // -------------------- |
1923 // AND Register-Storage (32) | 1806 // AND Register-Storage (32) |
1924 void Assembler::n(Register r1, const MemOperand& opnd) { | |
1925 rx_form(N, r1, opnd.rx(), opnd.rb(), opnd.offset()); | |
1926 } | |
1927 | |
1928 // AND Register-Storage (32) | |
1929 void Assembler::ny(Register r1, const MemOperand& opnd) { | 1807 void Assembler::ny(Register r1, const MemOperand& opnd) { |
1930 rxy_form(NY, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 1808 rxy_form(NY, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
1931 } | 1809 } |
1932 | 1810 |
1933 // AND Register-Register-Register (32) | 1811 // AND Register-Register-Register (32) |
1934 void Assembler::nrk(Register r1, Register r2, Register r3) { | 1812 void Assembler::nrk(Register r1, Register r2, Register r3) { |
1935 rrf1_form(NRK, r1, r2, r3); | 1813 rrf1_form(NRK, r1, r2, r3); |
1936 } | 1814 } |
1937 | 1815 |
1938 // AND Register-Storage (64) | 1816 // AND Register-Storage (64) |
1939 void Assembler::ng(Register r1, const MemOperand& opnd) { | 1817 void Assembler::ng(Register r1, const MemOperand& opnd) { |
1940 rxy_form(NG, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 1818 rxy_form(NG, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
1941 } | 1819 } |
1942 | 1820 |
1943 // AND Register-Register-Register (64) | 1821 // AND Register-Register-Register (64) |
1944 void Assembler::ngrk(Register r1, Register r2, Register r3) { | 1822 void Assembler::ngrk(Register r1, Register r2, Register r3) { |
1945 rrf1_form(NGRK, r1, r2, r3); | 1823 rrf1_form(NGRK, r1, r2, r3); |
1946 } | 1824 } |
1947 | 1825 |
1948 // OR Register-Storage (32) | 1826 // OR Register-Storage (32) |
1949 void Assembler::o(Register r1, const MemOperand& opnd) { | |
1950 rx_form(O, r1, opnd.rx(), opnd.rb(), opnd.offset()); | |
1951 } | |
1952 | |
1953 // OR Register-Storage (32) | |
1954 void Assembler::oy(Register r1, const MemOperand& opnd) { | 1827 void Assembler::oy(Register r1, const MemOperand& opnd) { |
1955 rxy_form(OY, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 1828 rxy_form(OY, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
1956 } | 1829 } |
1957 | 1830 |
1958 // OR Register-Register-Register (32) | 1831 // OR Register-Register-Register (32) |
1959 void Assembler::ork(Register r1, Register r2, Register r3) { | 1832 void Assembler::ork(Register r1, Register r2, Register r3) { |
1960 rrf1_form(ORK, r1, r2, r3); | 1833 rrf1_form(ORK, r1, r2, r3); |
1961 } | 1834 } |
1962 | 1835 |
1963 // OR Register-Storage (64) | 1836 // OR Register-Storage (64) |
1964 void Assembler::og(Register r1, const MemOperand& opnd) { | 1837 void Assembler::og(Register r1, const MemOperand& opnd) { |
1965 rxy_form(OG, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 1838 rxy_form(OG, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
1966 } | 1839 } |
1967 | 1840 |
1968 // OR Register-Register-Register (64) | 1841 // OR Register-Register-Register (64) |
1969 void Assembler::ogrk(Register r1, Register r2, Register r3) { | 1842 void Assembler::ogrk(Register r1, Register r2, Register r3) { |
1970 rrf1_form(OGRK, r1, r2, r3); | 1843 rrf1_form(OGRK, r1, r2, r3); |
1971 } | 1844 } |
1972 | 1845 |
1973 // XOR Register-Storage (32) | 1846 // XOR Register-Storage (32) |
1974 void Assembler::x(Register r1, const MemOperand& opnd) { | |
1975 rx_form(X, r1, opnd.rx(), opnd.rb(), opnd.offset()); | |
1976 } | |
1977 | |
1978 // XOR Register-Storage (32) | |
1979 void Assembler::xy(Register r1, const MemOperand& opnd) { | 1847 void Assembler::xy(Register r1, const MemOperand& opnd) { |
1980 rxy_form(XY, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 1848 rxy_form(XY, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
1981 } | 1849 } |
1982 | 1850 |
1983 // XOR Register-Register-Register (32) | 1851 // XOR Register-Register-Register (32) |
1984 void Assembler::xrk(Register r1, Register r2, Register r3) { | 1852 void Assembler::xrk(Register r1, Register r2, Register r3) { |
1985 rrf1_form(XRK, r1, r2, r3); | 1853 rrf1_form(XRK, r1, r2, r3); |
1986 } | 1854 } |
1987 | 1855 |
1988 // XOR Register-Storage (64) | 1856 // XOR Register-Storage (64) |
(...skipping 224 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
2213 | 2081 |
2214 void Assembler::jump(Handle<Code> target, RelocInfo::Mode rmode, | 2082 void Assembler::jump(Handle<Code> target, RelocInfo::Mode rmode, |
2215 Condition cond) { | 2083 Condition cond) { |
2216 EnsureSpace ensure_space(this); | 2084 EnsureSpace ensure_space(this); |
2217 | 2085 |
2218 int32_t target_index = emit_code_target(target, rmode); | 2086 int32_t target_index = emit_code_target(target, rmode); |
2219 brcl(cond, Operand(target_index)); | 2087 brcl(cond, Operand(target_index)); |
2220 } | 2088 } |
2221 | 2089 |
2222 // Store (32) | 2090 // Store (32) |
2223 void Assembler::st(Register src, const MemOperand& dst) { | |
2224 rx_form(ST, src, dst.rx(), dst.rb(), dst.offset()); | |
2225 } | |
2226 | |
2227 // Store (32) | |
2228 void Assembler::sty(Register src, const MemOperand& dst) { | 2091 void Assembler::sty(Register src, const MemOperand& dst) { |
2229 rxy_form(STY, src, dst.rx(), dst.rb(), dst.offset()); | 2092 rxy_form(STY, src, dst.rx(), dst.rb(), dst.offset()); |
2230 } | 2093 } |
2231 | 2094 |
2232 // Store Halfword | 2095 // Store Halfword |
2233 void Assembler::sth(Register src, const MemOperand& dst) { | |
2234 rx_form(STH, src, dst.rx(), dst.rb(), dst.offset()); | |
2235 } | |
2236 | |
2237 // Store Halfword | |
2238 void Assembler::sthy(Register src, const MemOperand& dst) { | 2096 void Assembler::sthy(Register src, const MemOperand& dst) { |
2239 rxy_form(STHY, src, dst.rx(), dst.rb(), dst.offset()); | 2097 rxy_form(STHY, src, dst.rx(), dst.rb(), dst.offset()); |
2240 } | 2098 } |
2241 | 2099 |
2242 // Store Character | 2100 // Store Character |
2243 void Assembler::stc(Register src, const MemOperand& dst) { | |
2244 rx_form(STC, src, dst.rx(), dst.rb(), dst.offset()); | |
2245 } | |
2246 | |
2247 // Store Character | |
2248 void Assembler::stcy(Register src, const MemOperand& dst) { | 2101 void Assembler::stcy(Register src, const MemOperand& dst) { |
2249 rxy_form(STCY, src, dst.rx(), dst.rb(), dst.offset()); | 2102 rxy_form(STCY, src, dst.rx(), dst.rb(), dst.offset()); |
2250 } | 2103 } |
2251 | 2104 |
2252 // 32-bit Load Multiple - short displacement (12-bits unsigned) | 2105 // 32-bit Load Multiple - short displacement (12-bits unsigned) |
2253 void Assembler::lm(Register r1, Register r2, const MemOperand& src) { | 2106 void Assembler::lm(Register r1, Register r2, const MemOperand& src) { |
2254 rs_form(LM, r1, r2, src.rb(), src.offset()); | 2107 rs_form(LM, r1, r2, src.rb(), src.offset()); |
2255 } | 2108 } |
2256 | 2109 |
2257 // 32-bit Load Multiple - long displacement (20-bits signed) | 2110 // 32-bit Load Multiple - long displacement (20-bits signed) |
(...skipping 16 matching lines...) Expand all Loading... |
2274 sil_form(MVGHI, opnd1.getBaseRegister(), opnd1.getDisplacement(), i2); | 2127 sil_form(MVGHI, opnd1.getBaseRegister(), opnd1.getDisplacement(), i2); |
2275 } | 2128 } |
2276 | 2129 |
2277 // Store Register (64) | 2130 // Store Register (64) |
2278 void Assembler::stg(Register src, const MemOperand& dst) { | 2131 void Assembler::stg(Register src, const MemOperand& dst) { |
2279 DCHECK(!(dst.rb().code() == 15 && dst.offset() < 0)); | 2132 DCHECK(!(dst.rb().code() == 15 && dst.offset() < 0)); |
2280 rxy_form(STG, src, dst.rx(), dst.rb(), dst.offset()); | 2133 rxy_form(STG, src, dst.rx(), dst.rb(), dst.offset()); |
2281 } | 2134 } |
2282 | 2135 |
2283 // Insert Character | 2136 // Insert Character |
2284 void Assembler::ic_z(Register r1, const MemOperand& opnd) { | |
2285 rx_form(IC_z, r1, opnd.rx(), opnd.rb(), opnd.offset()); | |
2286 } | |
2287 | |
2288 // Insert Character | |
2289 void Assembler::icy(Register r1, const MemOperand& opnd) { | 2137 void Assembler::icy(Register r1, const MemOperand& opnd) { |
2290 rxy_form(ICY, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 2138 rxy_form(ICY, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
2291 } | 2139 } |
2292 | 2140 |
2293 // Insert Immediate (high high) | 2141 // Insert Immediate (high high) |
2294 void Assembler::iihh(Register r1, const Operand& opnd) { | 2142 void Assembler::iihh(Register r1, const Operand& opnd) { |
2295 ri_form(IIHH, r1, opnd); | 2143 ri_form(IIHH, r1, opnd); |
2296 } | 2144 } |
2297 | 2145 |
2298 // Insert Immediate (high low) | 2146 // Insert Immediate (high low) |
(...skipping 14 matching lines...) Expand all Loading... |
2313 // GPR <-> FPR Instructions | 2161 // GPR <-> FPR Instructions |
2314 | 2162 |
2315 // Floating point instructions | 2163 // Floating point instructions |
2316 // | 2164 // |
2317 // Add Register-Storage (LB) | 2165 // Add Register-Storage (LB) |
2318 void Assembler::adb(DoubleRegister r1, const MemOperand& opnd) { | 2166 void Assembler::adb(DoubleRegister r1, const MemOperand& opnd) { |
2319 rxe_form(ADB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(), | 2167 rxe_form(ADB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(), |
2320 opnd.offset()); | 2168 opnd.offset()); |
2321 } | 2169 } |
2322 | 2170 |
2323 // Compare Register-Storage (LB) | |
2324 void Assembler::cdb(DoubleRegister r1, const MemOperand& opnd) { | |
2325 rx_form(CD, Register::from_code(r1.code()), opnd.rx(), opnd.rb(), | |
2326 opnd.offset()); | |
2327 } | |
2328 | |
2329 // Divide Register-Storage (LB) | 2171 // Divide Register-Storage (LB) |
2330 void Assembler::ddb(DoubleRegister r1, const MemOperand& opnd) { | 2172 void Assembler::ddb(DoubleRegister r1, const MemOperand& opnd) { |
2331 rxe_form(DDB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(), | 2173 rxe_form(DDB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(), |
2332 opnd.offset()); | 2174 opnd.offset()); |
2333 } | 2175 } |
2334 | 2176 |
2335 // Multiply Register-Storage (LB) | 2177 // Multiply Register-Storage (LB) |
2336 void Assembler::mdb(DoubleRegister r1, const MemOperand& opnd) { | 2178 void Assembler::mdb(DoubleRegister r1, const MemOperand& opnd) { |
2337 rxe_form(MDB, Register::from_code(r1.code()), opnd.rb(), opnd.rx(), | 2179 rxe_form(MDB, Register::from_code(r1.code()), opnd.rb(), opnd.rx(), |
2338 opnd.offset()); | 2180 opnd.offset()); |
2339 } | 2181 } |
2340 | 2182 |
2341 // Subtract Register-Storage (LB) | 2183 // Subtract Register-Storage (LB) |
2342 void Assembler::sdb(DoubleRegister r1, const MemOperand& opnd) { | 2184 void Assembler::sdb(DoubleRegister r1, const MemOperand& opnd) { |
2343 rxe_form(SDB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(), | 2185 rxe_form(SDB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(), |
2344 opnd.offset()); | 2186 opnd.offset()); |
2345 } | 2187 } |
2346 | 2188 |
2347 // Square Root (LB) | 2189 // Square Root (LB) |
2348 void Assembler::sqdb(DoubleRegister r1, const MemOperand& opnd) { | 2190 void Assembler::sqdb(DoubleRegister r1, const MemOperand& opnd) { |
2349 rxe_form(SQDB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(), | 2191 rxe_form(SQDB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(), |
2350 opnd.offset()); | 2192 opnd.offset()); |
2351 } | 2193 } |
2352 | 2194 |
2353 // Store Double (64) | 2195 // Store Double (64) |
2354 void Assembler::std(DoubleRegister r1, const MemOperand& opnd) { | |
2355 rx_form(STD, r1, opnd.rx(), opnd.rb(), opnd.offset()); | |
2356 } | |
2357 | |
2358 // Store Double (64) | |
2359 void Assembler::stdy(DoubleRegister r1, const MemOperand& opnd) { | 2196 void Assembler::stdy(DoubleRegister r1, const MemOperand& opnd) { |
2360 DCHECK(!(opnd.rb().code() == 15 && opnd.offset() < 0)); | 2197 DCHECK(!(opnd.rb().code() == 15 && opnd.offset() < 0)); |
2361 rxy_form(STDY, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 2198 rxy_form(STDY, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
2362 } | 2199 } |
2363 | 2200 |
2364 // Store Float (32) | 2201 // Store Float (32) |
2365 void Assembler::ste(DoubleRegister r1, const MemOperand& opnd) { | |
2366 rx_form(STE, r1, opnd.rx(), opnd.rb(), opnd.offset()); | |
2367 } | |
2368 | |
2369 // Store Float (32) | |
2370 void Assembler::stey(DoubleRegister r1, const MemOperand& opnd) { | 2202 void Assembler::stey(DoubleRegister r1, const MemOperand& opnd) { |
2371 DCHECK(!(opnd.rb().code() == 15 && opnd.offset() < 0)); | 2203 DCHECK(!(opnd.rb().code() == 15 && opnd.offset() < 0)); |
2372 rxy_form(STEY, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 2204 rxy_form(STEY, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
2373 } | 2205 } |
2374 | 2206 |
2375 // Load Double (64) | 2207 // Load Double (64) |
2376 void Assembler::ld(DoubleRegister r1, const MemOperand& opnd) { | |
2377 DCHECK(is_uint12(opnd.offset())); | |
2378 rx_form(LD, r1, opnd.rx(), opnd.rb(), opnd.offset() & 0xfff); | |
2379 } | |
2380 | |
2381 // Load Double (64) | |
2382 void Assembler::ldy(DoubleRegister r1, const MemOperand& opnd) { | 2208 void Assembler::ldy(DoubleRegister r1, const MemOperand& opnd) { |
2383 DCHECK(is_int20(opnd.offset())); | 2209 DCHECK(is_int20(opnd.offset())); |
2384 rxy_form(LDY, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 2210 rxy_form(LDY, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
2385 } | 2211 } |
2386 | 2212 |
2387 // Load Float (32) | 2213 // Load Float (32) |
2388 void Assembler::le_z(DoubleRegister r1, const MemOperand& opnd) { | |
2389 DCHECK(is_uint12(opnd.offset())); | |
2390 rx_form(LE, r1, opnd.rx(), opnd.rb(), opnd.offset() & 0xfff); | |
2391 } | |
2392 | |
2393 // Load Float (32) | |
2394 void Assembler::ley(DoubleRegister r1, const MemOperand& opnd) { | 2214 void Assembler::ley(DoubleRegister r1, const MemOperand& opnd) { |
2395 DCHECK(is_int20(opnd.offset())); | 2215 DCHECK(is_int20(opnd.offset())); |
2396 rxy_form(LEY, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 2216 rxy_form(LEY, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
2397 } | 2217 } |
2398 | 2218 |
2399 // Convert to Fixed point (64<-S) | 2219 // Convert to Fixed point (64<-S) |
2400 void Assembler::cgebr(Condition m, Register r1, DoubleRegister r2) { | 2220 void Assembler::cgebr(Condition m, Register r1, DoubleRegister r2) { |
2401 rrfe_form(CGEBR, m, Condition(0), r1, Register::from_code(r2.code())); | 2221 rrfe_form(CGEBR, m, Condition(0), r1, Register::from_code(r2.code())); |
2402 } | 2222 } |
2403 | 2223 |
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2640 SKIP_ICACHE_FLUSH); | 2460 SKIP_ICACHE_FLUSH); |
2641 } | 2461 } |
2642 | 2462 |
2643 reloc_info_writer.Write(&rinfo); | 2463 reloc_info_writer.Write(&rinfo); |
2644 } | 2464 } |
2645 } | 2465 } |
2646 | 2466 |
2647 } // namespace internal | 2467 } // namespace internal |
2648 } // namespace v8 | 2468 } // namespace v8 |
2649 #endif // V8_TARGET_ARCH_S390 | 2469 #endif // V8_TARGET_ARCH_S390 |
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