S390: Use macro to declare rx format assember function

src/s390/assembler-s390.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 574 matching lines @@
       break;
     case DEBUG_BREAK_NOP:
       // TODO(john.yan): Use a better NOP break
       oill(r3, Operand::Zero());
       break;
     default:
       UNIMPLEMENTED();
   }
 }
 
-// RX format: <insn> R1,D2(X2,B2)
-//    +--------+----+----+----+-------------+
-//    | OpCode | R1 | X2 | B2 |     D2      |
-//    +--------+----+----+----+-------------+
-//    0        8    12   16   20           31
-#define RX_FORM_EMIT(name, op)                                           \
-  void Assembler::name(Register r, const MemOperand& opnd) {             \
-    name(r, opnd.getIndexRegister(), opnd.getBaseRegister(),             \
-         opnd.getDisplacement());                                        \
-  }                                                                      \
-  void Assembler::name(Register r1, Register x2, Register b2, Disp d2) { \
-    rx_form(op, r1, x2, b2, d2);                                         \
-  }
-void Assembler::rx_form(Opcode op, Register r1, Register x2, Register b2,
-                        Disp d2) {
-  DCHECK(is_uint8(op));
-  DCHECK(is_uint12(d2));
-  emit4bytes(op * B24 | r1.code() * B20 | x2.code() * B16 | b2.code() * B12 |
-             d2);
-}
 
-void Assembler::rx_form(Opcode op, DoubleRegister r1, Register x2, Register b2,
-                        Disp d2) {
-  DCHECK(is_uint8(op));
-  DCHECK(is_uint12(d2));
-  emit4bytes(op * B24 | r1.code() * B20 | x2.code() * B16 | b2.code() * B12 |
-             d2);
-}
 
 // RI1 format: <insn> R1,I2
 //    +--------+----+----+------------------+
 //    | OpCode | R1 |OpCd|        I2        |
 //    +--------+----+----+------------------+
 //    0        8    12   16                31
 #define RI1_FORM_EMIT(name, op) \
   void Assembler::name(Register r, const Operand& i2) { ri_form(op, r, i2); }
 
 void Assembler::ri_form(Opcode op, Register r1, const Operand& i2) {
@@ skipping 688 matching lines @@
 //    0                  16   20   24   28  31
 void Assembler::rrfe_form(Opcode op, Condition m3, Condition m4, Register r1,
                           Register r2) {
   uint32_t code = op << 16 | m3 * B12 | m4 * B8 | r1.code() * B4 | r2.code();
   emit4bytes(code);
 }
 
 // end of S390 Instruction generation
 
 // start of S390 instruction
-RX_FORM_EMIT(bc, BC)
 RXE_FORM_EMIT(ceb, CEB)
 SS1_FORM_EMIT(ed, ED)
-RX_FORM_EMIT(ex, EX)
-RX_FORM_EMIT(le_z, LE)
 RXY_FORM_EMIT(ley, LEY)
 RXY_FORM_EMIT(lrv, LRV)
 RXY_FORM_EMIT(lrvg, LRVG)
 RXY_FORM_EMIT(lrvh, LRVH)
 SS1_FORM_EMIT(mvn, MVN)
 SS1_FORM_EMIT(nc, NC)
 SI_FORM_EMIT(ni, NI)
 RI1_FORM_EMIT(nilh, NILH)
 RI1_FORM_EMIT(nill, NILL)
 RI1_FORM_EMIT(oill, OILL)
 RXY_FORM_EMIT(pfd, PFD)
 RXY_FORM_EMIT(slgf, SLGF)
 RXY_FORM_EMIT(strvh, STRVH)
 RXY_FORM_EMIT(strv, STRV)
 RXY_FORM_EMIT(strvg, STRVG)
 RI1_FORM_EMIT(tmll, TMLL)
 SS1_FORM_EMIT(tr, TR)
 S_FORM_EMIT(ts, TS)
 
 // -------------------------
 // Load Address Instructions
 // -------------------------
 // Load Address Register-Storage
-void Assembler::la(Register r1, const MemOperand& opnd) {
-  rx_form(LA, r1, opnd.rx(), opnd.rb(), opnd.offset());
-}
-
-// Load Address Register-Storage
 void Assembler::lay(Register r1, const MemOperand& opnd) {
   rxy_form(LAY, r1, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // Load Address Relative Long
 void Assembler::larl(Register r1, Label* l) {
   larl(r1, Operand(branch_offset(l)));
 }
 
 // -----------------
 // Load Instructions
 // -----------------
 // Load Byte Register-Storage (32<-8)
 void Assembler::lb(Register r, const MemOperand& src) {
   rxy_form(LB, r, src.rx(), src.rb(), src.offset());
 }
 
 // Load Byte Register-Storage (64<-8)
 void Assembler::lgb(Register r, const MemOperand& src) {
   rxy_form(LGB, r, src.rx(), src.rb(), src.offset());
 }
 
 // Load Halfword Register-Storage (32<-16)
-void Assembler::lh(Register r, const MemOperand& src) {
-  rx_form(LH, r, src.rx(), src.rb(), src.offset());
-}
-
-// Load Halfword Register-Storage (32<-16)
 void Assembler::lhy(Register r, const MemOperand& src) {
   rxy_form(LHY, r, src.rx(), src.rb(), src.offset());
 }
 
 // Load Halfword Register-Storage (64<-16)
 void Assembler::lgh(Register r, const MemOperand& src) {
   rxy_form(LGH, r, src.rx(), src.rb(), src.offset());
 }
 
 // Load Register-Storage (32)
-void Assembler::l(Register r, const MemOperand& src) {
-  rx_form(L, r, src.rx(), src.rb(), src.offset());
-}
-
-// Load Register-Storage (32)
 void Assembler::ly(Register r, const MemOperand& src) {
   rxy_form(LY, r, src.rx(), src.rb(), src.offset());
 }
 
 // Load Register-Storage (64)
 void Assembler::lg(Register r, const MemOperand& src) {
   rxy_form(LG, r, src.rx(), src.rb(), src.offset());
 }
 
 // Load Register-Storage (64<-32)
@@ skipping 64 matching lines @@
 }
 
 // Load On Condition R-M (64)
 void Assembler::locg(Condition m3, Register r1, const MemOperand& src) {
   rxy_form(LOCG, r1, m3, src.rb(), src.offset());
 }
 
 // -------------------
 // Branch Instructions
 // -------------------
-
-// Branch on Count (32)
-void Assembler::bct(Register r, const MemOperand& opnd) {
-  rx_form(BCT, r, opnd.rx(), opnd.rb(), opnd.offset());
-}
-
 // Branch on Count (64)
 void Assembler::bctg(Register r, const MemOperand& opnd) {
   rxy_form(BCTG, r, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // Branch Relative and Save (32)
 void Assembler::bras(Register r, const Operand& opnd) {
   ri_form(BRAS, r, opnd);
 }
 
@@ skipping 15 matching lines @@
   int16_t numHalfwords = static_cast<int16_t>(imm.immediate()) / 2;
   Operand halfwordOp = Operand(numHalfwords);
   halfwordOp.setBits(16);
   ri_form(BRCTG, r1, halfwordOp);
 }
 
 // --------------------
 // Compare Instructions
 // --------------------
 // Compare Register-Storage (32)
-void Assembler::c(Register r, const MemOperand& opnd) {
-  rx_form(C, r, opnd.rx(), opnd.rb(), opnd.offset());
-}
-
-// Compare Register-Storage (32)
 void Assembler::cy(Register r, const MemOperand& opnd) {
   rxy_form(CY, r, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // Compare Register-Storage (64)
 void Assembler::cg(Register r, const MemOperand& opnd) {
   rxy_form(CG, r, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // Compare Halfword Register-Storage (32)
-void Assembler::ch(Register r, const MemOperand& opnd) {
-  rx_form(CH, r, opnd.rx(), opnd.rb(), opnd.offset());
-}
-
-// Compare Halfword Register-Storage (32)
 void Assembler::chy(Register r, const MemOperand& opnd) {
   rxy_form(CHY, r, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // Compare Halfword Immediate (32)
 void Assembler::chi(Register r, const Operand& opnd) { ri_form(CHI, r, opnd); }
 
 // Compare Halfword Immediate (64)
 void Assembler::cghi(Register r, const Operand& opnd) {
   ri_form(CGHI, r, opnd);
 }
 
 // ----------------------------
 // Compare Logical Instructions
 // ----------------------------
 // Compare Logical Register-Storage (32)
-void Assembler::cl(Register r, const MemOperand& opnd) {
-  rx_form(CL, r, opnd.rx(), opnd.rb(), opnd.offset());
-}
-
-// Compare Logical Register-Storage (32)
 void Assembler::cly(Register r, const MemOperand& opnd) {
   rxy_form(CLY, r, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // Compare Logical Register-Storage (64)
 void Assembler::clg(Register r, const MemOperand& opnd) {
   rxy_form(CLG, r, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // Compare Immediate (Mem - Imm) (8)
@@ skipping 60 matching lines @@
 void Assembler::mvc(const MemOperand& opnd1, const MemOperand& opnd2,
                     uint32_t length) {
   ss_form(MVC, length - 1, opnd1.getBaseRegister(), opnd1.getDisplacement(),
           opnd2.getBaseRegister(), opnd2.getDisplacement());
 }
 
 // -----------------------
 // 32-bit Add Instructions
 // -----------------------
 // Add Register-Storage (32)
-void Assembler::a(Register r1, const MemOperand& opnd) {
-  rx_form(A, r1, opnd.rx(), opnd.rb(), opnd.offset());
-}
-
-// Add Register-Storage (32)
 void Assembler::ay(Register r1, const MemOperand& opnd) {
   rxy_form(AY, r1, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // Add Halfword Register-Storage (32)
-void Assembler::ah(Register r1, const MemOperand& opnd) {
-  rx_form(AH, r1, opnd.rx(), opnd.rb(), opnd.offset());
-}
-
-// Add Halfword Register-Storage (32)
 void Assembler::ahy(Register r1, const MemOperand& opnd) {
   rxy_form(AHY, r1, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // Add Halfword Immediate (32)
 void Assembler::ahi(Register r1, const Operand& i2) { ri_form(AHI, r1, i2); }
 
 // Add Halfword Immediate (32)
 void Assembler::ahik(Register r1, Register r3, const Operand& i2) {
   rie_form(AHIK, r1, r3, i2);
@@ skipping 41 matching lines @@
 void Assembler::agsi(const MemOperand& opnd, const Operand& imm) {
   DCHECK(is_int8(imm.imm_));
   DCHECK(is_int20(opnd.offset()));
   siy_form(AGSI, Operand(0xff & imm.imm_), opnd.rb(), 0xfffff & opnd.offset());
 }
 
 // -------------------------------
 // 32-bit Add Logical Instructions
 // -------------------------------
 // Add Logical Register-Storage (32)
-void Assembler::al_z(Register r1, const MemOperand& opnd) {
-  rx_form(AL, r1, opnd.rx(), opnd.rb(), opnd.offset());
-}
-
-// Add Logical Register-Storage (32)
 void Assembler::aly(Register r1, const MemOperand& opnd) {
   rxy_form(ALY, r1, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // Add Logical Register-Register-Register (32)
 void Assembler::alrk(Register r1, Register r2, Register r3) {
   rrf1_form(ALRK, r1, r2, r3);
 }
 
 // -------------------------------
 // 64-bit Add Logical Instructions
 // -------------------------------
 // Add Logical Register-Storage (64)
 void Assembler::alg(Register r1, const MemOperand& opnd) {
   rxy_form(ALG, r1, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // Add Logical Register-Register-Register (64)
 void Assembler::algrk(Register r1, Register r2, Register r3) {
   rrf1_form(ALGRK, r1, r2, r3);
 }
 
 // ----------------------------
 // 32-bit Subtract Instructions
 // ----------------------------
 // Subtract Register-Storage (32)
-void Assembler::s(Register r1, const MemOperand& opnd) {
-  rx_form(S, r1, opnd.rx(), opnd.rb(), opnd.offset());
-}
-
-// Subtract Register-Storage (32)
 void Assembler::sy(Register r1, const MemOperand& opnd) {
   rxy_form(SY, r1, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // Subtract Halfword Register-Storage (32)
-void Assembler::sh(Register r1, const MemOperand& opnd) {
-  rx_form(SH, r1, opnd.rx(), opnd.rb(), opnd.offset());
-}
-
-// Subtract Halfword Register-Storage (32)
 void Assembler::shy(Register r1, const MemOperand& opnd) {
   rxy_form(SHY, r1, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // Subtract Register-Register-Register (32)
 void Assembler::srk(Register r1, Register r2, Register r3) {
   rrf1_form(SRK, r1, r2, r3);
 }
 
 // ----------------------------
@@ skipping 11 matching lines @@
 
 // Subtract Register-Register-Register (64)
 void Assembler::sgrk(Register r1, Register r2, Register r3) {
   rrf1_form(SGRK, r1, r2, r3);
 }
 
 // ------------------------------------
 // 32-bit Subtract Logical Instructions
 // ------------------------------------
 // Subtract Logical Register-Storage (32)
-void Assembler::sl(Register r1, const MemOperand& opnd) {
-  rx_form(SL, r1, opnd.rx(), opnd.rb(), opnd.offset());
-}
-
-// Subtract Logical Register-Storage (32)
 void Assembler::sly(Register r1, const MemOperand& opnd) {
   rxy_form(SLY, r1, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // Subtract Logical Register-Register-Register (32)
 void Assembler::slrk(Register r1, Register r2, Register r3) {
   rrf1_form(SLRK, r1, r2, r3);
 }
 
 // ------------------------------------
 // 64-bit Subtract Logical Instructions
 // ------------------------------------
 // Subtract Logical Register-Storage (64)
 void Assembler::slg(Register r1, const MemOperand& opnd) {
   rxy_form(SLG, r1, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // Subtract Logical Register-Register-Register (64)
 void Assembler::slgrk(Register r1, Register r2, Register r3) {
   rrf1_form(SLGRK, r1, r2, r3);
 }
 
 // ----------------------------
 // 32-bit Multiply Instructions
 // ----------------------------
-// Multiply Register-Storage (64<32)
-void Assembler::m(Register r1, const MemOperand& opnd) {
-  DCHECK(r1.code() % 2 == 0);
-  rx_form(M, r1, opnd.rx(), opnd.rb(), opnd.offset());
-}
-
 void Assembler::mfy(Register r1, const MemOperand& opnd) {
   DCHECK(r1.code() % 2 == 0);
   rxy_form(MFY, r1, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // Multiply Logical Register-Storage (64<32)
 void Assembler::ml(Register r1, const MemOperand& opnd) {
   rxy_form(ML, r1, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // Multiply Single Register-Storage (32)
-void Assembler::ms(Register r1, const MemOperand& opnd) {
-  rx_form(MS, r1, opnd.rx(), opnd.rb(), opnd.offset());
-}
-
-// Multiply Single Register-Storage (32)
 void Assembler::msy(Register r1, const MemOperand& opnd) {
   rxy_form(MSY, r1, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // Multiply Halfword Register-Storage (32)
-void Assembler::mh(Register r1, const MemOperand& opnd) {
-  rx_form(MH, r1, opnd.rx(), opnd.rb(), opnd.offset());
-}
-
-// Multiply Halfword Register-Storage (32)
 void Assembler::mhy(Register r1, const MemOperand& opnd) {
   rxy_form(MHY, r1, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // Multiply Halfword Immediate (32)
 void Assembler::mhi(Register r1, const Operand& opnd) {
   ri_form(MHI, r1, opnd);
 }
 
 // ----------------------------
@@ skipping 14 matching lines @@
   rxy_form(MSG, r1, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 void Assembler::msgf(Register r1, const MemOperand& opnd) {
   rxy_form(MSGF, r1, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // --------------------------
 // 32-bit Divide Instructions
 // --------------------------
-// Divide Register-Storage (32<-64)
-void Assembler::d(Register r1, const MemOperand& opnd) {
-  rx_form(D, r1, opnd.rx(), opnd.rb(), opnd.offset());
-}
-
 // Divide Logical Register-Storage (32<-64)
 void Assembler::dl(Register r1, const MemOperand& opnd) {
   rxy_form(DL, r1, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 void Assembler::dsg(Register r1, const MemOperand& opnd) {
   rxy_form(DSG, r1, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 void Assembler::dsgf(Register r1, const MemOperand& opnd) {
   rxy_form(DSGF, r1, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // --------------------
 // Bitwise Instructions
 // --------------------
 // AND Register-Storage (32)
-void Assembler::n(Register r1, const MemOperand& opnd) {
-  rx_form(N, r1, opnd.rx(), opnd.rb(), opnd.offset());
-}
-
-// AND Register-Storage (32)
 void Assembler::ny(Register r1, const MemOperand& opnd) {
   rxy_form(NY, r1, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // AND Register-Register-Register (32)
 void Assembler::nrk(Register r1, Register r2, Register r3) {
   rrf1_form(NRK, r1, r2, r3);
 }
 
 // AND Register-Storage (64)
 void Assembler::ng(Register r1, const MemOperand& opnd) {
   rxy_form(NG, r1, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // AND Register-Register-Register (64)
 void Assembler::ngrk(Register r1, Register r2, Register r3) {
   rrf1_form(NGRK, r1, r2, r3);
 }
 
 // OR Register-Storage (32)
-void Assembler::o(Register r1, const MemOperand& opnd) {
-  rx_form(O, r1, opnd.rx(), opnd.rb(), opnd.offset());
-}
-
-// OR Register-Storage (32)
 void Assembler::oy(Register r1, const MemOperand& opnd) {
   rxy_form(OY, r1, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // OR Register-Register-Register (32)
 void Assembler::ork(Register r1, Register r2, Register r3) {
   rrf1_form(ORK, r1, r2, r3);
 }
 
 // OR Register-Storage (64)
 void Assembler::og(Register r1, const MemOperand& opnd) {
   rxy_form(OG, r1, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // OR Register-Register-Register (64)
 void Assembler::ogrk(Register r1, Register r2, Register r3) {
   rrf1_form(OGRK, r1, r2, r3);
 }
 
 // XOR Register-Storage (32)
-void Assembler::x(Register r1, const MemOperand& opnd) {
-  rx_form(X, r1, opnd.rx(), opnd.rb(), opnd.offset());
-}
-
-// XOR Register-Storage (32)
 void Assembler::xy(Register r1, const MemOperand& opnd) {
   rxy_form(XY, r1, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // XOR Register-Register-Register (32)
 void Assembler::xrk(Register r1, Register r2, Register r3) {
   rrf1_form(XRK, r1, r2, r3);
 }
 
 // XOR Register-Storage (64)
@@ skipping 224 matching lines @@
 
 void Assembler::jump(Handle<Code> target, RelocInfo::Mode rmode,
                      Condition cond) {
   EnsureSpace ensure_space(this);
 
   int32_t target_index = emit_code_target(target, rmode);
   brcl(cond, Operand(target_index));
 }
 
 // Store (32)
-void Assembler::st(Register src, const MemOperand& dst) {
-  rx_form(ST, src, dst.rx(), dst.rb(), dst.offset());
-}
-
-// Store (32)
 void Assembler::sty(Register src, const MemOperand& dst) {
   rxy_form(STY, src, dst.rx(), dst.rb(), dst.offset());
 }
 
 // Store Halfword
-void Assembler::sth(Register src, const MemOperand& dst) {
-  rx_form(STH, src, dst.rx(), dst.rb(), dst.offset());
-}
-
-// Store Halfword
 void Assembler::sthy(Register src, const MemOperand& dst) {
   rxy_form(STHY, src, dst.rx(), dst.rb(), dst.offset());
 }
 
 // Store Character
-void Assembler::stc(Register src, const MemOperand& dst) {
-  rx_form(STC, src, dst.rx(), dst.rb(), dst.offset());
-}
-
-// Store Character
 void Assembler::stcy(Register src, const MemOperand& dst) {
   rxy_form(STCY, src, dst.rx(), dst.rb(), dst.offset());
 }
 
 // 32-bit Load Multiple - short displacement (12-bits unsigned)
 void Assembler::lm(Register r1, Register r2, const MemOperand& src) {
   rs_form(LM, r1, r2, src.rb(), src.offset());
 }
 
 // 32-bit Load Multiple - long displacement (20-bits signed)
@@ skipping 16 matching lines @@
   sil_form(MVGHI, opnd1.getBaseRegister(), opnd1.getDisplacement(), i2);
 }
 
 // Store Register (64)
 void Assembler::stg(Register src, const MemOperand& dst) {
   DCHECK(!(dst.rb().code() == 15 && dst.offset() < 0));
   rxy_form(STG, src, dst.rx(), dst.rb(), dst.offset());
 }
 
 // Insert Character
-void Assembler::ic_z(Register r1, const MemOperand& opnd) {
-  rx_form(IC_z, r1, opnd.rx(), opnd.rb(), opnd.offset());
-}
-
-// Insert Character
 void Assembler::icy(Register r1, const MemOperand& opnd) {
   rxy_form(ICY, r1, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // Insert Immediate (high high)
 void Assembler::iihh(Register r1, const Operand& opnd) {
   ri_form(IIHH, r1, opnd);
 }
 
 // Insert Immediate (high low)
@@ skipping 14 matching lines @@
 // GPR <-> FPR Instructions
 
 // Floating point instructions
 //
 // Add Register-Storage (LB)
 void Assembler::adb(DoubleRegister r1, const MemOperand& opnd) {
   rxe_form(ADB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(),
            opnd.offset());
 }
 
-// Compare Register-Storage (LB)
-void Assembler::cdb(DoubleRegister r1, const MemOperand& opnd) {
-  rx_form(CD, Register::from_code(r1.code()), opnd.rx(), opnd.rb(),
-          opnd.offset());
-}
-
 // Divide Register-Storage (LB)
 void Assembler::ddb(DoubleRegister r1, const MemOperand& opnd) {
   rxe_form(DDB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(),
            opnd.offset());
 }
 
 // Multiply Register-Storage (LB)
 void Assembler::mdb(DoubleRegister r1, const MemOperand& opnd) {
   rxe_form(MDB, Register::from_code(r1.code()), opnd.rb(), opnd.rx(),
            opnd.offset());
 }
 
 // Subtract Register-Storage (LB)
 void Assembler::sdb(DoubleRegister r1, const MemOperand& opnd) {
   rxe_form(SDB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(),
            opnd.offset());
 }
 
 // Square Root (LB)
 void Assembler::sqdb(DoubleRegister r1, const MemOperand& opnd) {
   rxe_form(SQDB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(),
            opnd.offset());
 }
 
 // Store Double (64)
-void Assembler::std(DoubleRegister r1, const MemOperand& opnd) {
-  rx_form(STD, r1, opnd.rx(), opnd.rb(), opnd.offset());
-}
-
-// Store Double (64)
 void Assembler::stdy(DoubleRegister r1, const MemOperand& opnd) {
   DCHECK(!(opnd.rb().code() == 15 && opnd.offset() < 0));
   rxy_form(STDY, r1, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // Store Float (32)
-void Assembler::ste(DoubleRegister r1, const MemOperand& opnd) {
-  rx_form(STE, r1, opnd.rx(), opnd.rb(), opnd.offset());
-}
-
-// Store Float (32)
 void Assembler::stey(DoubleRegister r1, const MemOperand& opnd) {
   DCHECK(!(opnd.rb().code() == 15 && opnd.offset() < 0));
   rxy_form(STEY, r1, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // Load Double (64)
-void Assembler::ld(DoubleRegister r1, const MemOperand& opnd) {
-  DCHECK(is_uint12(opnd.offset()));
-  rx_form(LD, r1, opnd.rx(), opnd.rb(), opnd.offset() & 0xfff);
-}
-
-// Load Double (64)
 void Assembler::ldy(DoubleRegister r1, const MemOperand& opnd) {
   DCHECK(is_int20(opnd.offset()));
   rxy_form(LDY, r1, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // Load Float (32)
-void Assembler::le_z(DoubleRegister r1, const MemOperand& opnd) {
-  DCHECK(is_uint12(opnd.offset()));
-  rx_form(LE, r1, opnd.rx(), opnd.rb(), opnd.offset() & 0xfff);
-}
-
-// Load Float (32)
 void Assembler::ley(DoubleRegister r1, const MemOperand& opnd) {
   DCHECK(is_int20(opnd.offset()));
   rxy_form(LEY, r1, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // Convert to Fixed point (64<-S)
 void Assembler::cgebr(Condition m, Register r1, DoubleRegister r2) {
   rrfe_form(CGEBR, m, Condition(0), r1, Register::from_code(r2.code()));
 }
 
@@ skipping 236 matching lines @@
                             SKIP_ICACHE_FLUSH);
     }
 
     reloc_info_writer.Write(&rinfo);
   }
 }
 
 }  // namespace internal
 }  // namespace v8
 #endif  // V8_TARGET_ARCH_S390