Revert "Optimizations to IC stub for unoptimized code performance on x64."

runtime/vm/stub_code_mips.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_MIPS)
 
 #include "vm/assembler.h"
 #include "vm/code_generator.h"
 #include "vm/compiler.h"
@@ skipping 1385 matching lines @@
   const int32_t imm_smi_cid = reinterpret_cast<int32_t>(Smi::New(kSmiCid));
   __ lw(T4, Address(T0));
   __ BranchNotEqual(T4, Immediate(imm_smi_cid), &error);
   __ lw(T4, Address(T0, kWordSize));
   __ BranchEqual(T4, Immediate(imm_smi_cid), &ok);
   __ Bind(&error);
   __ Stop("Incorrect IC data");
   __ Bind(&ok);
 #endif
   if (FLAG_optimization_counter_threshold >= 0) {
-    // Update counter, ignore overflow.
+    // Update counter.
     const intptr_t count_offset = ICData::CountIndexFor(num_args) * kWordSize;
     __ lw(T4, Address(T0, count_offset));
-    __ AddImmediate(T4, T4, Smi::RawValue(1));
+    __ AddImmediateDetectOverflow(T7, T4, Smi::RawValue(1), T5, T6);
+    __ slt(CMPRES1, T5, ZR);  // T5 is < 0 if there was overflow.
+    __ LoadImmediate(T4, Smi::RawValue(Smi::kMaxValue));
+    __ movz(T4, T7, CMPRES1);
     __ sw(T4, Address(T0, count_offset));
   }
 
   __ Ret();
 }
 
 
 // Generate inline cache check for 'num_args'.
 //  RA: return address
 //  S5: Inline cache data object.
 // Control flow:
 // - If receiver is null -> jump to IC miss.
 // - If receiver is Smi -> load Smi class.
 // - If receiver is not-Smi -> load receiver's class.
 // - Check if 'num_args' (including receiver) match any IC data group.
 // - Match found -> jump to target.
 // - Match not found -> jump to IC miss.
 void StubCode::GenerateNArgsCheckInlineCacheStub(
     Assembler* assembler,
     intptr_t num_args,
     const RuntimeEntry& handle_ic_miss,
     Token::Kind kind,
     bool optimized) {
   __ Comment("NArgsCheckInlineCacheStub");
-  ASSERT(num_args == 1 || num_args == 2);
+  ASSERT(num_args > 0);
 #if defined(DEBUG)
   {
     Label ok;
     // Check that the IC data array has NumArgsTested() == num_args.
     // 'NumArgsTested' is stored in the least significant bits of 'state_bits'.
     __ lw(T0, FieldAddress(S5, ICData::state_bits_offset()));
     ASSERT(ICData::NumArgsTestedShift() == 0);  // No shift needed.
     __ andi(T0, T0, Immediate(ICData::NumArgsTestedMask()));
     __ BranchEqual(T0, Immediate(num_args), &ok);
     __ Stop("Incorrect stub for IC data");
@@ skipping 16 matching lines @@
     EmitFastSmiOp(assembler, kind, num_args, &not_smi_or_overflow);
   }
   __ Bind(&not_smi_or_overflow);
 
   __ Comment("Extract ICData initial values and receiver cid");
   // Load argument descriptor into S4.
   __ lw(S4, FieldAddress(S5, ICData::arguments_descriptor_offset()));
   // Preserve return address, since RA is needed for subroutine call.
   __ mov(T2, RA);
   // Loop that checks if there is an IC data match.
-  Label loop, found, miss;
+  Label loop, update, test, found;
   // S5: IC data object (preserved).
   __ lw(T0, FieldAddress(S5, ICData::ic_data_offset()));
   // T0: ic_data_array with check entries: classes and target functions.
   __ AddImmediate(T0, Array::data_offset() - kHeapObjectTag);
   // T0: points directly to the first ic data array element.
 
   // Get the receiver's class ID (first read number of arguments from
   // arguments descriptor array and then access the receiver from the stack).
   __ lw(T1, FieldAddress(S4, ArgumentsDescriptor::count_offset()));
   __ LoadImmediate(TMP, Smi::RawValue(1));
   __ subu(T1, T1, TMP);
   __ sll(T3, T1, 1);  // T1 (argument_count - 1) is smi.
   __ addu(T3, T3, SP);
   __ lw(T3, Address(T3));
   __ LoadTaggedClassIdMayBeSmi(T3, T3);
 
-  if (num_args == 2) {
-    __ LoadImmediate(TMP, Smi::RawValue(1));
-    __ subu(T5, T1, TMP);
-    __ sll(T5, T5, 1);
-    __ addu(T5, SP, T5);
-    __ lw(T5, Address(T5));
-    __ LoadTaggedClassIdMayBeSmi(T5, T5);
-  }
-
   // T1: argument_count - 1 (smi).
   // T3: receiver's class ID (smi).
-  // T5: first argument's class ID (smi).
-
-  // We unroll the generic one that is generated once more than the others.
-  bool optimize = kind == Token::kILLEGAL;
+  __ b(&test);
+  __ delay_slot()->lw(T4, Address(T0));  // First class id (smi) to check.
 
   __ Comment("ICData loop");
   __ Bind(&loop);
-  for (int unroll = optimize ? 4 : 2; unroll >= 0; unroll--) {
-    Label update;
-    for (int i = 0; i < num_args; i++) {
+  for (int i = 0; i < num_args; i++) {
+    if (i > 0) {
+      // If not the first, load the next argument's class ID.
+      __ LoadImmediate(T3, Smi::RawValue(-i));
+      __ addu(T3, T1, T3);
+      __ sll(T3, T3, 1);
+      __ addu(T3, SP, T3);
+      __ lw(T3, Address(T3));
+      __ LoadTaggedClassIdMayBeSmi(T3, T3);
+      // T3: next argument class ID (smi).
       __ lw(T4, Address(T0, i * kWordSize));
-      if (i == 0) {
-        if (num_args == 1) {
-          __ beq(T3, T4, &found);  // IC hit.
-        } else {
-          __ bne(T3, T4, &update);  // Continue.
-        }
-      } else {
-        __ beq(T5, T4, &found);  // IC hit.
-      }
+      // T4: next class ID to check (smi).
     }
-    __ Bind(&update);
-
-    const intptr_t entry_size =
-        ICData::TestEntryLengthFor(num_args) * kWordSize;
-    __ AddImmediate(T0, entry_size);  // Next entry.
-    if (unroll == 0) {
-      __ BranchNotEqual(T4, Immediate(Smi::RawValue(kIllegalCid)),
-                        &loop);  // Done?
+    if (i < (num_args - 1)) {
+      __ bne(T3, T4, &update);  // Continue.
     } else {
-      __ BranchEqual(T4, Immediate(Smi::RawValue(kIllegalCid)),
-                     &miss);  // Done?
+      // Last check, all checks before matched.
+      Label skip;
+      __ bne(T3, T4, &skip);
+      __ b(&found);                  // Break.
+      __ delay_slot()->mov(RA, T2);  // Restore return address if found.
+      __ Bind(&skip);
     }
-    __ delay_slot()->lw(T4, Address(T0));  // Next class ID.
+  }
+  __ Bind(&update);
+  // Reload receiver class ID.  It has not been destroyed when num_args == 1.
+  if (num_args > 1) {
+    __ sll(T3, T1, 1);
+    __ addu(T3, T3, SP);
+    __ lw(T3, Address(T3));
+    __ LoadTaggedClassIdMayBeSmi(T3, T3);
   }
 
-  __ Bind(&miss);
+  const intptr_t entry_size = ICData::TestEntryLengthFor(num_args) * kWordSize;
+  __ AddImmediate(T0, entry_size);  // Next entry.
+  __ lw(T4, Address(T0));           // Next class ID.
+
+  __ Bind(&test);
+  __ BranchNotEqual(T4, Immediate(Smi::RawValue(kIllegalCid)), &loop);  // Done?
+
   __ Comment("IC miss");
   // Restore return address.
   __ mov(RA, T2);
 
   // Compute address of arguments (first read number of arguments from
   // arguments descriptor array and then compute address on the stack).
   // T1: argument_count - 1 (smi).
   __ sll(T1, T1, 1);  // T1 is Smi.
   __ addu(T1, SP, T1);
   // T1: address of receiver.
@@ skipping 29 matching lines @@
 
   Label call_target_function;
   if (!FLAG_lazy_dispatchers) {
     __ mov(T0, T3);
     GenerateDispatcherCode(assembler, &call_target_function);
   } else {
     __ b(&call_target_function);
   }
 
   __ Bind(&found);
-  __ mov(RA, T2);  // Restore return address if found.
   __ Comment("Update caller's counter");
   // T0: Pointer to an IC data check group.
   const intptr_t target_offset = ICData::TargetIndexFor(num_args) * kWordSize;
   const intptr_t count_offset = ICData::CountIndexFor(num_args) * kWordSize;
   __ lw(T3, Address(T0, target_offset));
 
   if (FLAG_optimization_counter_threshold >= 0) {
-    // Update counter, ignore overflow.
+    // Update counter.
     __ lw(T4, Address(T0, count_offset));
-    __ AddImmediate(T4, T4, Smi::RawValue(1));
+    __ AddImmediateDetectOverflow(T7, T4, Smi::RawValue(1), T5, T6);
+    __ slt(CMPRES1, T5, ZR);  // T5 is < 0 if there was overflow.
+    __ LoadImmediate(T4, Smi::RawValue(Smi::kMaxValue));
+    __ movz(T4, T7, CMPRES1);
     __ sw(T4, Address(T0, count_offset));
   }
 
   __ Comment("Call target");
   __ Bind(&call_target_function);
   // T0 <- T3: Target function.
   __ mov(T0, T3);
   Label is_compiled;
   __ lw(T4, FieldAddress(T0, Function::entry_point_offset()));
   __ lw(CODE_REG, FieldAddress(T0, Function::code_offset()));
@@ skipping 112 matching lines @@
 
   // S5: IC data object (preserved).
   __ lw(T0, FieldAddress(S5, ICData::ic_data_offset()));
   // T0: ic_data_array with entries: target functions and count.
   __ AddImmediate(T0, Array::data_offset() - kHeapObjectTag);
   // T0: points directly to the first ic data array element.
   const intptr_t target_offset = ICData::TargetIndexFor(0) * kWordSize;
   const intptr_t count_offset = ICData::CountIndexFor(0) * kWordSize;
 
   if (FLAG_optimization_counter_threshold >= 0) {
-    // Increment count for this call, ignore overflow.
+    // Increment count for this call.
     __ lw(T4, Address(T0, count_offset));
-    __ AddImmediate(T4, T4, Smi::RawValue(1));
+    __ AddImmediateDetectOverflow(T7, T4, Smi::RawValue(1), T5, T6);
+    __ slt(CMPRES1, T5, ZR);  // T5 is < 0 if there was overflow.
+    __ LoadImmediate(T4, Smi::RawValue(Smi::kMaxValue));
+    __ movz(T4, T7, CMPRES1);
     __ sw(T4, Address(T0, count_offset));
   }
 
   // Load arguments descriptor into S4.
   __ lw(S4, FieldAddress(S5, ICData::arguments_descriptor_offset()));
 
   // Get function and call it, if possible.
   __ lw(T0, Address(T0, target_offset));
   __ lw(CODE_REG, FieldAddress(T0, Function::code_offset()));
   __ lw(T4, FieldAddress(T0, Function::entry_point_offset()));
@@ skipping 673 matching lines @@
 }
 
 
 void StubCode::GenerateFrameAwaitingMaterializationStub(Assembler* assembler) {
   __ break_(0);
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_MIPS