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Unified Diff: tests_lit/llvm2ice_tests/64bit.pnacl.ll

Issue 265703002: Add Om1 lowering with no optimizations (Closed) Base URL: https://gerrit.chromium.org/gerrit/p/native_client/pnacl-subzero.git@master
Patch Set: Address Jan's third-round comments Created 6 years, 7 months ago
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Index: tests_lit/llvm2ice_tests/64bit.pnacl.ll
diff --git a/tests_lit/llvm2ice_tests/64bit.pnacl.ll b/tests_lit/llvm2ice_tests/64bit.pnacl.ll
index 4b79fd1479b3eeca33d4fe77dfe4ad02f3553e1d..8cfbab8d3e696b4a2a5d586238f214fc19619ffe 100644
--- a/tests_lit/llvm2ice_tests/64bit.pnacl.ll
+++ b/tests_lit/llvm2ice_tests/64bit.pnacl.ll
@@ -1,5 +1,10 @@
-; RUIN: %llvm2ice --verbose none %s | FileCheck %s
-; RUIN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
+; This tries to be a comprehensive test of i64 operations, in
+; particular the patterns for lowering i64 operations into constituent
+; i32 operations on x86-32.
+
+; RUIN: %llvm2ice -O2 --verbose none %s | FileCheck %s
+; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck --check-prefix=OPTM1 %s
+; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
; RUN: %szdiff --llvm2ice=%llvm2ice %s | FileCheck --check-prefix=DUMP %s
@__init_array_start = internal constant [0 x i8] zeroinitializer, align 4
@@ -38,6 +43,24 @@ entry:
; CHECK-NEXT: push
; CHECK-NEXT: push
; CHECK-NEXT: call ignore64BitArgNoInline
+;
+; OPTM1: pass64BitArg:
+; OPTM1: push 123
+; OPTM1-NEXT: push
+; OPTM1-NEXT: push
+; OPTM1-NEXT: call ignore64BitArgNoInline
+; OPTM1: push
+; OPTM1-NEXT: push
+; OPTM1-NEXT: push 123
+; OPTM1-NEXT: push
+; OPTM1-NEXT: push
+; OPTM1-NEXT: call ignore64BitArgNoInline
+; OPTM1: push
+; OPTM1-NEXT: push
+; OPTM1-NEXT: push 123
+; OPTM1-NEXT: push
+; OPTM1-NEXT: push
+; OPTM1-NEXT: call ignore64BitArgNoInline
declare i32 @ignore64BitArgNoInline(i64, i32, i64)
@@ -53,6 +76,14 @@ entry:
; CHECK-NEXT: push ecx
; CHECK-NEXT: push eax
; CHECK-NEXT: call ignore64BitArgNoInline
+;
+; OPTM1: pass64BitConstArg:
+; OPTM1: push 3735928559
+; OPTM1-NEXT: push 305419896
+; OPTM1-NEXT: push 123
+; OPTM1-NEXT: push dword ptr [
+; OPTM1-NEXT: push dword ptr [
+; OPTM1-NEXT: call ignore64BitArgNoInline
define internal i64 @return64BitArg(i64 %a) {
entry:
@@ -62,6 +93,11 @@ entry:
; CHECK: mov {{.*}}, dword ptr [esp+4]
; CHECK: mov {{.*}}, dword ptr [esp+8]
; CHECK: ret
+;
+; OPTM1: return64BitArg:
+; OPTM1: mov {{.*}}, dword ptr [esp+4]
+; OPTM1: mov {{.*}}, dword ptr [esp+8]
+; OPTM1: ret
define internal i64 @return64BitConst() {
entry:
@@ -71,6 +107,11 @@ entry:
; CHECK: mov eax, 305419896
; CHECK: mov edx, 3735928559
; CHECK: ret
+;
+; OPTM1: return64BitConst:
+; OPTM1: mov eax, 305419896
+; OPTM1: mov edx, 3735928559
+; OPTM1: ret
define internal i64 @add64BitSigned(i64 %a, i64 %b) {
entry:
@@ -81,6 +122,11 @@ entry:
; CHECK: add
; CHECK: adc
; CHECK: ret
+;
+; OPTM1: add64BitSigned:
+; OPTM1: add
+; OPTM1: adc
+; OPTM1: ret
define internal i64 @add64BitUnsigned(i64 %a, i64 %b) {
entry:
@@ -91,6 +137,11 @@ entry:
; CHECK: add
; CHECK: adc
; CHECK: ret
+;
+; OPTM1: add64BitUnsigned:
+; OPTM1: add
+; OPTM1: adc
+; OPTM1: ret
define internal i64 @sub64BitSigned(i64 %a, i64 %b) {
entry:
@@ -101,6 +152,11 @@ entry:
; CHECK: sub
; CHECK: sbb
; CHECK: ret
+;
+; OPTM1: sub64BitSigned:
+; OPTM1: sub
+; OPTM1: sbb
+; OPTM1: ret
define internal i64 @sub64BitUnsigned(i64 %a, i64 %b) {
entry:
@@ -111,6 +167,11 @@ entry:
; CHECK: sub
; CHECK: sbb
; CHECK: ret
+;
+; OPTM1: sub64BitUnsigned:
+; OPTM1: sub
+; OPTM1: sbb
+; OPTM1: ret
define internal i64 @mul64BitSigned(i64 %a, i64 %b) {
entry:
@@ -124,6 +185,14 @@ entry:
; CHECK: add
; CHECK: add
; CHECK: ret
+;
+; OPTM1: mul64BitSigned:
+; OPTM1: imul
+; OPTM1: imul
+; OPTM1: mul
+; OPTM1: add
+; OPTM1: add
+; OPTM1: ret
define internal i64 @mul64BitUnsigned(i64 %a, i64 %b) {
entry:
@@ -137,6 +206,14 @@ entry:
; CHECK: add
; CHECK: add
; CHECK: ret
+;
+; OPTM1: mul64BitUnsigned:
+; OPTM1: imul
+; OPTM1: imul
+; OPTM1: mul
+; OPTM1: add
+; OPTM1: add
+; OPTM1: ret
define internal i64 @div64BitSigned(i64 %a, i64 %b) {
entry:
@@ -146,6 +223,10 @@ entry:
; CHECK: div64BitSigned:
; CHECK: call __divdi3
; CHECK: ret
+;
+; OPTM1: div64BitSigned:
+; OPTM1: call __divdi3
+; OPTM1: ret
define internal i64 @div64BitUnsigned(i64 %a, i64 %b) {
entry:
@@ -155,6 +236,10 @@ entry:
; CHECK: div64BitUnsigned:
; CHECK: call __udivdi3
; CHECK: ret
+;
+; OPTM1: div64BitUnsigned:
+; OPTM1: call __udivdi3
+; OPTM1: ret
define internal i64 @rem64BitSigned(i64 %a, i64 %b) {
entry:
@@ -164,6 +249,10 @@ entry:
; CHECK: rem64BitSigned:
; CHECK: call __moddi3
; CHECK: ret
+;
+; OPTM1: rem64BitSigned:
+; OPTM1: call __moddi3
+; OPTM1: ret
define internal i64 @rem64BitUnsigned(i64 %a, i64 %b) {
entry:
@@ -173,6 +262,10 @@ entry:
; CHECK: rem64BitUnsigned:
; CHECK: call __umoddi3
; CHECK: ret
+;
+; OPTM1: rem64BitUnsigned:
+; OPTM1: call __umoddi3
+; OPTM1: ret
define internal i64 @shl64BitSigned(i64 %a, i64 %b) {
entry:
@@ -184,6 +277,12 @@ entry:
; CHECK: shl e
; CHECK: test {{.*}}, 32
; CHECK: je
+;
+; OPTM1: shl64BitSigned:
+; OPTM1: shld
+; OPTM1: shl e
+; OPTM1: test {{.*}}, 32
+; OPTM1: je
define internal i64 @shl64BitUnsigned(i64 %a, i64 %b) {
entry:
@@ -195,6 +294,12 @@ entry:
; CHECK: shl e
; CHECK: test {{.*}}, 32
; CHECK: je
+;
+; OPTM1: shl64BitUnsigned:
+; OPTM1: shld
+; OPTM1: shl e
+; OPTM1: test {{.*}}, 32
+; OPTM1: je
define internal i64 @shr64BitSigned(i64 %a, i64 %b) {
entry:
@@ -207,6 +312,13 @@ entry:
; CHECK: test {{.*}}, 32
; CHECK: je
; CHECK: sar {{.*}}, 31
+;
+; OPTM1: shr64BitSigned:
+; OPTM1: shrd
+; OPTM1: sar
+; OPTM1: test {{.*}}, 32
+; OPTM1: je
+; OPTM1: sar {{.*}}, 31
define internal i64 @shr64BitUnsigned(i64 %a, i64 %b) {
entry:
@@ -218,6 +330,12 @@ entry:
; CHECK: shr
; CHECK: test {{.*}}, 32
; CHECK: je
+;
+; OPTM1: shr64BitUnsigned:
+; OPTM1: shrd
+; OPTM1: shr
+; OPTM1: test {{.*}}, 32
+; OPTM1: je
define internal i64 @and64BitSigned(i64 %a, i64 %b) {
entry:
@@ -227,6 +345,10 @@ entry:
; CHECK: and64BitSigned:
; CHECK: and
; CHECK: and
+;
+; OPTM1: and64BitSigned:
+; OPTM1: and
+; OPTM1: and
define internal i64 @and64BitUnsigned(i64 %a, i64 %b) {
entry:
@@ -236,6 +358,10 @@ entry:
; CHECK: and64BitUnsigned:
; CHECK: and
; CHECK: and
+;
+; OPTM1: and64BitUnsigned:
+; OPTM1: and
+; OPTM1: and
define internal i64 @or64BitSigned(i64 %a, i64 %b) {
entry:
@@ -245,6 +371,10 @@ entry:
; CHECK: or64BitSigned:
; CHECK: or
; CHECK: or
+;
+; OPTM1: or64BitSigned:
+; OPTM1: or
+; OPTM1: or
define internal i64 @or64BitUnsigned(i64 %a, i64 %b) {
entry:
@@ -254,6 +384,10 @@ entry:
; CHECK: or64BitUnsigned:
; CHECK: or
; CHECK: or
+;
+; OPTM1: or64BitUnsigned:
+; OPTM1: or
+; OPTM1: or
define internal i64 @xor64BitSigned(i64 %a, i64 %b) {
entry:
@@ -263,6 +397,10 @@ entry:
; CHECK: xor64BitSigned:
; CHECK: xor
; CHECK: xor
+;
+; OPTM1: xor64BitSigned:
+; OPTM1: xor
+; OPTM1: xor
define internal i64 @xor64BitUnsigned(i64 %a, i64 %b) {
entry:
@@ -272,6 +410,10 @@ entry:
; CHECK: xor64BitUnsigned:
; CHECK: xor
; CHECK: xor
+;
+; OPTM1: xor64BitUnsigned:
+; OPTM1: xor
+; OPTM1: xor
define internal i32 @trunc64To32Signed(i64 %a) {
entry:
@@ -281,6 +423,10 @@ entry:
; CHECK: trunc64To32Signed:
; CHECK: mov eax, dword ptr [esp+4]
; CHECK-NEXT: ret
+;
+; OPTM1: trunc64To32Signed:
+; OPTM1: mov eax, dword ptr [esp+
+; OPTM1: ret
define internal i32 @trunc64To16Signed(i64 %a) {
entry:
@@ -292,6 +438,11 @@ entry:
; CHECK: mov eax, dword ptr [esp+4]
; CHECK-NEXT: movsx eax, ax
; CHECK-NEXT: ret
+;
+; OPTM1: trunc64To16Signed:
+; OPTM1: mov eax, dword ptr [esp+
+; OPTM1: movsx eax,
+; OPTM1: ret
define internal i32 @trunc64To8Signed(i64 %a) {
entry:
@@ -303,6 +454,11 @@ entry:
; CHECK: mov eax, dword ptr [esp+4]
; CHECK-NEXT: movsx eax, al
; CHECK-NEXT: ret
+;
+; OPTM1: trunc64To8Signed:
+; OPTM1: mov eax, dword ptr [esp+
+; OPTM1: movsx eax,
+; OPTM1: ret
define internal i32 @trunc64To32Unsigned(i64 %a) {
entry:
@@ -312,6 +468,10 @@ entry:
; CHECK: trunc64To32Unsigned:
; CHECK: mov eax, dword ptr [esp+4]
; CHECK-NEXT: ret
+;
+; OPTM1: trunc64To32Unsigned:
+; OPTM1: mov eax, dword ptr [esp+
+; OPTM1: ret
define internal i32 @trunc64To16Unsigned(i64 %a) {
entry:
@@ -323,6 +483,11 @@ entry:
; CHECK: mov eax, dword ptr [esp+4]
; CHECK-NEXT: movzx eax, ax
; CHECK-NEXT: ret
+;
+; OPTM1: trunc64To16Unsigned:
+; OPTM1: mov eax, dword ptr [esp+
+; OPTM1: movzx eax,
+; OPTM1: ret
define internal i32 @trunc64To8Unsigned(i64 %a) {
entry:
@@ -334,6 +499,11 @@ entry:
; CHECK: mov eax, dword ptr [esp+4]
; CHECK-NEXT: movzx eax, al
; CHECK-NEXT: ret
+;
+; OPTM1: trunc64To8Unsigned:
+; OPTM1: mov eax, dword ptr [esp+
+; OPTM1: movzx eax,
+; OPTM1: ret
define internal i32 @trunc64To1(i64 %a) {
entry:
@@ -346,6 +516,11 @@ entry:
; CHECK: mov eax, dword ptr [esp+4]
; CHECK: and eax, 1
; CHECK-NEXT: ret
+;
+; OPTM1: trunc64To1:
+; OPTM1: mov eax, dword ptr [esp+
+; OPTM1: and eax, 1
+; OPTM1: ret
define internal i64 @sext32To64(i32 %a) {
entry:
@@ -355,6 +530,10 @@ entry:
; CHECK: sext32To64:
; CHECK: mov
; CHECK: sar {{.*}}, 31
+;
+; OPTM1: sext32To64:
+; OPTM1: mov
+; OPTM1: sar {{.*}}, 31
define internal i64 @sext16To64(i32 %a) {
entry:
@@ -365,6 +544,10 @@ entry:
; CHECK: sext16To64:
; CHECK: movsx
; CHECK: sar {{.*}}, 31
+;
+; OPTM1: sext16To64:
+; OPTM1: movsx
+; OPTM1: sar {{.*}}, 31
define internal i64 @sext8To64(i32 %a) {
entry:
@@ -375,6 +558,10 @@ entry:
; CHECK: sext8To64:
; CHECK: movsx
; CHECK: sar {{.*}}, 31
+;
+; OPTM1: sext8To64:
+; OPTM1: movsx
+; OPTM1: sar {{.*}}, 31
define internal i64 @zext32To64(i32 %a) {
entry:
@@ -384,6 +571,10 @@ entry:
; CHECK: zext32To64:
; CHECK: mov
; CHECK: mov {{.*}}, 0
+;
+; OPTM1: zext32To64:
+; OPTM1: mov
+; OPTM1: mov {{.*}}, 0
define internal i64 @zext16To64(i32 %a) {
entry:
@@ -394,6 +585,10 @@ entry:
; CHECK: zext16To64:
; CHECK: movzx
; CHECK: mov {{.*}}, 0
+;
+; OPTM1: zext16To64:
+; OPTM1: movzx
+; OPTM1: mov {{.*}}, 0
define internal i64 @zext8To64(i32 %a) {
entry:
@@ -404,6 +599,10 @@ entry:
; CHECK: zext8To64:
; CHECK: movzx
; CHECK: mov {{.*}}, 0
+;
+; OPTM1: zext8To64:
+; OPTM1: movzx
+; OPTM1: mov {{.*}}, 0
define internal i64 @zext1To64(i32 %a) {
entry:
@@ -414,6 +613,10 @@ entry:
; CHECK: zext1To64:
; CHECK: movzx
; CHECK: mov {{.*}}, 0
+;
+; OPTM1: zext1To64:
+; OPTM1: movzx
+; OPTM1: mov {{.*}}, 0
define internal void @icmpEq64(i64 %a, i64 %b, i64 %c, i64 %d) {
entry:
@@ -442,6 +645,14 @@ if.end3: ; preds = %if.then2, %if.end
; CHECK: jne
; CHECK: jne
; CHECK: call
+;
+; OPTM1: icmpEq64:
+; OPTM1: jne
+; OPTM1: jne
+; OPTM1: call
+; OPTM1: jne
+; OPTM1: jne
+; OPTM1: call
declare void @func()
@@ -472,6 +683,14 @@ if.end3: ; preds = %if.end, %if.then2
; CHECK: jne
; CHECK: jne
; CHECK: call
+;
+; OPTM1: icmpNe64:
+; OPTM1: jne
+; OPTM1: jne
+; OPTM1: call
+; OPTM1: jne
+; OPTM1: jne
+; OPTM1: call
define internal void @icmpGt64(i64 %a, i64 %b, i64 %c, i64 %d) {
entry:
@@ -502,6 +721,16 @@ if.end3: ; preds = %if.then2, %if.end
; CHECK: jl
; CHECK: ja
; CHECK: call
+;
+; OPTM1: icmpGt64:
+; OPTM1: ja
+; OPTM1: jb
+; OPTM1: ja
+; OPTM1: call
+; OPTM1: jg
+; OPTM1: jl
+; OPTM1: ja
+; OPTM1: call
define internal void @icmpGe64(i64 %a, i64 %b, i64 %c, i64 %d) {
entry:
@@ -532,6 +761,16 @@ if.end3: ; preds = %if.end, %if.then2
; CHECK: jl
; CHECK: jae
; CHECK: call
+;
+; OPTM1: icmpGe64:
+; OPTM1: ja
+; OPTM1: jb
+; OPTM1: jae
+; OPTM1: call
+; OPTM1: jg
+; OPTM1: jl
+; OPTM1: jae
+; OPTM1: call
define internal void @icmpLt64(i64 %a, i64 %b, i64 %c, i64 %d) {
entry:
@@ -562,6 +801,16 @@ if.end3: ; preds = %if.then2, %if.end
; CHECK: jg
; CHECK: jb
; CHECK: call
+;
+; OPTM1: icmpLt64:
+; OPTM1: jb
+; OPTM1: ja
+; OPTM1: jb
+; OPTM1: call
+; OPTM1: jl
+; OPTM1: jg
+; OPTM1: jb
+; OPTM1: call
define internal void @icmpLe64(i64 %a, i64 %b, i64 %c, i64 %d) {
entry:
@@ -592,6 +841,16 @@ if.end3: ; preds = %if.end, %if.then2
; CHECK: jg
; CHECK: jbe
; CHECK: call
+;
+; OPTM1: icmpLe64:
+; OPTM1: jb
+; OPTM1: ja
+; OPTM1: jbe
+; OPTM1: call
+; OPTM1: jl
+; OPTM1: jg
+; OPTM1: jbe
+; OPTM1: call
define internal i32 @icmpEq64Bool(i64 %a, i64 %b) {
entry:
@@ -602,6 +861,10 @@ entry:
; CHECK: icmpEq64Bool:
; CHECK: jne
; CHECK: jne
+;
+; OPTM1: icmpEq64Bool:
+; OPTM1: jne
+; OPTM1: jne
define internal i32 @icmpNe64Bool(i64 %a, i64 %b) {
entry:
@@ -612,6 +875,10 @@ entry:
; CHECK: icmpNe64Bool:
; CHECK: jne
; CHECK: jne
+;
+; OPTM1: icmpNe64Bool:
+; OPTM1: jne
+; OPTM1: jne
define internal i32 @icmpSgt64Bool(i64 %a, i64 %b) {
entry:
@@ -625,6 +892,13 @@ entry:
; CHECK: jl
; CHECK: cmp
; CHECK: ja
+;
+; OPTM1: icmpSgt64Bool:
+; OPTM1: cmp
+; OPTM1: jg
+; OPTM1: jl
+; OPTM1: cmp
+; OPTM1: ja
define internal i32 @icmpUgt64Bool(i64 %a, i64 %b) {
entry:
@@ -638,6 +912,13 @@ entry:
; CHECK: jb
; CHECK: cmp
; CHECK: ja
+;
+; OPTM1: icmpUgt64Bool:
+; OPTM1: cmp
+; OPTM1: ja
+; OPTM1: jb
+; OPTM1: cmp
+; OPTM1: ja
define internal i32 @icmpSge64Bool(i64 %a, i64 %b) {
entry:
@@ -651,6 +932,13 @@ entry:
; CHECK: jl
; CHECK: cmp
; CHECK: jae
+;
+; OPTM1: icmpSge64Bool:
+; OPTM1: cmp
+; OPTM1: jg
+; OPTM1: jl
+; OPTM1: cmp
+; OPTM1: jae
define internal i32 @icmpUge64Bool(i64 %a, i64 %b) {
entry:
@@ -664,6 +952,13 @@ entry:
; CHECK: jb
; CHECK: cmp
; CHECK: jae
+;
+; OPTM1: icmpUge64Bool:
+; OPTM1: cmp
+; OPTM1: ja
+; OPTM1: jb
+; OPTM1: cmp
+; OPTM1: jae
define internal i32 @icmpSlt64Bool(i64 %a, i64 %b) {
entry:
@@ -677,6 +972,13 @@ entry:
; CHECK: jg
; CHECK: cmp
; CHECK: jb
+;
+; OPTM1: icmpSlt64Bool:
+; OPTM1: cmp
+; OPTM1: jl
+; OPTM1: jg
+; OPTM1: cmp
+; OPTM1: jb
define internal i32 @icmpUlt64Bool(i64 %a, i64 %b) {
entry:
@@ -690,6 +992,13 @@ entry:
; CHECK: ja
; CHECK: cmp
; CHECK: jb
+;
+; OPTM1: icmpUlt64Bool:
+; OPTM1: cmp
+; OPTM1: jb
+; OPTM1: ja
+; OPTM1: cmp
+; OPTM1: jb
define internal i32 @icmpSle64Bool(i64 %a, i64 %b) {
entry:
@@ -703,6 +1012,13 @@ entry:
; CHECK: jg
; CHECK: cmp
; CHECK: jbe
+;
+; OPTM1: icmpSle64Bool:
+; OPTM1: cmp
+; OPTM1: jl
+; OPTM1: jg
+; OPTM1: cmp
+; OPTM1: jbe
define internal i32 @icmpUle64Bool(i64 %a, i64 %b) {
entry:
@@ -716,6 +1032,13 @@ entry:
; CHECK: ja
; CHECK: cmp
; CHECK: jbe
+;
+; OPTM1: icmpUle64Bool:
+; OPTM1: cmp
+; OPTM1: jb
+; OPTM1: ja
+; OPTM1: cmp
+; OPTM1: jbe
define internal i64 @load64(i32 %a) {
entry:
@@ -727,6 +1050,10 @@ entry:
; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp+4]
; CHECK-NEXT: mov {{.*}}, dword ptr [e[[REGISTER]]]
; CHECK-NEXT: mov {{.*}}, dword ptr [e[[REGISTER]]+4]
+;
+; OPTM1: load64:
+; OPTM1: mov e{{..}}, dword ptr [e{{..}}]
+; OPTM1: mov e{{..}}, dword ptr [e{{..}}+4]
define internal void @store64(i32 %a, i64 %value) {
entry:
@@ -738,6 +1065,10 @@ entry:
; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp+4]
; CHECK: mov dword ptr [e[[REGISTER]]+4],
; CHECK: mov dword ptr [e[[REGISTER]]],
+;
+; OPTM1: store64:
+; OPTM1: mov dword ptr [e[[REGISTER:[a-z]+]]+4],
+; OPTM1: mov dword ptr [e[[REGISTER]]],
define internal void @store64Const(i32 %a) {
entry:
@@ -749,6 +1080,10 @@ entry:
; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp+4]
; CHECK: mov dword ptr [e[[REGISTER]]+4], 3735928559
; CHECK: mov dword ptr [e[[REGISTER]]], 305419896
+;
+; OPTM1: store64Const:
+; OPTM1: mov dword ptr [e[[REGISTER:[a-z]+]]+4], 3735928559
+; OPTM1: mov dword ptr [e[[REGISTER]]], 305419896
define internal i64 @select64VarVar(i64 %a, i64 %b) {
entry:
@@ -764,6 +1099,15 @@ entry:
; CHECK: jb
; CHECK: cmp
; CHECK: jne
+;
+; OPTM1: select64VarVar:
+; OPTM1: cmp
+; OPTM1: jb
+; OPTM1: ja
+; OPTM1: cmp
+; OPTM1: jb
+; OPTM1: cmp
+; OPTM1: jne
define internal i64 @select64VarConst(i64 %a, i64 %b) {
entry:
@@ -779,6 +1123,15 @@ entry:
; CHECK: jb
; CHECK: cmp
; CHECK: jne
+;
+; OPTM1: select64VarConst:
+; OPTM1: cmp
+; OPTM1: jb
+; OPTM1: ja
+; OPTM1: cmp
+; OPTM1: jb
+; OPTM1: cmp
+; OPTM1: jne
define internal i64 @select64ConstVar(i64 %a, i64 %b) {
entry:
@@ -794,6 +1147,15 @@ entry:
; CHECK: jb
; CHECK: cmp
; CHECK: jne
+;
+; OPTM1: select64ConstVar:
+; OPTM1: cmp
+; OPTM1: jb
+; OPTM1: ja
+; OPTM1: cmp
+; OPTM1: jb
+; OPTM1: cmp
+; OPTM1: jne
; ERRORS-NOT: ICE translation error
; DUMP-NOT: SZ
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