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Unified Diff: tests_lit/llvm2ice_tests/convert.ll

Issue 265703002: Add Om1 lowering with no optimizations (Closed) Base URL: https://gerrit.chromium.org/gerrit/p/native_client/pnacl-subzero.git@master
Patch Set: Address Jan's second-round comments Created 6 years, 7 months ago
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« src/IceTargetLoweringX8632.cpp ('K') | « tests_lit/llvm2ice_tests/cmp-opt.ll ('k') | tests_lit/llvm2ice_tests/empty-func.ll » ('j') | no next file with comments »
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Index: tests_lit/llvm2ice_tests/convert.ll
diff --git a/tests_lit/llvm2ice_tests/convert.ll b/tests_lit/llvm2ice_tests/convert.ll
index 53a1de4391466144a9c7a288655f33338c8571c7..1fde62d3475ea17b47543b6c78144c604aad5518 100644
--- a/tests_lit/llvm2ice_tests/convert.ll
+++ b/tests_lit/llvm2ice_tests/convert.ll
@@ -1,5 +1,8 @@
-; RUIN: %llvm2ice %s | FileCheck %s
-; RUIN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
+; Simple test of signed and unsigned integer conversions.
+
+; RUIN: %llvm2ice -O2 --verbose none %s | FileCheck %s
+; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck --check-prefix=OPTM1 %s
+; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
; RUN: %szdiff --llvm2ice=%llvm2ice %s | FileCheck --check-prefix=DUMP %s
@i8v = common global i8 0, align 1
@@ -25,16 +28,28 @@ entry:
%v3 = sext i8 %v0 to i64
store i64 %v3, i64* @i64v, align 1
ret void
- ; CHECK: mov al, byte ptr [
- ; CHECK-NEXT: movsx cx, al
- ; CHECK-NEXT: mov word ptr [
- ; CHECK-NEXT: movsx ecx, al
- ; CHECK-NEXT: mov dword ptr [
- ; CHECK-NEXT: movsx ecx, al
- ; CHECK-NEXT: sar eax, 31
- ; CHECK-NEXT: mov dword ptr [i64v+4],
- ; CHECK-NEXT: mov dword ptr [i64v],
}
+; CHECK: from_int8:
+; CHECK: mov al, byte ptr [
+; CHECK-NEXT: movsx cx, al
+; CHECK-NEXT: mov word ptr [
+; CHECK-NEXT: movsx ecx, al
+; CHECK-NEXT: mov dword ptr [
+; CHECK-NEXT: movsx ecx, al
+; CHECK-NEXT: sar eax, 31
+; CHECK-NEXT: mov dword ptr [i64v+4],
+; CHECK-NEXT: mov dword ptr [i64v],
+;
+; OPTM1: from_int8:
+; OPTM1: mov {{.*}}, byte ptr [
+; OPTM1: movsx
+; OPTM1: mov word ptr [
+; OPTM1: movsx
+; OPTM1: mov dword ptr [
+; OPTM1: movsx
+; OPTM1: sar {{.*}}, 31
+; OPTM1: mov dword ptr [i64v+4],
+; OPTM1: mov dword ptr [i64v],
define void @from_int16() {
entry:
@@ -46,16 +61,27 @@ entry:
%v3 = sext i16 %v0 to i64
store i64 %v3, i64* @i64v, align 1
ret void
- ; CHECK: mov ax, word ptr [
- ; CHECK-NEXT: mov cx, ax
- ; CHECK-NEXT: mov byte ptr [
- ; CHECK-NEXT: movsx ecx, ax
- ; CHECK-NEXT: mov dword ptr [
- ; CHECK-NEXT: movsx ecx, ax
- ; CHECK-NEXT: sar eax, 31
- ; CHECK-NEXT: mov dword ptr [i64v+4],
- ; CHECK-NEXT: mov dword ptr [i64v],
}
+; CHECK: from_int16:
+; CHECK: mov ax, word ptr [
+; CHECK-NEXT: mov cx, ax
+; CHECK-NEXT: mov byte ptr [
+; CHECK-NEXT: movsx ecx, ax
+; CHECK-NEXT: mov dword ptr [
+; CHECK-NEXT: movsx ecx, ax
+; CHECK-NEXT: sar eax, 31
+; CHECK-NEXT: mov dword ptr [i64v+4],
+; CHECK-NEXT: mov dword ptr [i64v],
+;
+; OPTM1: from_int16:
+; OPTM1: mov {{.*}}, word ptr [
+; OPTM1: mov byte ptr [i8v],
+; OPTM1: movsx
+; OPTM1: mov dword ptr [i32v],
+; OPTM1: movsx
+; OPTM1: sar {{.*}}, 31
+; OPTM1: mov dword ptr [i64v+4],
+; OPTM1: mov dword ptr [i64v],
define void @from_int32() {
entry:
@@ -67,16 +93,25 @@ entry:
%v3 = sext i32 %v0 to i64
store i64 %v3, i64* @i64v, align 1
ret void
- ; CHECK: mov eax, dword ptr [
- ; CHECK-NEXT: mov ecx, eax
- ; CHECK-NEXT: mov byte ptr [
- ; CHECK-NEXT: mov ecx, eax
- ; CHECK-NEXT: mov word ptr [
- ; CHECK-NEXT: mov ecx, eax
- ; CHECK-NEXT: sar eax, 31
- ; CHECK-NEXT: mov dword ptr [i64v+4],
- ; CHECK-NEXT: mov dword ptr [i64v],
}
+; CHECK: from_int32:
+; CHECK: mov eax, dword ptr [
+; CHECK-NEXT: mov ecx, eax
+; CHECK-NEXT: mov byte ptr [
+; CHECK-NEXT: mov ecx, eax
+; CHECK-NEXT: mov word ptr [
+; CHECK-NEXT: mov ecx, eax
+; CHECK-NEXT: sar eax, 31
+; CHECK-NEXT: mov dword ptr [i64v+4],
+; CHECK-NEXT: mov dword ptr [i64v],
+;
+; OPTM1: from_int32:
+; OPTM1: mov {{.*}}, dword ptr [i32v]
+; OPTM1: mov byte ptr [i8v],
+; OPTM1: mov word ptr [i16v],
+; OPTM1: sar {{.*}}, 31
+; OPTM1: mov dword ptr [i64v+4],
+; OPTM1: mov dword ptr [i64v],
define void @from_int64() {
entry:
@@ -88,13 +123,21 @@ entry:
%v3 = trunc i64 %v0 to i32
store i32 %v3, i32* @i32v, align 1
ret void
- ; CHECK: mov eax, dword ptr [
- ; CHECK-NEXT: mov ecx, eax
- ; CHECK-NEXT: mov byte ptr [
- ; CHECK-NEXT: mov ecx, eax
- ; CHECK-NEXT: mov word ptr [
- ; CHECK-NEXT: mov dword ptr [
}
+; CHECK: from_int64:
+; CHECK: mov eax, dword ptr [
+; CHECK-NEXT: mov ecx, eax
+; CHECK-NEXT: mov byte ptr [
+; CHECK-NEXT: mov ecx, eax
+; CHECK-NEXT: mov word ptr [
+; CHECK-NEXT: mov dword ptr [
+;
+; OPTM1: from_int64:
+; OPTM1: mov {{.*}}, dword ptr [i64v]
+; OPTM1: mov {{.*}}, dword ptr [i64v+4]
+; OPTM1: mov byte ptr [i8v],
+; OPTM1: mov word ptr [i16v],
+; OPTM1: mov dword ptr [i32v],
define void @from_uint8() {
entry:
@@ -106,16 +149,28 @@ entry:
%v3 = zext i8 %v0 to i64
store i64 %v3, i64* @i64v, align 1
ret void
- ; CHECK: mov al, byte ptr [
- ; CHECK-NEXT: movzx cx, al
- ; CHECK-NEXT: mov word ptr [
- ; CHECK-NEXT: movzx ecx, al
- ; CHECK-NEXT: mov dword ptr [
- ; CHECK-NEXT: movzx eax, al
- ; CHECK-NEXT: mov ecx, 0
- ; CHECK-NEXT: mov dword ptr [i64v+4],
- ; CHECK-NEXT: mov dword ptr [i64v],
}
+; CHECK: from_uint8:
+; CHECK: mov al, byte ptr [
+; CHECK-NEXT: movzx cx, al
+; CHECK-NEXT: mov word ptr [
+; CHECK-NEXT: movzx ecx, al
+; CHECK-NEXT: mov dword ptr [
+; CHECK-NEXT: movzx eax, al
+; CHECK-NEXT: mov ecx, 0
+; CHECK-NEXT: mov dword ptr [i64v+4],
+; CHECK-NEXT: mov dword ptr [i64v],
+;
+; OPTM1: from_uint8:
+; OPTM1: mov {{.*}}, byte ptr [u8v]
+; OPTM1: movzx
+; OPTM1: mov word ptr [i16v],
+; OPTM1: movzx
+; OPTM1: mov dword ptr [i32v],
+; OPTM1: movzx
+; OPTM1: mov {{.*}}, 0
+; OPTM1: mov dword ptr [i64v+4],
+; OPTM1: mov dword ptr [i64v],
define void @from_uint16() {
entry:
@@ -127,16 +182,27 @@ entry:
%v3 = zext i16 %v0 to i64
store i64 %v3, i64* @i64v, align 1
ret void
- ; CHECK: mov ax, word ptr [
- ; CHECK-NEXT: mov cx, ax
- ; CHECK-NEXT: mov byte ptr [
- ; CHECK-NEXT: movzx ecx, ax
- ; CHECK-NEXT: mov dword ptr [
- ; CHECK-NEXT: movzx eax, ax
- ; CHECK-NEXT: mov ecx, 0
- ; CHECK-NEXT: mov dword ptr [i64v+4],
- ; CHECK-NEXT: mov dword ptr [i64v],
}
+; CHECK: from_uint16:
+; CHECK: mov ax, word ptr [
+; CHECK-NEXT: mov cx, ax
+; CHECK-NEXT: mov byte ptr [
+; CHECK-NEXT: movzx ecx, ax
+; CHECK-NEXT: mov dword ptr [
+; CHECK-NEXT: movzx eax, ax
+; CHECK-NEXT: mov ecx, 0
+; CHECK-NEXT: mov dword ptr [i64v+4],
+; CHECK-NEXT: mov dword ptr [i64v],
+;
+; OPTM1: from_uint16:
+; OPTM1: mov {{.*}}, word ptr [u16v]
+; OPTM1: mov byte ptr [i8v],
+; OPTM1: movzx
+; OPTM1: mov dword ptr [i32v],
+; OPTM1: movzx
+; OPTM1: mov {{.*}}, 0
+; OPTM1: mov dword ptr [i64v+4],
+; OPTM1: mov dword ptr [i64v],
define void @from_uint32() {
entry:
@@ -148,15 +214,24 @@ entry:
%v3 = zext i32 %v0 to i64
store i64 %v3, i64* @i64v, align 1
ret void
- ; CHECK: mov eax, dword ptr [
- ; CHECK-NEXT: mov ecx, eax
- ; CHECK-NEXT: mov byte ptr [
- ; CHECK-NEXT: mov ecx, eax
- ; CHECK-NEXT: mov word ptr [
- ; CHECK-NEXT: mov ecx, 0
- ; CHECK-NEXT: mov dword ptr [i64v+4],
- ; CHECK-NEXT: mov dword ptr [i64v],
}
+; CHECK: from_uint32:
+; CHECK: mov eax, dword ptr [
+; CHECK-NEXT: mov ecx, eax
+; CHECK-NEXT: mov byte ptr [
+; CHECK-NEXT: mov ecx, eax
+; CHECK-NEXT: mov word ptr [
+; CHECK-NEXT: mov ecx, 0
+; CHECK-NEXT: mov dword ptr [i64v+4],
+; CHECK-NEXT: mov dword ptr [i64v],
+;
+; OPTM1: from_uint32:
+; OPTM1: mov {{.*}}, dword ptr [u32v]
+; OPTM1: mov byte ptr [i8v],
+; OPTM1: mov word ptr [i16v],
+; OPTM1: mov {{.*}}, 0
+; OPTM1: mov dword ptr [i64v+4],
+; OPTM1: mov dword ptr [i64v],
define void @from_uint64() {
entry:
@@ -168,13 +243,20 @@ entry:
%v3 = trunc i64 %v0 to i32
store i32 %v3, i32* @i32v, align 1
ret void
- ; CHECK: mov eax, dword ptr [
- ; CHECK-NEXT: mov ecx, eax
- ; CHECK-NEXT: mov byte ptr [
- ; CHECK-NEXT: mov ecx, eax
- ; CHECK-NEXT: mov word ptr [
- ; CHECK-NEXT: mov dword ptr [
}
+; CHECK: from_uint64:
+; CHECK: mov eax, dword ptr [
+; CHECK-NEXT: mov ecx, eax
+; CHECK-NEXT: mov byte ptr [
+; CHECK-NEXT: mov ecx, eax
+; CHECK-NEXT: mov word ptr [
+; CHECK-NEXT: mov dword ptr [
+;
+; OPTM1: from_uint64:
+; OPTM1: mov eax, dword ptr [u64v]
+; OPTM1: mov byte ptr [i8v],
+; OPTM1: mov word ptr [i16v],
+; OPTM1: mov dword ptr [i32v],
; ERRORS-NOT: ICE translation error
; DUMP-NOT: SZ
« src/IceTargetLoweringX8632.cpp ('K') | « tests_lit/llvm2ice_tests/cmp-opt.ll ('k') | tests_lit/llvm2ice_tests/empty-func.ll » ('j') | no next file with comments »

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