OLD | NEW |
1 ; RUIN: %llvm2ice --verbose none %s | FileCheck %s | 1 ; This tries to be a comprehensive test of i64 operations, in |
2 ; RUIN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s | 2 ; particular the patterns for lowering i64 operations into constituent |
| 3 ; i32 operations on x86-32. |
| 4 |
| 5 ; RUIN: %llvm2ice -O2 --verbose none %s | FileCheck %s |
| 6 ; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck --check-prefix=OPTM1 %s |
| 7 ; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s |
3 ; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s | 8 ; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s |
4 ; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \ | 9 ; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \ |
5 ; RUN: | FileCheck --check-prefix=DUMP %s | 10 ; RUN: | FileCheck --check-prefix=DUMP %s |
6 | 11 |
7 @__init_array_start = internal constant [0 x i8] zeroinitializer, align 4 | 12 @__init_array_start = internal constant [0 x i8] zeroinitializer, align 4 |
8 @__fini_array_start = internal constant [0 x i8] zeroinitializer, align 4 | 13 @__fini_array_start = internal constant [0 x i8] zeroinitializer, align 4 |
9 @__tls_template_start = internal constant [0 x i8] zeroinitializer, align 8 | 14 @__tls_template_start = internal constant [0 x i8] zeroinitializer, align 8 |
10 @__tls_template_alignment = internal constant [4 x i8] c"\01\00\00\00", align 4 | 15 @__tls_template_alignment = internal constant [4 x i8] c"\01\00\00\00", align 4 |
11 | 16 |
12 define internal i32 @ignore64BitArg(i64 %a, i32 %b, i64 %c) { | 17 define internal i32 @ignore64BitArg(i64 %a, i32 %b, i64 %c) { |
(...skipping 20 matching lines...) Expand all Loading... |
33 ; CHECK-NEXT: push 123 | 38 ; CHECK-NEXT: push 123 |
34 ; CHECK-NEXT: push | 39 ; CHECK-NEXT: push |
35 ; CHECK-NEXT: push | 40 ; CHECK-NEXT: push |
36 ; CHECK-NEXT: call ignore64BitArgNoInline | 41 ; CHECK-NEXT: call ignore64BitArgNoInline |
37 ; CHECK: push | 42 ; CHECK: push |
38 ; CHECK-NEXT: push | 43 ; CHECK-NEXT: push |
39 ; CHECK-NEXT: push 123 | 44 ; CHECK-NEXT: push 123 |
40 ; CHECK-NEXT: push | 45 ; CHECK-NEXT: push |
41 ; CHECK-NEXT: push | 46 ; CHECK-NEXT: push |
42 ; CHECK-NEXT: call ignore64BitArgNoInline | 47 ; CHECK-NEXT: call ignore64BitArgNoInline |
| 48 ; |
| 49 ; OPTM1: pass64BitArg: |
| 50 ; OPTM1: push 123 |
| 51 ; OPTM1-NEXT: push |
| 52 ; OPTM1-NEXT: push |
| 53 ; OPTM1-NEXT: call ignore64BitArgNoInline |
| 54 ; OPTM1: push |
| 55 ; OPTM1-NEXT: push |
| 56 ; OPTM1-NEXT: push 123 |
| 57 ; OPTM1-NEXT: push |
| 58 ; OPTM1-NEXT: push |
| 59 ; OPTM1-NEXT: call ignore64BitArgNoInline |
| 60 ; OPTM1: push |
| 61 ; OPTM1-NEXT: push |
| 62 ; OPTM1-NEXT: push 123 |
| 63 ; OPTM1-NEXT: push |
| 64 ; OPTM1-NEXT: push |
| 65 ; OPTM1-NEXT: call ignore64BitArgNoInline |
43 | 66 |
44 declare i32 @ignore64BitArgNoInline(i64, i32, i64) | 67 declare i32 @ignore64BitArgNoInline(i64, i32, i64) |
45 | 68 |
46 define internal i32 @pass64BitConstArg(i64 %a, i64 %b) { | 69 define internal i32 @pass64BitConstArg(i64 %a, i64 %b) { |
47 entry: | 70 entry: |
48 %call = call i32 @ignore64BitArgNoInline(i64 %a, i32 123, i64 -240105309230672
5256) | 71 %call = call i32 @ignore64BitArgNoInline(i64 %a, i32 123, i64 -240105309230672
5256) |
49 ret i32 %call | 72 ret i32 %call |
50 } | 73 } |
51 ; CHECK: pass64BitConstArg: | 74 ; CHECK: pass64BitConstArg: |
52 ; CHECK: push 3735928559 | 75 ; CHECK: push 3735928559 |
53 ; CHECK-NEXT: push 305419896 | 76 ; CHECK-NEXT: push 305419896 |
54 ; CHECK-NEXT: push 123 | 77 ; CHECK-NEXT: push 123 |
55 ; CHECK-NEXT: push ecx | 78 ; CHECK-NEXT: push ecx |
56 ; CHECK-NEXT: push eax | 79 ; CHECK-NEXT: push eax |
57 ; CHECK-NEXT: call ignore64BitArgNoInline | 80 ; CHECK-NEXT: call ignore64BitArgNoInline |
| 81 ; |
| 82 ; OPTM1: pass64BitConstArg: |
| 83 ; OPTM1: push 3735928559 |
| 84 ; OPTM1-NEXT: push 305419896 |
| 85 ; OPTM1-NEXT: push 123 |
| 86 ; OPTM1-NEXT: push dword ptr [ |
| 87 ; OPTM1-NEXT: push dword ptr [ |
| 88 ; OPTM1-NEXT: call ignore64BitArgNoInline |
58 | 89 |
59 define internal i64 @return64BitArg(i64 %a) { | 90 define internal i64 @return64BitArg(i64 %a) { |
60 entry: | 91 entry: |
61 ret i64 %a | 92 ret i64 %a |
62 } | 93 } |
63 ; CHECK: return64BitArg: | 94 ; CHECK: return64BitArg: |
64 ; CHECK: mov {{.*}}, dword ptr [esp+4] | 95 ; CHECK: mov {{.*}}, dword ptr [esp+4] |
65 ; CHECK: mov {{.*}}, dword ptr [esp+8] | 96 ; CHECK: mov {{.*}}, dword ptr [esp+8] |
66 ; CHECK: ret | 97 ; CHECK: ret |
| 98 ; |
| 99 ; OPTM1: return64BitArg: |
| 100 ; OPTM1: mov {{.*}}, dword ptr [esp+4] |
| 101 ; OPTM1: mov {{.*}}, dword ptr [esp+8] |
| 102 ; OPTM1: ret |
67 | 103 |
68 define internal i64 @return64BitConst() { | 104 define internal i64 @return64BitConst() { |
69 entry: | 105 entry: |
70 ret i64 -2401053092306725256 | 106 ret i64 -2401053092306725256 |
71 } | 107 } |
72 ; CHECK: return64BitConst: | 108 ; CHECK: return64BitConst: |
73 ; CHECK: mov eax, 305419896 | 109 ; CHECK: mov eax, 305419896 |
74 ; CHECK: mov edx, 3735928559 | 110 ; CHECK: mov edx, 3735928559 |
75 ; CHECK: ret | 111 ; CHECK: ret |
| 112 ; |
| 113 ; OPTM1: return64BitConst: |
| 114 ; OPTM1: mov eax, 305419896 |
| 115 ; OPTM1: mov edx, 3735928559 |
| 116 ; OPTM1: ret |
76 | 117 |
77 define internal i64 @add64BitSigned(i64 %a, i64 %b) { | 118 define internal i64 @add64BitSigned(i64 %a, i64 %b) { |
78 entry: | 119 entry: |
79 %add = add i64 %b, %a | 120 %add = add i64 %b, %a |
80 ret i64 %add | 121 ret i64 %add |
81 } | 122 } |
82 ; CHECK: add64BitSigned: | 123 ; CHECK: add64BitSigned: |
83 ; CHECK: add | 124 ; CHECK: add |
84 ; CHECK: adc | 125 ; CHECK: adc |
85 ; CHECK: ret | 126 ; CHECK: ret |
| 127 ; |
| 128 ; OPTM1: add64BitSigned: |
| 129 ; OPTM1: add |
| 130 ; OPTM1: adc |
| 131 ; OPTM1: ret |
86 | 132 |
87 define internal i64 @add64BitUnsigned(i64 %a, i64 %b) { | 133 define internal i64 @add64BitUnsigned(i64 %a, i64 %b) { |
88 entry: | 134 entry: |
89 %add = add i64 %b, %a | 135 %add = add i64 %b, %a |
90 ret i64 %add | 136 ret i64 %add |
91 } | 137 } |
92 ; CHECK: add64BitUnsigned: | 138 ; CHECK: add64BitUnsigned: |
93 ; CHECK: add | 139 ; CHECK: add |
94 ; CHECK: adc | 140 ; CHECK: adc |
95 ; CHECK: ret | 141 ; CHECK: ret |
| 142 ; |
| 143 ; OPTM1: add64BitUnsigned: |
| 144 ; OPTM1: add |
| 145 ; OPTM1: adc |
| 146 ; OPTM1: ret |
96 | 147 |
97 define internal i64 @sub64BitSigned(i64 %a, i64 %b) { | 148 define internal i64 @sub64BitSigned(i64 %a, i64 %b) { |
98 entry: | 149 entry: |
99 %sub = sub i64 %a, %b | 150 %sub = sub i64 %a, %b |
100 ret i64 %sub | 151 ret i64 %sub |
101 } | 152 } |
102 ; CHECK: sub64BitSigned: | 153 ; CHECK: sub64BitSigned: |
103 ; CHECK: sub | 154 ; CHECK: sub |
104 ; CHECK: sbb | 155 ; CHECK: sbb |
105 ; CHECK: ret | 156 ; CHECK: ret |
| 157 ; |
| 158 ; OPTM1: sub64BitSigned: |
| 159 ; OPTM1: sub |
| 160 ; OPTM1: sbb |
| 161 ; OPTM1: ret |
106 | 162 |
107 define internal i64 @sub64BitUnsigned(i64 %a, i64 %b) { | 163 define internal i64 @sub64BitUnsigned(i64 %a, i64 %b) { |
108 entry: | 164 entry: |
109 %sub = sub i64 %a, %b | 165 %sub = sub i64 %a, %b |
110 ret i64 %sub | 166 ret i64 %sub |
111 } | 167 } |
112 ; CHECK: sub64BitUnsigned: | 168 ; CHECK: sub64BitUnsigned: |
113 ; CHECK: sub | 169 ; CHECK: sub |
114 ; CHECK: sbb | 170 ; CHECK: sbb |
115 ; CHECK: ret | 171 ; CHECK: ret |
| 172 ; |
| 173 ; OPTM1: sub64BitUnsigned: |
| 174 ; OPTM1: sub |
| 175 ; OPTM1: sbb |
| 176 ; OPTM1: ret |
116 | 177 |
117 define internal i64 @mul64BitSigned(i64 %a, i64 %b) { | 178 define internal i64 @mul64BitSigned(i64 %a, i64 %b) { |
118 entry: | 179 entry: |
119 %mul = mul i64 %b, %a | 180 %mul = mul i64 %b, %a |
120 ret i64 %mul | 181 ret i64 %mul |
121 } | 182 } |
122 ; CHECK: mul64BitSigned: | 183 ; CHECK: mul64BitSigned: |
123 ; CHECK: imul | 184 ; CHECK: imul |
124 ; CHECK: imul | 185 ; CHECK: imul |
125 ; CHECK: mul | 186 ; CHECK: mul |
126 ; CHECK: add | 187 ; CHECK: add |
127 ; CHECK: add | 188 ; CHECK: add |
128 ; CHECK: ret | 189 ; CHECK: ret |
| 190 ; |
| 191 ; OPTM1: mul64BitSigned: |
| 192 ; OPTM1: imul |
| 193 ; OPTM1: imul |
| 194 ; OPTM1: mul |
| 195 ; OPTM1: add |
| 196 ; OPTM1: add |
| 197 ; OPTM1: ret |
129 | 198 |
130 define internal i64 @mul64BitUnsigned(i64 %a, i64 %b) { | 199 define internal i64 @mul64BitUnsigned(i64 %a, i64 %b) { |
131 entry: | 200 entry: |
132 %mul = mul i64 %b, %a | 201 %mul = mul i64 %b, %a |
133 ret i64 %mul | 202 ret i64 %mul |
134 } | 203 } |
135 ; CHECK: mul64BitUnsigned: | 204 ; CHECK: mul64BitUnsigned: |
136 ; CHECK: imul | 205 ; CHECK: imul |
137 ; CHECK: imul | 206 ; CHECK: imul |
138 ; CHECK: mul | 207 ; CHECK: mul |
139 ; CHECK: add | 208 ; CHECK: add |
140 ; CHECK: add | 209 ; CHECK: add |
141 ; CHECK: ret | 210 ; CHECK: ret |
| 211 ; |
| 212 ; OPTM1: mul64BitUnsigned: |
| 213 ; OPTM1: imul |
| 214 ; OPTM1: imul |
| 215 ; OPTM1: mul |
| 216 ; OPTM1: add |
| 217 ; OPTM1: add |
| 218 ; OPTM1: ret |
142 | 219 |
143 define internal i64 @div64BitSigned(i64 %a, i64 %b) { | 220 define internal i64 @div64BitSigned(i64 %a, i64 %b) { |
144 entry: | 221 entry: |
145 %div = sdiv i64 %a, %b | 222 %div = sdiv i64 %a, %b |
146 ret i64 %div | 223 ret i64 %div |
147 } | 224 } |
148 ; CHECK: div64BitSigned: | 225 ; CHECK: div64BitSigned: |
149 ; CHECK: call __divdi3 | 226 ; CHECK: call __divdi3 |
150 ; CHECK: ret | 227 ; CHECK: ret |
| 228 ; |
| 229 ; OPTM1: div64BitSigned: |
| 230 ; OPTM1: call __divdi3 |
| 231 ; OPTM1: ret |
151 | 232 |
152 define internal i64 @div64BitUnsigned(i64 %a, i64 %b) { | 233 define internal i64 @div64BitUnsigned(i64 %a, i64 %b) { |
153 entry: | 234 entry: |
154 %div = udiv i64 %a, %b | 235 %div = udiv i64 %a, %b |
155 ret i64 %div | 236 ret i64 %div |
156 } | 237 } |
157 ; CHECK: div64BitUnsigned: | 238 ; CHECK: div64BitUnsigned: |
158 ; CHECK: call __udivdi3 | 239 ; CHECK: call __udivdi3 |
159 ; CHECK: ret | 240 ; CHECK: ret |
| 241 ; |
| 242 ; OPTM1: div64BitUnsigned: |
| 243 ; OPTM1: call __udivdi3 |
| 244 ; OPTM1: ret |
160 | 245 |
161 define internal i64 @rem64BitSigned(i64 %a, i64 %b) { | 246 define internal i64 @rem64BitSigned(i64 %a, i64 %b) { |
162 entry: | 247 entry: |
163 %rem = srem i64 %a, %b | 248 %rem = srem i64 %a, %b |
164 ret i64 %rem | 249 ret i64 %rem |
165 } | 250 } |
166 ; CHECK: rem64BitSigned: | 251 ; CHECK: rem64BitSigned: |
167 ; CHECK: call __moddi3 | 252 ; CHECK: call __moddi3 |
168 ; CHECK: ret | 253 ; CHECK: ret |
| 254 ; |
| 255 ; OPTM1: rem64BitSigned: |
| 256 ; OPTM1: call __moddi3 |
| 257 ; OPTM1: ret |
169 | 258 |
170 define internal i64 @rem64BitUnsigned(i64 %a, i64 %b) { | 259 define internal i64 @rem64BitUnsigned(i64 %a, i64 %b) { |
171 entry: | 260 entry: |
172 %rem = urem i64 %a, %b | 261 %rem = urem i64 %a, %b |
173 ret i64 %rem | 262 ret i64 %rem |
174 } | 263 } |
175 ; CHECK: rem64BitUnsigned: | 264 ; CHECK: rem64BitUnsigned: |
176 ; CHECK: call __umoddi3 | 265 ; CHECK: call __umoddi3 |
177 ; CHECK: ret | 266 ; CHECK: ret |
| 267 ; |
| 268 ; OPTM1: rem64BitUnsigned: |
| 269 ; OPTM1: call __umoddi3 |
| 270 ; OPTM1: ret |
178 | 271 |
179 define internal i64 @shl64BitSigned(i64 %a, i64 %b) { | 272 define internal i64 @shl64BitSigned(i64 %a, i64 %b) { |
180 entry: | 273 entry: |
181 %shl = shl i64 %a, %b | 274 %shl = shl i64 %a, %b |
182 ret i64 %shl | 275 ret i64 %shl |
183 } | 276 } |
184 ; CHECK: shl64BitSigned: | 277 ; CHECK: shl64BitSigned: |
185 ; CHECK: shld | 278 ; CHECK: shld |
186 ; CHECK: shl e | 279 ; CHECK: shl e |
187 ; CHECK: test {{.*}}, 32 | 280 ; CHECK: test {{.*}}, 32 |
188 ; CHECK: je | 281 ; CHECK: je |
| 282 ; |
| 283 ; OPTM1: shl64BitSigned: |
| 284 ; OPTM1: shld |
| 285 ; OPTM1: shl e |
| 286 ; OPTM1: test {{.*}}, 32 |
| 287 ; OPTM1: je |
189 | 288 |
190 define internal i64 @shl64BitUnsigned(i64 %a, i64 %b) { | 289 define internal i64 @shl64BitUnsigned(i64 %a, i64 %b) { |
191 entry: | 290 entry: |
192 %shl = shl i64 %a, %b | 291 %shl = shl i64 %a, %b |
193 ret i64 %shl | 292 ret i64 %shl |
194 } | 293 } |
195 ; CHECK: shl64BitUnsigned: | 294 ; CHECK: shl64BitUnsigned: |
196 ; CHECK: shld | 295 ; CHECK: shld |
197 ; CHECK: shl e | 296 ; CHECK: shl e |
198 ; CHECK: test {{.*}}, 32 | 297 ; CHECK: test {{.*}}, 32 |
199 ; CHECK: je | 298 ; CHECK: je |
| 299 ; |
| 300 ; OPTM1: shl64BitUnsigned: |
| 301 ; OPTM1: shld |
| 302 ; OPTM1: shl e |
| 303 ; OPTM1: test {{.*}}, 32 |
| 304 ; OPTM1: je |
200 | 305 |
201 define internal i64 @shr64BitSigned(i64 %a, i64 %b) { | 306 define internal i64 @shr64BitSigned(i64 %a, i64 %b) { |
202 entry: | 307 entry: |
203 %shr = ashr i64 %a, %b | 308 %shr = ashr i64 %a, %b |
204 ret i64 %shr | 309 ret i64 %shr |
205 } | 310 } |
206 ; CHECK: shr64BitSigned: | 311 ; CHECK: shr64BitSigned: |
207 ; CHECK: shrd | 312 ; CHECK: shrd |
208 ; CHECK: sar | 313 ; CHECK: sar |
209 ; CHECK: test {{.*}}, 32 | 314 ; CHECK: test {{.*}}, 32 |
210 ; CHECK: je | 315 ; CHECK: je |
211 ; CHECK: sar {{.*}}, 31 | 316 ; CHECK: sar {{.*}}, 31 |
| 317 ; |
| 318 ; OPTM1: shr64BitSigned: |
| 319 ; OPTM1: shrd |
| 320 ; OPTM1: sar |
| 321 ; OPTM1: test {{.*}}, 32 |
| 322 ; OPTM1: je |
| 323 ; OPTM1: sar {{.*}}, 31 |
212 | 324 |
213 define internal i64 @shr64BitUnsigned(i64 %a, i64 %b) { | 325 define internal i64 @shr64BitUnsigned(i64 %a, i64 %b) { |
214 entry: | 326 entry: |
215 %shr = lshr i64 %a, %b | 327 %shr = lshr i64 %a, %b |
216 ret i64 %shr | 328 ret i64 %shr |
217 } | 329 } |
218 ; CHECK: shr64BitUnsigned: | 330 ; CHECK: shr64BitUnsigned: |
219 ; CHECK: shrd | 331 ; CHECK: shrd |
220 ; CHECK: shr | 332 ; CHECK: shr |
221 ; CHECK: test {{.*}}, 32 | 333 ; CHECK: test {{.*}}, 32 |
222 ; CHECK: je | 334 ; CHECK: je |
| 335 ; |
| 336 ; OPTM1: shr64BitUnsigned: |
| 337 ; OPTM1: shrd |
| 338 ; OPTM1: shr |
| 339 ; OPTM1: test {{.*}}, 32 |
| 340 ; OPTM1: je |
223 | 341 |
224 define internal i64 @and64BitSigned(i64 %a, i64 %b) { | 342 define internal i64 @and64BitSigned(i64 %a, i64 %b) { |
225 entry: | 343 entry: |
226 %and = and i64 %b, %a | 344 %and = and i64 %b, %a |
227 ret i64 %and | 345 ret i64 %and |
228 } | 346 } |
229 ; CHECK: and64BitSigned: | 347 ; CHECK: and64BitSigned: |
230 ; CHECK: and | 348 ; CHECK: and |
231 ; CHECK: and | 349 ; CHECK: and |
| 350 ; |
| 351 ; OPTM1: and64BitSigned: |
| 352 ; OPTM1: and |
| 353 ; OPTM1: and |
232 | 354 |
233 define internal i64 @and64BitUnsigned(i64 %a, i64 %b) { | 355 define internal i64 @and64BitUnsigned(i64 %a, i64 %b) { |
234 entry: | 356 entry: |
235 %and = and i64 %b, %a | 357 %and = and i64 %b, %a |
236 ret i64 %and | 358 ret i64 %and |
237 } | 359 } |
238 ; CHECK: and64BitUnsigned: | 360 ; CHECK: and64BitUnsigned: |
239 ; CHECK: and | 361 ; CHECK: and |
240 ; CHECK: and | 362 ; CHECK: and |
| 363 ; |
| 364 ; OPTM1: and64BitUnsigned: |
| 365 ; OPTM1: and |
| 366 ; OPTM1: and |
241 | 367 |
242 define internal i64 @or64BitSigned(i64 %a, i64 %b) { | 368 define internal i64 @or64BitSigned(i64 %a, i64 %b) { |
243 entry: | 369 entry: |
244 %or = or i64 %b, %a | 370 %or = or i64 %b, %a |
245 ret i64 %or | 371 ret i64 %or |
246 } | 372 } |
247 ; CHECK: or64BitSigned: | 373 ; CHECK: or64BitSigned: |
248 ; CHECK: or | 374 ; CHECK: or |
249 ; CHECK: or | 375 ; CHECK: or |
| 376 ; |
| 377 ; OPTM1: or64BitSigned: |
| 378 ; OPTM1: or |
| 379 ; OPTM1: or |
250 | 380 |
251 define internal i64 @or64BitUnsigned(i64 %a, i64 %b) { | 381 define internal i64 @or64BitUnsigned(i64 %a, i64 %b) { |
252 entry: | 382 entry: |
253 %or = or i64 %b, %a | 383 %or = or i64 %b, %a |
254 ret i64 %or | 384 ret i64 %or |
255 } | 385 } |
256 ; CHECK: or64BitUnsigned: | 386 ; CHECK: or64BitUnsigned: |
257 ; CHECK: or | 387 ; CHECK: or |
258 ; CHECK: or | 388 ; CHECK: or |
| 389 ; |
| 390 ; OPTM1: or64BitUnsigned: |
| 391 ; OPTM1: or |
| 392 ; OPTM1: or |
259 | 393 |
260 define internal i64 @xor64BitSigned(i64 %a, i64 %b) { | 394 define internal i64 @xor64BitSigned(i64 %a, i64 %b) { |
261 entry: | 395 entry: |
262 %xor = xor i64 %b, %a | 396 %xor = xor i64 %b, %a |
263 ret i64 %xor | 397 ret i64 %xor |
264 } | 398 } |
265 ; CHECK: xor64BitSigned: | 399 ; CHECK: xor64BitSigned: |
266 ; CHECK: xor | 400 ; CHECK: xor |
267 ; CHECK: xor | 401 ; CHECK: xor |
| 402 ; |
| 403 ; OPTM1: xor64BitSigned: |
| 404 ; OPTM1: xor |
| 405 ; OPTM1: xor |
268 | 406 |
269 define internal i64 @xor64BitUnsigned(i64 %a, i64 %b) { | 407 define internal i64 @xor64BitUnsigned(i64 %a, i64 %b) { |
270 entry: | 408 entry: |
271 %xor = xor i64 %b, %a | 409 %xor = xor i64 %b, %a |
272 ret i64 %xor | 410 ret i64 %xor |
273 } | 411 } |
274 ; CHECK: xor64BitUnsigned: | 412 ; CHECK: xor64BitUnsigned: |
275 ; CHECK: xor | 413 ; CHECK: xor |
276 ; CHECK: xor | 414 ; CHECK: xor |
| 415 ; |
| 416 ; OPTM1: xor64BitUnsigned: |
| 417 ; OPTM1: xor |
| 418 ; OPTM1: xor |
277 | 419 |
278 define internal i32 @trunc64To32Signed(i64 %a) { | 420 define internal i32 @trunc64To32Signed(i64 %a) { |
279 entry: | 421 entry: |
280 %conv = trunc i64 %a to i32 | 422 %conv = trunc i64 %a to i32 |
281 ret i32 %conv | 423 ret i32 %conv |
282 } | 424 } |
283 ; CHECK: trunc64To32Signed: | 425 ; CHECK: trunc64To32Signed: |
284 ; CHECK: mov eax, dword ptr [esp+4] | 426 ; CHECK: mov eax, dword ptr [esp+4] |
285 ; CHECK-NEXT: ret | 427 ; CHECK-NEXT: ret |
| 428 ; |
| 429 ; OPTM1: trunc64To32Signed: |
| 430 ; OPTM1: mov eax, dword ptr [esp+ |
| 431 ; OPTM1: ret |
286 | 432 |
287 define internal i32 @trunc64To16Signed(i64 %a) { | 433 define internal i32 @trunc64To16Signed(i64 %a) { |
288 entry: | 434 entry: |
289 %conv = trunc i64 %a to i16 | 435 %conv = trunc i64 %a to i16 |
290 %conv.ret_ext = sext i16 %conv to i32 | 436 %conv.ret_ext = sext i16 %conv to i32 |
291 ret i32 %conv.ret_ext | 437 ret i32 %conv.ret_ext |
292 } | 438 } |
293 ; CHECK: trunc64To16Signed: | 439 ; CHECK: trunc64To16Signed: |
294 ; CHECK: mov eax, dword ptr [esp+4] | 440 ; CHECK: mov eax, dword ptr [esp+4] |
295 ; CHECK-NEXT: movsx eax, ax | 441 ; CHECK-NEXT: movsx eax, ax |
296 ; CHECK-NEXT: ret | 442 ; CHECK-NEXT: ret |
| 443 ; |
| 444 ; OPTM1: trunc64To16Signed: |
| 445 ; OPTM1: mov eax, dword ptr [esp+ |
| 446 ; OPTM1: movsx eax, |
| 447 ; OPTM1: ret |
297 | 448 |
298 define internal i32 @trunc64To8Signed(i64 %a) { | 449 define internal i32 @trunc64To8Signed(i64 %a) { |
299 entry: | 450 entry: |
300 %conv = trunc i64 %a to i8 | 451 %conv = trunc i64 %a to i8 |
301 %conv.ret_ext = sext i8 %conv to i32 | 452 %conv.ret_ext = sext i8 %conv to i32 |
302 ret i32 %conv.ret_ext | 453 ret i32 %conv.ret_ext |
303 } | 454 } |
304 ; CHECK: trunc64To8Signed: | 455 ; CHECK: trunc64To8Signed: |
305 ; CHECK: mov eax, dword ptr [esp+4] | 456 ; CHECK: mov eax, dword ptr [esp+4] |
306 ; CHECK-NEXT: movsx eax, al | 457 ; CHECK-NEXT: movsx eax, al |
307 ; CHECK-NEXT: ret | 458 ; CHECK-NEXT: ret |
| 459 ; |
| 460 ; OPTM1: trunc64To8Signed: |
| 461 ; OPTM1: mov eax, dword ptr [esp+ |
| 462 ; OPTM1: movsx eax, |
| 463 ; OPTM1: ret |
308 | 464 |
309 define internal i32 @trunc64To32Unsigned(i64 %a) { | 465 define internal i32 @trunc64To32Unsigned(i64 %a) { |
310 entry: | 466 entry: |
311 %conv = trunc i64 %a to i32 | 467 %conv = trunc i64 %a to i32 |
312 ret i32 %conv | 468 ret i32 %conv |
313 } | 469 } |
314 ; CHECK: trunc64To32Unsigned: | 470 ; CHECK: trunc64To32Unsigned: |
315 ; CHECK: mov eax, dword ptr [esp+4] | 471 ; CHECK: mov eax, dword ptr [esp+4] |
316 ; CHECK-NEXT: ret | 472 ; CHECK-NEXT: ret |
| 473 ; |
| 474 ; OPTM1: trunc64To32Unsigned: |
| 475 ; OPTM1: mov eax, dword ptr [esp+ |
| 476 ; OPTM1: ret |
317 | 477 |
318 define internal i32 @trunc64To16Unsigned(i64 %a) { | 478 define internal i32 @trunc64To16Unsigned(i64 %a) { |
319 entry: | 479 entry: |
320 %conv = trunc i64 %a to i16 | 480 %conv = trunc i64 %a to i16 |
321 %conv.ret_ext = zext i16 %conv to i32 | 481 %conv.ret_ext = zext i16 %conv to i32 |
322 ret i32 %conv.ret_ext | 482 ret i32 %conv.ret_ext |
323 } | 483 } |
324 ; CHECK: trunc64To16Unsigned: | 484 ; CHECK: trunc64To16Unsigned: |
325 ; CHECK: mov eax, dword ptr [esp+4] | 485 ; CHECK: mov eax, dword ptr [esp+4] |
326 ; CHECK-NEXT: movzx eax, ax | 486 ; CHECK-NEXT: movzx eax, ax |
327 ; CHECK-NEXT: ret | 487 ; CHECK-NEXT: ret |
| 488 ; |
| 489 ; OPTM1: trunc64To16Unsigned: |
| 490 ; OPTM1: mov eax, dword ptr [esp+ |
| 491 ; OPTM1: movzx eax, |
| 492 ; OPTM1: ret |
328 | 493 |
329 define internal i32 @trunc64To8Unsigned(i64 %a) { | 494 define internal i32 @trunc64To8Unsigned(i64 %a) { |
330 entry: | 495 entry: |
331 %conv = trunc i64 %a to i8 | 496 %conv = trunc i64 %a to i8 |
332 %conv.ret_ext = zext i8 %conv to i32 | 497 %conv.ret_ext = zext i8 %conv to i32 |
333 ret i32 %conv.ret_ext | 498 ret i32 %conv.ret_ext |
334 } | 499 } |
335 ; CHECK: trunc64To8Unsigned: | 500 ; CHECK: trunc64To8Unsigned: |
336 ; CHECK: mov eax, dword ptr [esp+4] | 501 ; CHECK: mov eax, dword ptr [esp+4] |
337 ; CHECK-NEXT: movzx eax, al | 502 ; CHECK-NEXT: movzx eax, al |
338 ; CHECK-NEXT: ret | 503 ; CHECK-NEXT: ret |
| 504 ; |
| 505 ; OPTM1: trunc64To8Unsigned: |
| 506 ; OPTM1: mov eax, dword ptr [esp+ |
| 507 ; OPTM1: movzx eax, |
| 508 ; OPTM1: ret |
339 | 509 |
340 define internal i32 @trunc64To1(i64 %a) { | 510 define internal i32 @trunc64To1(i64 %a) { |
341 entry: | 511 entry: |
342 ; %tobool = icmp ne i64 %a, 0 | 512 ; %tobool = icmp ne i64 %a, 0 |
343 %tobool = trunc i64 %a to i1 | 513 %tobool = trunc i64 %a to i1 |
344 %tobool.ret_ext = zext i1 %tobool to i32 | 514 %tobool.ret_ext = zext i1 %tobool to i32 |
345 ret i32 %tobool.ret_ext | 515 ret i32 %tobool.ret_ext |
346 } | 516 } |
347 ; CHECK: trunc64To1: | 517 ; CHECK: trunc64To1: |
348 ; CHECK: mov eax, dword ptr [esp+4] | 518 ; CHECK: mov eax, dword ptr [esp+4] |
349 ; CHECK: and eax, 1 | 519 ; CHECK: and eax, 1 |
350 ; CHECK-NEXT: ret | 520 ; CHECK-NEXT: ret |
| 521 ; |
| 522 ; OPTM1: trunc64To1: |
| 523 ; OPTM1: mov eax, dword ptr [esp+ |
| 524 ; OPTM1: and eax, 1 |
| 525 ; OPTM1: ret |
351 | 526 |
352 define internal i64 @sext32To64(i32 %a) { | 527 define internal i64 @sext32To64(i32 %a) { |
353 entry: | 528 entry: |
354 %conv = sext i32 %a to i64 | 529 %conv = sext i32 %a to i64 |
355 ret i64 %conv | 530 ret i64 %conv |
356 } | 531 } |
357 ; CHECK: sext32To64: | 532 ; CHECK: sext32To64: |
358 ; CHECK: mov | 533 ; CHECK: mov |
359 ; CHECK: sar {{.*}}, 31 | 534 ; CHECK: sar {{.*}}, 31 |
| 535 ; |
| 536 ; OPTM1: sext32To64: |
| 537 ; OPTM1: mov |
| 538 ; OPTM1: sar {{.*}}, 31 |
360 | 539 |
361 define internal i64 @sext16To64(i32 %a) { | 540 define internal i64 @sext16To64(i32 %a) { |
362 entry: | 541 entry: |
363 %a.arg_trunc = trunc i32 %a to i16 | 542 %a.arg_trunc = trunc i32 %a to i16 |
364 %conv = sext i16 %a.arg_trunc to i64 | 543 %conv = sext i16 %a.arg_trunc to i64 |
365 ret i64 %conv | 544 ret i64 %conv |
366 } | 545 } |
367 ; CHECK: sext16To64: | 546 ; CHECK: sext16To64: |
368 ; CHECK: movsx | 547 ; CHECK: movsx |
369 ; CHECK: sar {{.*}}, 31 | 548 ; CHECK: sar {{.*}}, 31 |
| 549 ; |
| 550 ; OPTM1: sext16To64: |
| 551 ; OPTM1: movsx |
| 552 ; OPTM1: sar {{.*}}, 31 |
370 | 553 |
371 define internal i64 @sext8To64(i32 %a) { | 554 define internal i64 @sext8To64(i32 %a) { |
372 entry: | 555 entry: |
373 %a.arg_trunc = trunc i32 %a to i8 | 556 %a.arg_trunc = trunc i32 %a to i8 |
374 %conv = sext i8 %a.arg_trunc to i64 | 557 %conv = sext i8 %a.arg_trunc to i64 |
375 ret i64 %conv | 558 ret i64 %conv |
376 } | 559 } |
377 ; CHECK: sext8To64: | 560 ; CHECK: sext8To64: |
378 ; CHECK: movsx | 561 ; CHECK: movsx |
379 ; CHECK: sar {{.*}}, 31 | 562 ; CHECK: sar {{.*}}, 31 |
| 563 ; |
| 564 ; OPTM1: sext8To64: |
| 565 ; OPTM1: movsx |
| 566 ; OPTM1: sar {{.*}}, 31 |
380 | 567 |
381 define internal i64 @zext32To64(i32 %a) { | 568 define internal i64 @zext32To64(i32 %a) { |
382 entry: | 569 entry: |
383 %conv = zext i32 %a to i64 | 570 %conv = zext i32 %a to i64 |
384 ret i64 %conv | 571 ret i64 %conv |
385 } | 572 } |
386 ; CHECK: zext32To64: | 573 ; CHECK: zext32To64: |
387 ; CHECK: mov | 574 ; CHECK: mov |
388 ; CHECK: mov {{.*}}, 0 | 575 ; CHECK: mov {{.*}}, 0 |
| 576 ; |
| 577 ; OPTM1: zext32To64: |
| 578 ; OPTM1: mov |
| 579 ; OPTM1: mov {{.*}}, 0 |
389 | 580 |
390 define internal i64 @zext16To64(i32 %a) { | 581 define internal i64 @zext16To64(i32 %a) { |
391 entry: | 582 entry: |
392 %a.arg_trunc = trunc i32 %a to i16 | 583 %a.arg_trunc = trunc i32 %a to i16 |
393 %conv = zext i16 %a.arg_trunc to i64 | 584 %conv = zext i16 %a.arg_trunc to i64 |
394 ret i64 %conv | 585 ret i64 %conv |
395 } | 586 } |
396 ; CHECK: zext16To64: | 587 ; CHECK: zext16To64: |
397 ; CHECK: movzx | 588 ; CHECK: movzx |
398 ; CHECK: mov {{.*}}, 0 | 589 ; CHECK: mov {{.*}}, 0 |
| 590 ; |
| 591 ; OPTM1: zext16To64: |
| 592 ; OPTM1: movzx |
| 593 ; OPTM1: mov {{.*}}, 0 |
399 | 594 |
400 define internal i64 @zext8To64(i32 %a) { | 595 define internal i64 @zext8To64(i32 %a) { |
401 entry: | 596 entry: |
402 %a.arg_trunc = trunc i32 %a to i8 | 597 %a.arg_trunc = trunc i32 %a to i8 |
403 %conv = zext i8 %a.arg_trunc to i64 | 598 %conv = zext i8 %a.arg_trunc to i64 |
404 ret i64 %conv | 599 ret i64 %conv |
405 } | 600 } |
406 ; CHECK: zext8To64: | 601 ; CHECK: zext8To64: |
407 ; CHECK: movzx | 602 ; CHECK: movzx |
408 ; CHECK: mov {{.*}}, 0 | 603 ; CHECK: mov {{.*}}, 0 |
| 604 ; |
| 605 ; OPTM1: zext8To64: |
| 606 ; OPTM1: movzx |
| 607 ; OPTM1: mov {{.*}}, 0 |
409 | 608 |
410 define internal i64 @zext1To64(i32 %a) { | 609 define internal i64 @zext1To64(i32 %a) { |
411 entry: | 610 entry: |
412 %a.arg_trunc = trunc i32 %a to i1 | 611 %a.arg_trunc = trunc i32 %a to i1 |
413 %conv = zext i1 %a.arg_trunc to i64 | 612 %conv = zext i1 %a.arg_trunc to i64 |
414 ret i64 %conv | 613 ret i64 %conv |
415 } | 614 } |
416 ; CHECK: zext1To64: | 615 ; CHECK: zext1To64: |
417 ; CHECK: movzx | 616 ; CHECK: movzx |
418 ; CHECK: mov {{.*}}, 0 | 617 ; CHECK: mov {{.*}}, 0 |
| 618 ; |
| 619 ; OPTM1: zext1To64: |
| 620 ; OPTM1: movzx |
| 621 ; OPTM1: mov {{.*}}, 0 |
419 | 622 |
420 define internal void @icmpEq64(i64 %a, i64 %b, i64 %c, i64 %d) { | 623 define internal void @icmpEq64(i64 %a, i64 %b, i64 %c, i64 %d) { |
421 entry: | 624 entry: |
422 %cmp = icmp eq i64 %a, %b | 625 %cmp = icmp eq i64 %a, %b |
423 br i1 %cmp, label %if.then, label %if.end | 626 br i1 %cmp, label %if.then, label %if.end |
424 | 627 |
425 if.then: ; preds = %entry | 628 if.then: ; preds = %entry |
426 call void @func() | 629 call void @func() |
427 br label %if.end | 630 br label %if.end |
428 | 631 |
429 if.end: ; preds = %if.then, %entry | 632 if.end: ; preds = %if.then, %entry |
430 %cmp1 = icmp eq i64 %c, %d | 633 %cmp1 = icmp eq i64 %c, %d |
431 br i1 %cmp1, label %if.then2, label %if.end3 | 634 br i1 %cmp1, label %if.then2, label %if.end3 |
432 | 635 |
433 if.then2: ; preds = %if.end | 636 if.then2: ; preds = %if.end |
434 call void @func() | 637 call void @func() |
435 br label %if.end3 | 638 br label %if.end3 |
436 | 639 |
437 if.end3: ; preds = %if.then2, %if.end | 640 if.end3: ; preds = %if.then2, %if.end |
438 ret void | 641 ret void |
439 } | 642 } |
440 ; CHECK: icmpEq64: | 643 ; CHECK: icmpEq64: |
441 ; CHECK: jne | 644 ; CHECK: jne |
442 ; CHECK: jne | 645 ; CHECK: jne |
443 ; CHECK: call | 646 ; CHECK: call |
444 ; CHECK: jne | 647 ; CHECK: jne |
445 ; CHECK: jne | 648 ; CHECK: jne |
446 ; CHECK: call | 649 ; CHECK: call |
| 650 ; |
| 651 ; OPTM1: icmpEq64: |
| 652 ; OPTM1: jne |
| 653 ; OPTM1: jne |
| 654 ; OPTM1: call |
| 655 ; OPTM1: jne |
| 656 ; OPTM1: jne |
| 657 ; OPTM1: call |
447 | 658 |
448 declare void @func() | 659 declare void @func() |
449 | 660 |
450 define internal void @icmpNe64(i64 %a, i64 %b, i64 %c, i64 %d) { | 661 define internal void @icmpNe64(i64 %a, i64 %b, i64 %c, i64 %d) { |
451 entry: | 662 entry: |
452 %cmp = icmp ne i64 %a, %b | 663 %cmp = icmp ne i64 %a, %b |
453 br i1 %cmp, label %if.then, label %if.end | 664 br i1 %cmp, label %if.then, label %if.end |
454 | 665 |
455 if.then: ; preds = %entry | 666 if.then: ; preds = %entry |
456 call void @func() | 667 call void @func() |
(...skipping 10 matching lines...) Expand all Loading... |
467 if.end3: ; preds = %if.end, %if.then2 | 678 if.end3: ; preds = %if.end, %if.then2 |
468 ret void | 679 ret void |
469 } | 680 } |
470 ; CHECK: icmpNe64: | 681 ; CHECK: icmpNe64: |
471 ; CHECK: jne | 682 ; CHECK: jne |
472 ; CHECK: jne | 683 ; CHECK: jne |
473 ; CHECK: call | 684 ; CHECK: call |
474 ; CHECK: jne | 685 ; CHECK: jne |
475 ; CHECK: jne | 686 ; CHECK: jne |
476 ; CHECK: call | 687 ; CHECK: call |
| 688 ; |
| 689 ; OPTM1: icmpNe64: |
| 690 ; OPTM1: jne |
| 691 ; OPTM1: jne |
| 692 ; OPTM1: call |
| 693 ; OPTM1: jne |
| 694 ; OPTM1: jne |
| 695 ; OPTM1: call |
477 | 696 |
478 define internal void @icmpGt64(i64 %a, i64 %b, i64 %c, i64 %d) { | 697 define internal void @icmpGt64(i64 %a, i64 %b, i64 %c, i64 %d) { |
479 entry: | 698 entry: |
480 %cmp = icmp ugt i64 %a, %b | 699 %cmp = icmp ugt i64 %a, %b |
481 br i1 %cmp, label %if.then, label %if.end | 700 br i1 %cmp, label %if.then, label %if.end |
482 | 701 |
483 if.then: ; preds = %entry | 702 if.then: ; preds = %entry |
484 call void @func() | 703 call void @func() |
485 br label %if.end | 704 br label %if.end |
486 | 705 |
(...skipping 10 matching lines...) Expand all Loading... |
497 } | 716 } |
498 ; CHECK: icmpGt64: | 717 ; CHECK: icmpGt64: |
499 ; CHECK: ja | 718 ; CHECK: ja |
500 ; CHECK: jb | 719 ; CHECK: jb |
501 ; CHECK: ja | 720 ; CHECK: ja |
502 ; CHECK: call | 721 ; CHECK: call |
503 ; CHECK: jg | 722 ; CHECK: jg |
504 ; CHECK: jl | 723 ; CHECK: jl |
505 ; CHECK: ja | 724 ; CHECK: ja |
506 ; CHECK: call | 725 ; CHECK: call |
| 726 ; |
| 727 ; OPTM1: icmpGt64: |
| 728 ; OPTM1: ja |
| 729 ; OPTM1: jb |
| 730 ; OPTM1: ja |
| 731 ; OPTM1: call |
| 732 ; OPTM1: jg |
| 733 ; OPTM1: jl |
| 734 ; OPTM1: ja |
| 735 ; OPTM1: call |
507 | 736 |
508 define internal void @icmpGe64(i64 %a, i64 %b, i64 %c, i64 %d) { | 737 define internal void @icmpGe64(i64 %a, i64 %b, i64 %c, i64 %d) { |
509 entry: | 738 entry: |
510 %cmp = icmp uge i64 %a, %b | 739 %cmp = icmp uge i64 %a, %b |
511 br i1 %cmp, label %if.then, label %if.end | 740 br i1 %cmp, label %if.then, label %if.end |
512 | 741 |
513 if.then: ; preds = %entry | 742 if.then: ; preds = %entry |
514 call void @func() | 743 call void @func() |
515 br label %if.end | 744 br label %if.end |
516 | 745 |
(...skipping 10 matching lines...) Expand all Loading... |
527 } | 756 } |
528 ; CHECK: icmpGe64: | 757 ; CHECK: icmpGe64: |
529 ; CHECK: ja | 758 ; CHECK: ja |
530 ; CHECK: jb | 759 ; CHECK: jb |
531 ; CHECK: jae | 760 ; CHECK: jae |
532 ; CHECK: call | 761 ; CHECK: call |
533 ; CHECK: jg | 762 ; CHECK: jg |
534 ; CHECK: jl | 763 ; CHECK: jl |
535 ; CHECK: jae | 764 ; CHECK: jae |
536 ; CHECK: call | 765 ; CHECK: call |
| 766 ; |
| 767 ; OPTM1: icmpGe64: |
| 768 ; OPTM1: ja |
| 769 ; OPTM1: jb |
| 770 ; OPTM1: jae |
| 771 ; OPTM1: call |
| 772 ; OPTM1: jg |
| 773 ; OPTM1: jl |
| 774 ; OPTM1: jae |
| 775 ; OPTM1: call |
537 | 776 |
538 define internal void @icmpLt64(i64 %a, i64 %b, i64 %c, i64 %d) { | 777 define internal void @icmpLt64(i64 %a, i64 %b, i64 %c, i64 %d) { |
539 entry: | 778 entry: |
540 %cmp = icmp ult i64 %a, %b | 779 %cmp = icmp ult i64 %a, %b |
541 br i1 %cmp, label %if.then, label %if.end | 780 br i1 %cmp, label %if.then, label %if.end |
542 | 781 |
543 if.then: ; preds = %entry | 782 if.then: ; preds = %entry |
544 call void @func() | 783 call void @func() |
545 br label %if.end | 784 br label %if.end |
546 | 785 |
(...skipping 10 matching lines...) Expand all Loading... |
557 } | 796 } |
558 ; CHECK: icmpLt64: | 797 ; CHECK: icmpLt64: |
559 ; CHECK: jb | 798 ; CHECK: jb |
560 ; CHECK: ja | 799 ; CHECK: ja |
561 ; CHECK: jb | 800 ; CHECK: jb |
562 ; CHECK: call | 801 ; CHECK: call |
563 ; CHECK: jl | 802 ; CHECK: jl |
564 ; CHECK: jg | 803 ; CHECK: jg |
565 ; CHECK: jb | 804 ; CHECK: jb |
566 ; CHECK: call | 805 ; CHECK: call |
| 806 ; |
| 807 ; OPTM1: icmpLt64: |
| 808 ; OPTM1: jb |
| 809 ; OPTM1: ja |
| 810 ; OPTM1: jb |
| 811 ; OPTM1: call |
| 812 ; OPTM1: jl |
| 813 ; OPTM1: jg |
| 814 ; OPTM1: jb |
| 815 ; OPTM1: call |
567 | 816 |
568 define internal void @icmpLe64(i64 %a, i64 %b, i64 %c, i64 %d) { | 817 define internal void @icmpLe64(i64 %a, i64 %b, i64 %c, i64 %d) { |
569 entry: | 818 entry: |
570 %cmp = icmp ule i64 %a, %b | 819 %cmp = icmp ule i64 %a, %b |
571 br i1 %cmp, label %if.then, label %if.end | 820 br i1 %cmp, label %if.then, label %if.end |
572 | 821 |
573 if.then: ; preds = %entry | 822 if.then: ; preds = %entry |
574 call void @func() | 823 call void @func() |
575 br label %if.end | 824 br label %if.end |
576 | 825 |
(...skipping 10 matching lines...) Expand all Loading... |
587 } | 836 } |
588 ; CHECK: icmpLe64: | 837 ; CHECK: icmpLe64: |
589 ; CHECK: jb | 838 ; CHECK: jb |
590 ; CHECK: ja | 839 ; CHECK: ja |
591 ; CHECK: jbe | 840 ; CHECK: jbe |
592 ; CHECK: call | 841 ; CHECK: call |
593 ; CHECK: jl | 842 ; CHECK: jl |
594 ; CHECK: jg | 843 ; CHECK: jg |
595 ; CHECK: jbe | 844 ; CHECK: jbe |
596 ; CHECK: call | 845 ; CHECK: call |
| 846 ; |
| 847 ; OPTM1: icmpLe64: |
| 848 ; OPTM1: jb |
| 849 ; OPTM1: ja |
| 850 ; OPTM1: jbe |
| 851 ; OPTM1: call |
| 852 ; OPTM1: jl |
| 853 ; OPTM1: jg |
| 854 ; OPTM1: jbe |
| 855 ; OPTM1: call |
597 | 856 |
598 define internal i32 @icmpEq64Bool(i64 %a, i64 %b) { | 857 define internal i32 @icmpEq64Bool(i64 %a, i64 %b) { |
599 entry: | 858 entry: |
600 %cmp = icmp eq i64 %a, %b | 859 %cmp = icmp eq i64 %a, %b |
601 %cmp.ret_ext = zext i1 %cmp to i32 | 860 %cmp.ret_ext = zext i1 %cmp to i32 |
602 ret i32 %cmp.ret_ext | 861 ret i32 %cmp.ret_ext |
603 } | 862 } |
604 ; CHECK: icmpEq64Bool: | 863 ; CHECK: icmpEq64Bool: |
605 ; CHECK: jne | 864 ; CHECK: jne |
606 ; CHECK: jne | 865 ; CHECK: jne |
| 866 ; |
| 867 ; OPTM1: icmpEq64Bool: |
| 868 ; OPTM1: jne |
| 869 ; OPTM1: jne |
607 | 870 |
608 define internal i32 @icmpNe64Bool(i64 %a, i64 %b) { | 871 define internal i32 @icmpNe64Bool(i64 %a, i64 %b) { |
609 entry: | 872 entry: |
610 %cmp = icmp ne i64 %a, %b | 873 %cmp = icmp ne i64 %a, %b |
611 %cmp.ret_ext = zext i1 %cmp to i32 | 874 %cmp.ret_ext = zext i1 %cmp to i32 |
612 ret i32 %cmp.ret_ext | 875 ret i32 %cmp.ret_ext |
613 } | 876 } |
614 ; CHECK: icmpNe64Bool: | 877 ; CHECK: icmpNe64Bool: |
615 ; CHECK: jne | 878 ; CHECK: jne |
616 ; CHECK: jne | 879 ; CHECK: jne |
| 880 ; |
| 881 ; OPTM1: icmpNe64Bool: |
| 882 ; OPTM1: jne |
| 883 ; OPTM1: jne |
617 | 884 |
618 define internal i32 @icmpSgt64Bool(i64 %a, i64 %b) { | 885 define internal i32 @icmpSgt64Bool(i64 %a, i64 %b) { |
619 entry: | 886 entry: |
620 %cmp = icmp sgt i64 %a, %b | 887 %cmp = icmp sgt i64 %a, %b |
621 %cmp.ret_ext = zext i1 %cmp to i32 | 888 %cmp.ret_ext = zext i1 %cmp to i32 |
622 ret i32 %cmp.ret_ext | 889 ret i32 %cmp.ret_ext |
623 } | 890 } |
624 ; CHECK: icmpSgt64Bool: | 891 ; CHECK: icmpSgt64Bool: |
625 ; CHECK: cmp | 892 ; CHECK: cmp |
626 ; CHECK: jg | 893 ; CHECK: jg |
627 ; CHECK: jl | 894 ; CHECK: jl |
628 ; CHECK: cmp | 895 ; CHECK: cmp |
629 ; CHECK: ja | 896 ; CHECK: ja |
| 897 ; |
| 898 ; OPTM1: icmpSgt64Bool: |
| 899 ; OPTM1: cmp |
| 900 ; OPTM1: jg |
| 901 ; OPTM1: jl |
| 902 ; OPTM1: cmp |
| 903 ; OPTM1: ja |
630 | 904 |
631 define internal i32 @icmpUgt64Bool(i64 %a, i64 %b) { | 905 define internal i32 @icmpUgt64Bool(i64 %a, i64 %b) { |
632 entry: | 906 entry: |
633 %cmp = icmp ugt i64 %a, %b | 907 %cmp = icmp ugt i64 %a, %b |
634 %cmp.ret_ext = zext i1 %cmp to i32 | 908 %cmp.ret_ext = zext i1 %cmp to i32 |
635 ret i32 %cmp.ret_ext | 909 ret i32 %cmp.ret_ext |
636 } | 910 } |
637 ; CHECK: icmpUgt64Bool: | 911 ; CHECK: icmpUgt64Bool: |
638 ; CHECK: cmp | 912 ; CHECK: cmp |
639 ; CHECK: ja | 913 ; CHECK: ja |
640 ; CHECK: jb | 914 ; CHECK: jb |
641 ; CHECK: cmp | 915 ; CHECK: cmp |
642 ; CHECK: ja | 916 ; CHECK: ja |
| 917 ; |
| 918 ; OPTM1: icmpUgt64Bool: |
| 919 ; OPTM1: cmp |
| 920 ; OPTM1: ja |
| 921 ; OPTM1: jb |
| 922 ; OPTM1: cmp |
| 923 ; OPTM1: ja |
643 | 924 |
644 define internal i32 @icmpSge64Bool(i64 %a, i64 %b) { | 925 define internal i32 @icmpSge64Bool(i64 %a, i64 %b) { |
645 entry: | 926 entry: |
646 %cmp = icmp sge i64 %a, %b | 927 %cmp = icmp sge i64 %a, %b |
647 %cmp.ret_ext = zext i1 %cmp to i32 | 928 %cmp.ret_ext = zext i1 %cmp to i32 |
648 ret i32 %cmp.ret_ext | 929 ret i32 %cmp.ret_ext |
649 } | 930 } |
650 ; CHECK: icmpSge64Bool: | 931 ; CHECK: icmpSge64Bool: |
651 ; CHECK: cmp | 932 ; CHECK: cmp |
652 ; CHECK: jg | 933 ; CHECK: jg |
653 ; CHECK: jl | 934 ; CHECK: jl |
654 ; CHECK: cmp | 935 ; CHECK: cmp |
655 ; CHECK: jae | 936 ; CHECK: jae |
| 937 ; |
| 938 ; OPTM1: icmpSge64Bool: |
| 939 ; OPTM1: cmp |
| 940 ; OPTM1: jg |
| 941 ; OPTM1: jl |
| 942 ; OPTM1: cmp |
| 943 ; OPTM1: jae |
656 | 944 |
657 define internal i32 @icmpUge64Bool(i64 %a, i64 %b) { | 945 define internal i32 @icmpUge64Bool(i64 %a, i64 %b) { |
658 entry: | 946 entry: |
659 %cmp = icmp uge i64 %a, %b | 947 %cmp = icmp uge i64 %a, %b |
660 %cmp.ret_ext = zext i1 %cmp to i32 | 948 %cmp.ret_ext = zext i1 %cmp to i32 |
661 ret i32 %cmp.ret_ext | 949 ret i32 %cmp.ret_ext |
662 } | 950 } |
663 ; CHECK: icmpUge64Bool: | 951 ; CHECK: icmpUge64Bool: |
664 ; CHECK: cmp | 952 ; CHECK: cmp |
665 ; CHECK: ja | 953 ; CHECK: ja |
666 ; CHECK: jb | 954 ; CHECK: jb |
667 ; CHECK: cmp | 955 ; CHECK: cmp |
668 ; CHECK: jae | 956 ; CHECK: jae |
| 957 ; |
| 958 ; OPTM1: icmpUge64Bool: |
| 959 ; OPTM1: cmp |
| 960 ; OPTM1: ja |
| 961 ; OPTM1: jb |
| 962 ; OPTM1: cmp |
| 963 ; OPTM1: jae |
669 | 964 |
670 define internal i32 @icmpSlt64Bool(i64 %a, i64 %b) { | 965 define internal i32 @icmpSlt64Bool(i64 %a, i64 %b) { |
671 entry: | 966 entry: |
672 %cmp = icmp slt i64 %a, %b | 967 %cmp = icmp slt i64 %a, %b |
673 %cmp.ret_ext = zext i1 %cmp to i32 | 968 %cmp.ret_ext = zext i1 %cmp to i32 |
674 ret i32 %cmp.ret_ext | 969 ret i32 %cmp.ret_ext |
675 } | 970 } |
676 ; CHECK: icmpSlt64Bool: | 971 ; CHECK: icmpSlt64Bool: |
677 ; CHECK: cmp | 972 ; CHECK: cmp |
678 ; CHECK: jl | 973 ; CHECK: jl |
679 ; CHECK: jg | 974 ; CHECK: jg |
680 ; CHECK: cmp | 975 ; CHECK: cmp |
681 ; CHECK: jb | 976 ; CHECK: jb |
| 977 ; |
| 978 ; OPTM1: icmpSlt64Bool: |
| 979 ; OPTM1: cmp |
| 980 ; OPTM1: jl |
| 981 ; OPTM1: jg |
| 982 ; OPTM1: cmp |
| 983 ; OPTM1: jb |
682 | 984 |
683 define internal i32 @icmpUlt64Bool(i64 %a, i64 %b) { | 985 define internal i32 @icmpUlt64Bool(i64 %a, i64 %b) { |
684 entry: | 986 entry: |
685 %cmp = icmp ult i64 %a, %b | 987 %cmp = icmp ult i64 %a, %b |
686 %cmp.ret_ext = zext i1 %cmp to i32 | 988 %cmp.ret_ext = zext i1 %cmp to i32 |
687 ret i32 %cmp.ret_ext | 989 ret i32 %cmp.ret_ext |
688 } | 990 } |
689 ; CHECK: icmpUlt64Bool: | 991 ; CHECK: icmpUlt64Bool: |
690 ; CHECK: cmp | 992 ; CHECK: cmp |
691 ; CHECK: jb | 993 ; CHECK: jb |
692 ; CHECK: ja | 994 ; CHECK: ja |
693 ; CHECK: cmp | 995 ; CHECK: cmp |
694 ; CHECK: jb | 996 ; CHECK: jb |
| 997 ; |
| 998 ; OPTM1: icmpUlt64Bool: |
| 999 ; OPTM1: cmp |
| 1000 ; OPTM1: jb |
| 1001 ; OPTM1: ja |
| 1002 ; OPTM1: cmp |
| 1003 ; OPTM1: jb |
695 | 1004 |
696 define internal i32 @icmpSle64Bool(i64 %a, i64 %b) { | 1005 define internal i32 @icmpSle64Bool(i64 %a, i64 %b) { |
697 entry: | 1006 entry: |
698 %cmp = icmp sle i64 %a, %b | 1007 %cmp = icmp sle i64 %a, %b |
699 %cmp.ret_ext = zext i1 %cmp to i32 | 1008 %cmp.ret_ext = zext i1 %cmp to i32 |
700 ret i32 %cmp.ret_ext | 1009 ret i32 %cmp.ret_ext |
701 } | 1010 } |
702 ; CHECK: icmpSle64Bool: | 1011 ; CHECK: icmpSle64Bool: |
703 ; CHECK: cmp | 1012 ; CHECK: cmp |
704 ; CHECK: jl | 1013 ; CHECK: jl |
705 ; CHECK: jg | 1014 ; CHECK: jg |
706 ; CHECK: cmp | 1015 ; CHECK: cmp |
707 ; CHECK: jbe | 1016 ; CHECK: jbe |
| 1017 ; |
| 1018 ; OPTM1: icmpSle64Bool: |
| 1019 ; OPTM1: cmp |
| 1020 ; OPTM1: jl |
| 1021 ; OPTM1: jg |
| 1022 ; OPTM1: cmp |
| 1023 ; OPTM1: jbe |
708 | 1024 |
709 define internal i32 @icmpUle64Bool(i64 %a, i64 %b) { | 1025 define internal i32 @icmpUle64Bool(i64 %a, i64 %b) { |
710 entry: | 1026 entry: |
711 %cmp = icmp ule i64 %a, %b | 1027 %cmp = icmp ule i64 %a, %b |
712 %cmp.ret_ext = zext i1 %cmp to i32 | 1028 %cmp.ret_ext = zext i1 %cmp to i32 |
713 ret i32 %cmp.ret_ext | 1029 ret i32 %cmp.ret_ext |
714 } | 1030 } |
715 ; CHECK: icmpUle64Bool: | 1031 ; CHECK: icmpUle64Bool: |
716 ; CHECK: cmp | 1032 ; CHECK: cmp |
717 ; CHECK: jb | 1033 ; CHECK: jb |
718 ; CHECK: ja | 1034 ; CHECK: ja |
719 ; CHECK: cmp | 1035 ; CHECK: cmp |
720 ; CHECK: jbe | 1036 ; CHECK: jbe |
| 1037 ; |
| 1038 ; OPTM1: icmpUle64Bool: |
| 1039 ; OPTM1: cmp |
| 1040 ; OPTM1: jb |
| 1041 ; OPTM1: ja |
| 1042 ; OPTM1: cmp |
| 1043 ; OPTM1: jbe |
721 | 1044 |
722 define internal i64 @load64(i32 %a) { | 1045 define internal i64 @load64(i32 %a) { |
723 entry: | 1046 entry: |
724 %__1 = inttoptr i32 %a to i64* | 1047 %__1 = inttoptr i32 %a to i64* |
725 %v0 = load i64* %__1, align 1 | 1048 %v0 = load i64* %__1, align 1 |
726 ret i64 %v0 | 1049 ret i64 %v0 |
727 } | 1050 } |
728 ; CHECK: load64: | 1051 ; CHECK: load64: |
729 ; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp+4] | 1052 ; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp+4] |
730 ; CHECK-NEXT: mov {{.*}}, dword ptr [e[[REGISTER]]] | 1053 ; CHECK-NEXT: mov {{.*}}, dword ptr [e[[REGISTER]]] |
731 ; CHECK-NEXT: mov {{.*}}, dword ptr [e[[REGISTER]]+4] | 1054 ; CHECK-NEXT: mov {{.*}}, dword ptr [e[[REGISTER]]+4] |
| 1055 ; |
| 1056 ; OPTM1: load64: |
| 1057 ; OPTM1: mov e{{..}}, dword ptr [e{{..}}] |
| 1058 ; OPTM1: mov e{{..}}, dword ptr [e{{..}}+4] |
732 | 1059 |
733 define internal void @store64(i32 %a, i64 %value) { | 1060 define internal void @store64(i32 %a, i64 %value) { |
734 entry: | 1061 entry: |
735 %__2 = inttoptr i32 %a to i64* | 1062 %__2 = inttoptr i32 %a to i64* |
736 store i64 %value, i64* %__2, align 1 | 1063 store i64 %value, i64* %__2, align 1 |
737 ret void | 1064 ret void |
738 } | 1065 } |
739 ; CHECK: store64: | 1066 ; CHECK: store64: |
740 ; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp+4] | 1067 ; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp+4] |
741 ; CHECK: mov dword ptr [e[[REGISTER]]+4], | 1068 ; CHECK: mov dword ptr [e[[REGISTER]]+4], |
742 ; CHECK: mov dword ptr [e[[REGISTER]]], | 1069 ; CHECK: mov dword ptr [e[[REGISTER]]], |
| 1070 ; |
| 1071 ; OPTM1: store64: |
| 1072 ; OPTM1: mov dword ptr [e[[REGISTER:[a-z]+]]+4], |
| 1073 ; OPTM1: mov dword ptr [e[[REGISTER]]], |
743 | 1074 |
744 define internal void @store64Const(i32 %a) { | 1075 define internal void @store64Const(i32 %a) { |
745 entry: | 1076 entry: |
746 %a.asptr = inttoptr i32 %a to i64* | 1077 %a.asptr = inttoptr i32 %a to i64* |
747 store i64 -2401053092306725256, i64* %a.asptr, align 1 | 1078 store i64 -2401053092306725256, i64* %a.asptr, align 1 |
748 ret void | 1079 ret void |
749 } | 1080 } |
750 ; CHECK: store64Const: | 1081 ; CHECK: store64Const: |
751 ; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp+4] | 1082 ; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp+4] |
752 ; CHECK: mov dword ptr [e[[REGISTER]]+4], 3735928559 | 1083 ; CHECK: mov dword ptr [e[[REGISTER]]+4], 3735928559 |
753 ; CHECK: mov dword ptr [e[[REGISTER]]], 305419896 | 1084 ; CHECK: mov dword ptr [e[[REGISTER]]], 305419896 |
| 1085 ; |
| 1086 ; OPTM1: store64Const: |
| 1087 ; OPTM1: mov dword ptr [e[[REGISTER:[a-z]+]]+4], 3735928559 |
| 1088 ; OPTM1: mov dword ptr [e[[REGISTER]]], 305419896 |
754 | 1089 |
755 define internal i64 @select64VarVar(i64 %a, i64 %b) { | 1090 define internal i64 @select64VarVar(i64 %a, i64 %b) { |
756 entry: | 1091 entry: |
757 %cmp = icmp ult i64 %a, %b | 1092 %cmp = icmp ult i64 %a, %b |
758 %cond = select i1 %cmp, i64 %a, i64 %b | 1093 %cond = select i1 %cmp, i64 %a, i64 %b |
759 ret i64 %cond | 1094 ret i64 %cond |
760 } | 1095 } |
761 ; CHECK: select64VarVar: | 1096 ; CHECK: select64VarVar: |
762 ; CHECK: cmp | 1097 ; CHECK: cmp |
763 ; CHECK: jb | 1098 ; CHECK: jb |
764 ; CHECK: ja | 1099 ; CHECK: ja |
765 ; CHECK: cmp | 1100 ; CHECK: cmp |
766 ; CHECK: jb | 1101 ; CHECK: jb |
767 ; CHECK: cmp | 1102 ; CHECK: cmp |
768 ; CHECK: jne | 1103 ; CHECK: jne |
| 1104 ; |
| 1105 ; OPTM1: select64VarVar: |
| 1106 ; OPTM1: cmp |
| 1107 ; OPTM1: jb |
| 1108 ; OPTM1: ja |
| 1109 ; OPTM1: cmp |
| 1110 ; OPTM1: jb |
| 1111 ; OPTM1: cmp |
| 1112 ; OPTM1: jne |
769 | 1113 |
770 define internal i64 @select64VarConst(i64 %a, i64 %b) { | 1114 define internal i64 @select64VarConst(i64 %a, i64 %b) { |
771 entry: | 1115 entry: |
772 %cmp = icmp ult i64 %a, %b | 1116 %cmp = icmp ult i64 %a, %b |
773 %cond = select i1 %cmp, i64 %a, i64 -2401053092306725256 | 1117 %cond = select i1 %cmp, i64 %a, i64 -2401053092306725256 |
774 ret i64 %cond | 1118 ret i64 %cond |
775 } | 1119 } |
776 ; CHECK: select64VarConst: | 1120 ; CHECK: select64VarConst: |
777 ; CHECK: cmp | 1121 ; CHECK: cmp |
778 ; CHECK: jb | 1122 ; CHECK: jb |
779 ; CHECK: ja | 1123 ; CHECK: ja |
780 ; CHECK: cmp | 1124 ; CHECK: cmp |
781 ; CHECK: jb | 1125 ; CHECK: jb |
782 ; CHECK: cmp | 1126 ; CHECK: cmp |
783 ; CHECK: jne | 1127 ; CHECK: jne |
| 1128 ; |
| 1129 ; OPTM1: select64VarConst: |
| 1130 ; OPTM1: cmp |
| 1131 ; OPTM1: jb |
| 1132 ; OPTM1: ja |
| 1133 ; OPTM1: cmp |
| 1134 ; OPTM1: jb |
| 1135 ; OPTM1: cmp |
| 1136 ; OPTM1: jne |
784 | 1137 |
785 define internal i64 @select64ConstVar(i64 %a, i64 %b) { | 1138 define internal i64 @select64ConstVar(i64 %a, i64 %b) { |
786 entry: | 1139 entry: |
787 %cmp = icmp ult i64 %a, %b | 1140 %cmp = icmp ult i64 %a, %b |
788 %cond = select i1 %cmp, i64 -2401053092306725256, i64 %b | 1141 %cond = select i1 %cmp, i64 -2401053092306725256, i64 %b |
789 ret i64 %cond | 1142 ret i64 %cond |
790 } | 1143 } |
791 ; CHECK: select64ConstVar: | 1144 ; CHECK: select64ConstVar: |
792 ; CHECK: cmp | 1145 ; CHECK: cmp |
793 ; CHECK: jb | 1146 ; CHECK: jb |
794 ; CHECK: ja | 1147 ; CHECK: ja |
795 ; CHECK: cmp | 1148 ; CHECK: cmp |
796 ; CHECK: jb | 1149 ; CHECK: jb |
797 ; CHECK: cmp | 1150 ; CHECK: cmp |
798 ; CHECK: jne | 1151 ; CHECK: jne |
| 1152 ; |
| 1153 ; OPTM1: select64ConstVar: |
| 1154 ; OPTM1: cmp |
| 1155 ; OPTM1: jb |
| 1156 ; OPTM1: ja |
| 1157 ; OPTM1: cmp |
| 1158 ; OPTM1: jb |
| 1159 ; OPTM1: cmp |
| 1160 ; OPTM1: jne |
799 | 1161 |
800 ; ERRORS-NOT: ICE translation error | 1162 ; ERRORS-NOT: ICE translation error |
801 ; DUMP-NOT: SZ | 1163 ; DUMP-NOT: SZ |
OLD | NEW |