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Issue 265703002: Add Om1 lowering with no optimizations (Closed) Base URL: https://gerrit.chromium.org/gerrit/p/native_client/pnacl-subzero.git@master
Patch Set: Add frem test; add LOWERING.rst file Created 6 years, 7 months ago
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1 ; RUIN: %llvm2ice %s | FileCheck %s 1 ; Simple test of signed and unsigned integer conversions.
2 ; RUIN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s 2
3 ; RUIN: %llvm2ice -O2 --verbose none %s | FileCheck %s
4 ; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck --check-prefix=OPTM1 %s
5 ; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
3 ; RUN: %szdiff --llvm2ice=%llvm2ice %s | FileCheck --check-prefix=DUMP %s 6 ; RUN: %szdiff --llvm2ice=%llvm2ice %s | FileCheck --check-prefix=DUMP %s
4 7
5 @i8v = common global i8 0, align 1 8 @i8v = common global i8 0, align 1
6 @i16v = common global i16 0, align 2 9 @i16v = common global i16 0, align 2
7 @i32v = common global i32 0, align 4 10 @i32v = common global i32 0, align 4
8 @i64v = common global i64 0, align 8 11 @i64v = common global i64 0, align 8
9 @u8v = common global i8 0, align 1 12 @u8v = common global i8 0, align 1
10 @u16v = common global i16 0, align 2 13 @u16v = common global i16 0, align 2
11 @u32v = common global i32 0, align 4 14 @u32v = common global i32 0, align 4
12 @u64v = common global i64 0, align 8 15 @u64v = common global i64 0, align 8
13 @i1 = common global i32 0, align 4 16 @i1 = common global i32 0, align 4
14 @i2 = common global i32 0, align 4 17 @i2 = common global i32 0, align 4
15 @u1 = common global i32 0, align 4 18 @u1 = common global i32 0, align 4
16 @u2 = common global i32 0, align 4 19 @u2 = common global i32 0, align 4
17 20
18 define void @from_int8() { 21 define void @from_int8() {
19 entry: 22 entry:
20 %v0 = load i8* @i8v, align 1 23 %v0 = load i8* @i8v, align 1
21 %v1 = sext i8 %v0 to i16 24 %v1 = sext i8 %v0 to i16
22 store i16 %v1, i16* @i16v, align 1 25 store i16 %v1, i16* @i16v, align 1
23 %v2 = sext i8 %v0 to i32 26 %v2 = sext i8 %v0 to i32
24 store i32 %v2, i32* @i32v, align 1 27 store i32 %v2, i32* @i32v, align 1
25 %v3 = sext i8 %v0 to i64 28 %v3 = sext i8 %v0 to i64
26 store i64 %v3, i64* @i64v, align 1 29 store i64 %v3, i64* @i64v, align 1
27 ret void 30 ret void
28 ; CHECK: mov al, byte ptr [
29 ; CHECK-NEXT: movsx cx, al
30 ; CHECK-NEXT: mov word ptr [
31 ; CHECK-NEXT: movsx ecx, al
32 ; CHECK-NEXT: mov dword ptr [
33 ; CHECK-NEXT: movsx ecx, al
34 ; CHECK-NEXT: sar eax, 31
35 ; CHECK-NEXT: mov dword ptr [i64v+4],
36 ; CHECK-NEXT: mov dword ptr [i64v],
37 } 31 }
32 ; CHECK: from_int8:
33 ; CHECK: mov al, byte ptr [
34 ; CHECK-NEXT: movsx cx, al
35 ; CHECK-NEXT: mov word ptr [
36 ; CHECK-NEXT: movsx ecx, al
37 ; CHECK-NEXT: mov dword ptr [
38 ; CHECK-NEXT: movsx ecx, al
39 ; CHECK-NEXT: sar eax, 31
40 ; CHECK-NEXT: mov dword ptr [i64v+4],
41 ; CHECK-NEXT: mov dword ptr [i64v],
42 ;
43 ; OPTM1: from_int8:
44 ; OPTM1: mov {{.*}}, byte ptr [
45 ; OPTM1: movsx
46 ; OPTM1: mov word ptr [
47 ; OPTM1: movsx
48 ; OPTM1: mov dword ptr [
49 ; OPTM1: movsx
50 ; OPTM1: sar {{.*}}, 31
51 ; OPTM1: mov dword ptr [i64v+4],
52 ; OPTM1: mov dword ptr [i64v],
38 53
39 define void @from_int16() { 54 define void @from_int16() {
40 entry: 55 entry:
41 %v0 = load i16* @i16v, align 1 56 %v0 = load i16* @i16v, align 1
42 %v1 = trunc i16 %v0 to i8 57 %v1 = trunc i16 %v0 to i8
43 store i8 %v1, i8* @i8v, align 1 58 store i8 %v1, i8* @i8v, align 1
44 %v2 = sext i16 %v0 to i32 59 %v2 = sext i16 %v0 to i32
45 store i32 %v2, i32* @i32v, align 1 60 store i32 %v2, i32* @i32v, align 1
46 %v3 = sext i16 %v0 to i64 61 %v3 = sext i16 %v0 to i64
47 store i64 %v3, i64* @i64v, align 1 62 store i64 %v3, i64* @i64v, align 1
48 ret void 63 ret void
49 ; CHECK: mov ax, word ptr [
50 ; CHECK-NEXT: mov cx, ax
51 ; CHECK-NEXT: mov byte ptr [
52 ; CHECK-NEXT: movsx ecx, ax
53 ; CHECK-NEXT: mov dword ptr [
54 ; CHECK-NEXT: movsx ecx, ax
55 ; CHECK-NEXT: sar eax, 31
56 ; CHECK-NEXT: mov dword ptr [i64v+4],
57 ; CHECK-NEXT: mov dword ptr [i64v],
58 } 64 }
65 ; CHECK: from_int16:
66 ; CHECK: mov ax, word ptr [
67 ; CHECK-NEXT: mov cx, ax
68 ; CHECK-NEXT: mov byte ptr [
69 ; CHECK-NEXT: movsx ecx, ax
70 ; CHECK-NEXT: mov dword ptr [
71 ; CHECK-NEXT: movsx ecx, ax
72 ; CHECK-NEXT: sar eax, 31
73 ; CHECK-NEXT: mov dword ptr [i64v+4],
74 ; CHECK-NEXT: mov dword ptr [i64v],
75 ;
76 ; OPTM1: from_int16:
77 ; OPTM1: mov {{.*}}, word ptr [
78 ; OPTM1: mov byte ptr [i8v],
79 ; OPTM1: movsx
80 ; OPTM1: mov dword ptr [i32v],
81 ; OPTM1: movsx
82 ; OPTM1: sar {{.*}}, 31
83 ; OPTM1: mov dword ptr [i64v+4],
84 ; OPTM1: mov dword ptr [i64v],
59 85
60 define void @from_int32() { 86 define void @from_int32() {
61 entry: 87 entry:
62 %v0 = load i32* @i32v, align 1 88 %v0 = load i32* @i32v, align 1
63 %v1 = trunc i32 %v0 to i8 89 %v1 = trunc i32 %v0 to i8
64 store i8 %v1, i8* @i8v, align 1 90 store i8 %v1, i8* @i8v, align 1
65 %v2 = trunc i32 %v0 to i16 91 %v2 = trunc i32 %v0 to i16
66 store i16 %v2, i16* @i16v, align 1 92 store i16 %v2, i16* @i16v, align 1
67 %v3 = sext i32 %v0 to i64 93 %v3 = sext i32 %v0 to i64
68 store i64 %v3, i64* @i64v, align 1 94 store i64 %v3, i64* @i64v, align 1
69 ret void 95 ret void
70 ; CHECK: mov eax, dword ptr [
71 ; CHECK-NEXT: mov ecx, eax
72 ; CHECK-NEXT: mov byte ptr [
73 ; CHECK-NEXT: mov ecx, eax
74 ; CHECK-NEXT: mov word ptr [
75 ; CHECK-NEXT: mov ecx, eax
76 ; CHECK-NEXT: sar eax, 31
77 ; CHECK-NEXT: mov dword ptr [i64v+4],
78 ; CHECK-NEXT: mov dword ptr [i64v],
79 } 96 }
97 ; CHECK: from_int32:
98 ; CHECK: mov eax, dword ptr [
99 ; CHECK-NEXT: mov ecx, eax
100 ; CHECK-NEXT: mov byte ptr [
101 ; CHECK-NEXT: mov ecx, eax
102 ; CHECK-NEXT: mov word ptr [
103 ; CHECK-NEXT: mov ecx, eax
104 ; CHECK-NEXT: sar eax, 31
105 ; CHECK-NEXT: mov dword ptr [i64v+4],
106 ; CHECK-NEXT: mov dword ptr [i64v],
107 ;
108 ; OPTM1: from_int32:
109 ; OPTM1: mov {{.*}}, dword ptr [i32v]
110 ; OPTM1: mov byte ptr [i8v],
111 ; OPTM1: mov word ptr [i16v],
112 ; OPTM1: sar {{.*}}, 31
113 ; OPTM1: mov dword ptr [i64v+4],
114 ; OPTM1: mov dword ptr [i64v],
80 115
81 define void @from_int64() { 116 define void @from_int64() {
82 entry: 117 entry:
83 %v0 = load i64* @i64v, align 1 118 %v0 = load i64* @i64v, align 1
84 %v1 = trunc i64 %v0 to i8 119 %v1 = trunc i64 %v0 to i8
85 store i8 %v1, i8* @i8v, align 1 120 store i8 %v1, i8* @i8v, align 1
86 %v2 = trunc i64 %v0 to i16 121 %v2 = trunc i64 %v0 to i16
87 store i16 %v2, i16* @i16v, align 1 122 store i16 %v2, i16* @i16v, align 1
88 %v3 = trunc i64 %v0 to i32 123 %v3 = trunc i64 %v0 to i32
89 store i32 %v3, i32* @i32v, align 1 124 store i32 %v3, i32* @i32v, align 1
90 ret void 125 ret void
91 ; CHECK: mov eax, dword ptr [
92 ; CHECK-NEXT: mov ecx, eax
93 ; CHECK-NEXT: mov byte ptr [
94 ; CHECK-NEXT: mov ecx, eax
95 ; CHECK-NEXT: mov word ptr [
96 ; CHECK-NEXT: mov dword ptr [
97 } 126 }
127 ; CHECK: from_int64:
128 ; CHECK: mov eax, dword ptr [
129 ; CHECK-NEXT: mov ecx, eax
130 ; CHECK-NEXT: mov byte ptr [
131 ; CHECK-NEXT: mov ecx, eax
132 ; CHECK-NEXT: mov word ptr [
133 ; CHECK-NEXT: mov dword ptr [
134 ;
135 ; OPTM1: from_int64:
136 ; OPTM1: mov {{.*}}, dword ptr [i64v]
137 ; OPTM1: mov {{.*}}, dword ptr [i64v+4]
138 ; OPTM1: mov byte ptr [i8v],
139 ; OPTM1: mov word ptr [i16v],
140 ; OPTM1: mov dword ptr [i32v],
98 141
99 define void @from_uint8() { 142 define void @from_uint8() {
100 entry: 143 entry:
101 %v0 = load i8* @u8v, align 1 144 %v0 = load i8* @u8v, align 1
102 %v1 = zext i8 %v0 to i16 145 %v1 = zext i8 %v0 to i16
103 store i16 %v1, i16* @i16v, align 1 146 store i16 %v1, i16* @i16v, align 1
104 %v2 = zext i8 %v0 to i32 147 %v2 = zext i8 %v0 to i32
105 store i32 %v2, i32* @i32v, align 1 148 store i32 %v2, i32* @i32v, align 1
106 %v3 = zext i8 %v0 to i64 149 %v3 = zext i8 %v0 to i64
107 store i64 %v3, i64* @i64v, align 1 150 store i64 %v3, i64* @i64v, align 1
108 ret void 151 ret void
109 ; CHECK: mov al, byte ptr [
110 ; CHECK-NEXT: movzx cx, al
111 ; CHECK-NEXT: mov word ptr [
112 ; CHECK-NEXT: movzx ecx, al
113 ; CHECK-NEXT: mov dword ptr [
114 ; CHECK-NEXT: movzx eax, al
115 ; CHECK-NEXT: mov ecx, 0
116 ; CHECK-NEXT: mov dword ptr [i64v+4],
117 ; CHECK-NEXT: mov dword ptr [i64v],
118 } 152 }
153 ; CHECK: from_uint8:
154 ; CHECK: mov al, byte ptr [
155 ; CHECK-NEXT: movzx cx, al
156 ; CHECK-NEXT: mov word ptr [
157 ; CHECK-NEXT: movzx ecx, al
158 ; CHECK-NEXT: mov dword ptr [
159 ; CHECK-NEXT: movzx eax, al
160 ; CHECK-NEXT: mov ecx, 0
161 ; CHECK-NEXT: mov dword ptr [i64v+4],
162 ; CHECK-NEXT: mov dword ptr [i64v],
163 ;
164 ; OPTM1: from_uint8:
165 ; OPTM1: mov {{.*}}, byte ptr [u8v]
166 ; OPTM1: movzx
167 ; OPTM1: mov word ptr [i16v],
168 ; OPTM1: movzx
169 ; OPTM1: mov dword ptr [i32v],
170 ; OPTM1: movzx
171 ; OPTM1: mov {{.*}}, 0
172 ; OPTM1: mov dword ptr [i64v+4],
173 ; OPTM1: mov dword ptr [i64v],
119 174
120 define void @from_uint16() { 175 define void @from_uint16() {
121 entry: 176 entry:
122 %v0 = load i16* @u16v, align 1 177 %v0 = load i16* @u16v, align 1
123 %v1 = trunc i16 %v0 to i8 178 %v1 = trunc i16 %v0 to i8
124 store i8 %v1, i8* @i8v, align 1 179 store i8 %v1, i8* @i8v, align 1
125 %v2 = zext i16 %v0 to i32 180 %v2 = zext i16 %v0 to i32
126 store i32 %v2, i32* @i32v, align 1 181 store i32 %v2, i32* @i32v, align 1
127 %v3 = zext i16 %v0 to i64 182 %v3 = zext i16 %v0 to i64
128 store i64 %v3, i64* @i64v, align 1 183 store i64 %v3, i64* @i64v, align 1
129 ret void 184 ret void
130 ; CHECK: mov ax, word ptr [
131 ; CHECK-NEXT: mov cx, ax
132 ; CHECK-NEXT: mov byte ptr [
133 ; CHECK-NEXT: movzx ecx, ax
134 ; CHECK-NEXT: mov dword ptr [
135 ; CHECK-NEXT: movzx eax, ax
136 ; CHECK-NEXT: mov ecx, 0
137 ; CHECK-NEXT: mov dword ptr [i64v+4],
138 ; CHECK-NEXT: mov dword ptr [i64v],
139 } 185 }
186 ; CHECK: from_uint16:
187 ; CHECK: mov ax, word ptr [
188 ; CHECK-NEXT: mov cx, ax
189 ; CHECK-NEXT: mov byte ptr [
190 ; CHECK-NEXT: movzx ecx, ax
191 ; CHECK-NEXT: mov dword ptr [
192 ; CHECK-NEXT: movzx eax, ax
193 ; CHECK-NEXT: mov ecx, 0
194 ; CHECK-NEXT: mov dword ptr [i64v+4],
195 ; CHECK-NEXT: mov dword ptr [i64v],
196 ;
197 ; OPTM1: from_uint16:
198 ; OPTM1: mov {{.*}}, word ptr [u16v]
199 ; OPTM1: mov byte ptr [i8v],
200 ; OPTM1: movzx
201 ; OPTM1: mov dword ptr [i32v],
202 ; OPTM1: movzx
203 ; OPTM1: mov {{.*}}, 0
204 ; OPTM1: mov dword ptr [i64v+4],
205 ; OPTM1: mov dword ptr [i64v],
140 206
141 define void @from_uint32() { 207 define void @from_uint32() {
142 entry: 208 entry:
143 %v0 = load i32* @u32v, align 1 209 %v0 = load i32* @u32v, align 1
144 %v1 = trunc i32 %v0 to i8 210 %v1 = trunc i32 %v0 to i8
145 store i8 %v1, i8* @i8v, align 1 211 store i8 %v1, i8* @i8v, align 1
146 %v2 = trunc i32 %v0 to i16 212 %v2 = trunc i32 %v0 to i16
147 store i16 %v2, i16* @i16v, align 1 213 store i16 %v2, i16* @i16v, align 1
148 %v3 = zext i32 %v0 to i64 214 %v3 = zext i32 %v0 to i64
149 store i64 %v3, i64* @i64v, align 1 215 store i64 %v3, i64* @i64v, align 1
150 ret void 216 ret void
151 ; CHECK: mov eax, dword ptr [
152 ; CHECK-NEXT: mov ecx, eax
153 ; CHECK-NEXT: mov byte ptr [
154 ; CHECK-NEXT: mov ecx, eax
155 ; CHECK-NEXT: mov word ptr [
156 ; CHECK-NEXT: mov ecx, 0
157 ; CHECK-NEXT: mov dword ptr [i64v+4],
158 ; CHECK-NEXT: mov dword ptr [i64v],
159 } 217 }
218 ; CHECK: from_uint32:
219 ; CHECK: mov eax, dword ptr [
220 ; CHECK-NEXT: mov ecx, eax
221 ; CHECK-NEXT: mov byte ptr [
222 ; CHECK-NEXT: mov ecx, eax
223 ; CHECK-NEXT: mov word ptr [
224 ; CHECK-NEXT: mov ecx, 0
225 ; CHECK-NEXT: mov dword ptr [i64v+4],
226 ; CHECK-NEXT: mov dword ptr [i64v],
227 ;
228 ; OPTM1: from_uint32:
229 ; OPTM1: mov {{.*}}, dword ptr [u32v]
230 ; OPTM1: mov byte ptr [i8v],
231 ; OPTM1: mov word ptr [i16v],
232 ; OPTM1: mov {{.*}}, 0
233 ; OPTM1: mov dword ptr [i64v+4],
234 ; OPTM1: mov dword ptr [i64v],
160 235
161 define void @from_uint64() { 236 define void @from_uint64() {
162 entry: 237 entry:
163 %v0 = load i64* @u64v, align 1 238 %v0 = load i64* @u64v, align 1
164 %v1 = trunc i64 %v0 to i8 239 %v1 = trunc i64 %v0 to i8
165 store i8 %v1, i8* @i8v, align 1 240 store i8 %v1, i8* @i8v, align 1
166 %v2 = trunc i64 %v0 to i16 241 %v2 = trunc i64 %v0 to i16
167 store i16 %v2, i16* @i16v, align 1 242 store i16 %v2, i16* @i16v, align 1
168 %v3 = trunc i64 %v0 to i32 243 %v3 = trunc i64 %v0 to i32
169 store i32 %v3, i32* @i32v, align 1 244 store i32 %v3, i32* @i32v, align 1
170 ret void 245 ret void
171 ; CHECK: mov eax, dword ptr [
172 ; CHECK-NEXT: mov ecx, eax
173 ; CHECK-NEXT: mov byte ptr [
174 ; CHECK-NEXT: mov ecx, eax
175 ; CHECK-NEXT: mov word ptr [
176 ; CHECK-NEXT: mov dword ptr [
177 } 246 }
247 ; CHECK: from_uint64:
248 ; CHECK: mov eax, dword ptr [
249 ; CHECK-NEXT: mov ecx, eax
250 ; CHECK-NEXT: mov byte ptr [
251 ; CHECK-NEXT: mov ecx, eax
252 ; CHECK-NEXT: mov word ptr [
253 ; CHECK-NEXT: mov dword ptr [
254 ;
255 ; OPTM1: from_uint64:
256 ; OPTM1: mov eax, dword ptr [u64v]
257 ; OPTM1: mov byte ptr [i8v],
258 ; OPTM1: mov word ptr [i16v],
259 ; OPTM1: mov dword ptr [i32v],
178 260
179 ; ERRORS-NOT: ICE translation error 261 ; ERRORS-NOT: ICE translation error
180 ; DUMP-NOT: SZ 262 ; DUMP-NOT: SZ
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