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Issue 2656723003: [SubZero] Fix code generation of AtomicCmpxchg (Closed)
Patch Set: Created 3 years, 10 months ago
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1 ; This tests each of the supported NaCl atomic instructions for every 1 ; This tests each of the supported NaCl atomic instructions for every
2 ; size allowed. 2 ; size allowed.
3 3
4 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \ 4 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
5 ; RUN: -allow-externally-defined-symbols | FileCheck %s 5 ; RUN: -allow-externally-defined-symbols | FileCheck %s
6 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \ 6 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
7 ; RUN: -allow-externally-defined-symbols | FileCheck --check-prefix=O2 %s 7 ; RUN: -allow-externally-defined-symbols | FileCheck --check-prefix=O2 %s
8 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \ 8 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
9 ; RUN: -allow-externally-defined-symbols | FileCheck %s 9 ; RUN: -allow-externally-defined-symbols | FileCheck %s
10 10
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1631 ; ARM32: dmb 1631 ; ARM32: dmb
1632 ; ARM32: ldrexb [[V:r[0-9]+]], {{[[]}}[[A:r[0-9]+]]{{[]]}} 1632 ; ARM32: ldrexb [[V:r[0-9]+]], {{[[]}}[[A:r[0-9]+]]{{[]]}}
1633 ; ARM32: lsl [[VV:r[0-9]+]], [[V]], #24 1633 ; ARM32: lsl [[VV:r[0-9]+]], [[V]], #24
1634 ; ARM32: cmp [[VV]], {{r[0-9]+}}, lsl #24 1634 ; ARM32: cmp [[VV]], {{r[0-9]+}}, lsl #24
1635 ; ARM32: movne [[SUCCESS:r[0-9]+]], 1635 ; ARM32: movne [[SUCCESS:r[0-9]+]],
1636 ; ARM32: strexbeq [[SUCCESS]], {{r[0-9]+}}, {{[[]}}[[A]]{{[]]}} 1636 ; ARM32: strexbeq [[SUCCESS]], {{r[0-9]+}}, {{[[]}}[[A]]{{[]]}}
1637 ; ARM32: cmp [[SUCCESS]], #0 1637 ; ARM32: cmp [[SUCCESS]], #0
1638 ; ARM32: bne 1638 ; ARM32: bne
1639 ; ARM32: dmb 1639 ; ARM32: dmb
1640 ; MIPS32-LABEL: test_atomic_cmpxchg_8 1640 ; MIPS32-LABEL: test_atomic_cmpxchg_8
1641 ; MIPS32: sync
1642 ; MIPS32: addiu {{.*}}, $zero, -4 1641 ; MIPS32: addiu {{.*}}, $zero, -4
1643 ; MIPS32: and 1642 ; MIPS32: and
1644 ; MIPS32: andi {{.*}}, {{.*}}, 3 1643 ; MIPS32: andi {{.*}}, {{.*}}, 3
1645 ; MIPS32: sll {{.*}}, {{.*}}, 3 1644 ; MIPS32: sll {{.*}}, {{.*}}, 3
1646 ; MIPS32: ori {{.*}}, $zero, 255 1645 ; MIPS32: ori {{.*}}, $zero, 255
1647 ; MIPS32: sllv 1646 ; MIPS32: sllv
1648 ; MIPS32: nor 1647 ; MIPS32: nor
1649 ; MIPS32: andi {{.*}}, {{.*}}, 255 1648 ; MIPS32: andi {{.*}}, {{.*}}, 255
1650 ; MIPS32: sllv 1649 ; MIPS32: sllv
1651 ; MIPS32: andi {{.*}}, {{.*}}, 255 1650 ; MIPS32: andi {{.*}}, {{.*}}, 255
1652 ; MIPS32: sllv 1651 ; MIPS32: sllv
1652 ; MIPS32: sync
1653 ; MIPS32: ll 1653 ; MIPS32: ll
1654 ; MIPS32: and 1654 ; MIPS32: and
1655 ; MIPS32: bne 1655 ; MIPS32: bne
1656 ; MIPS32: and 1656 ; MIPS32: and
1657 ; MIPS32: or 1657 ; MIPS32: or
1658 ; MIPS32: sc 1658 ; MIPS32: sc
1659 ; MIPS32: beq $zero, {{.*}}, {{.*}} 1659 ; MIPS32: beq $zero, {{.*}}, {{.*}}
1660 ; MIPS32: srlv 1660 ; MIPS32: srlv
1661 ; MIPS32: sll {{.*}}, {{.*}}, 24 1661 ; MIPS32: sll {{.*}}, {{.*}}, 24
1662 ; MIPS32: sra {{.*}}, {{.*}}, 24 1662 ; MIPS32: sra {{.*}}, {{.*}}, 24
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1680 ; ARM32: dmb 1680 ; ARM32: dmb
1681 ; ARM32: ldrexh [[V:r[0-9]+]], {{[[]}}[[A:r[0-9]+]]{{[]]}} 1681 ; ARM32: ldrexh [[V:r[0-9]+]], {{[[]}}[[A:r[0-9]+]]{{[]]}}
1682 ; ARM32: lsl [[VV:r[0-9]+]], [[V]], #16 1682 ; ARM32: lsl [[VV:r[0-9]+]], [[V]], #16
1683 ; ARM32: cmp [[VV]], {{r[0-9]+}}, lsl #16 1683 ; ARM32: cmp [[VV]], {{r[0-9]+}}, lsl #16
1684 ; ARM32: movne [[SUCCESS:r[0-9]+]], 1684 ; ARM32: movne [[SUCCESS:r[0-9]+]],
1685 ; ARM32: strexheq [[SUCCESS]], {{r[0-9]+}}, {{[[]}}[[A]]{{[]]}} 1685 ; ARM32: strexheq [[SUCCESS]], {{r[0-9]+}}, {{[[]}}[[A]]{{[]]}}
1686 ; ARM32: cmp [[SUCCESS]], #0 1686 ; ARM32: cmp [[SUCCESS]], #0
1687 ; ARM32: bne 1687 ; ARM32: bne
1688 ; ARM32: dmb 1688 ; ARM32: dmb
1689 ; MIPS32-LABEL: test_atomic_cmpxchg_16 1689 ; MIPS32-LABEL: test_atomic_cmpxchg_16
1690 ; MIPS32: sync
1691 ; MIPS32: addiu {{.*}}, $zero, -4 1690 ; MIPS32: addiu {{.*}}, $zero, -4
1692 ; MIPS32: and 1691 ; MIPS32: and
1693 ; MIPS32: andi {{.*}}, {{.*}}, 3 1692 ; MIPS32: andi {{.*}}, {{.*}}, 3
1694 ; MIPS32: sll {{.*}}, {{.*}}, 3 1693 ; MIPS32: sll {{.*}}, {{.*}}, 3
1695 ; MIPS32: ori {{.*}}, {{.*}}, 65535 1694 ; MIPS32: ori {{.*}}, {{.*}}, 65535
1696 ; MIPS32: sllv 1695 ; MIPS32: sllv
1697 ; MIPS32: nor 1696 ; MIPS32: nor
1698 ; MIPS32: andi {{.*}}, {{.*}}, 65535 1697 ; MIPS32: andi {{.*}}, {{.*}}, 65535
1699 ; MIPS32: sllv 1698 ; MIPS32: sllv
1700 ; MIPS32: andi {{.*}}, {{.*}}, 65535 1699 ; MIPS32: andi {{.*}}, {{.*}}, 65535
1701 ; MIPS32: sllv 1700 ; MIPS32: sllv
1701 ; MIPS32: sync
1702 ; MIPS32: ll 1702 ; MIPS32: ll
1703 ; MIPS32: and 1703 ; MIPS32: and
1704 ; MIPS32: bne 1704 ; MIPS32: bne
1705 ; MIPS32: and 1705 ; MIPS32: and
1706 ; MIPS32: or 1706 ; MIPS32: or
1707 ; MIPS32: sc 1707 ; MIPS32: sc
1708 ; MIPS32: beq $zero, {{.*}}, {{.*}} 1708 ; MIPS32: beq $zero, {{.*}}, {{.*}}
1709 ; MIPS32: srlv 1709 ; MIPS32: srlv
1710 ; MIPS32: sll {{.*}}, {{.*}}, 16 1710 ; MIPS32: sll {{.*}}, {{.*}}, 16
1711 ; MIPS32: sra {{.*}}, {{.*}}, 16 1711 ; MIPS32: sra {{.*}}, {{.*}}, 16
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2155 br i1 %cmp, label %done, label %body 2155 br i1 %cmp, label %done, label %body
2156 done: 2156 done:
2157 ret void 2157 ret void
2158 } 2158 }
2159 ; O2-LABEL: test_cmpxchg8b_regalloc 2159 ; O2-LABEL: test_cmpxchg8b_regalloc
2160 ;;; eax and some other register will be used in the cmpxchg instruction. 2160 ;;; eax and some other register will be used in the cmpxchg instruction.
2161 ; O2: lock cmpxchg8b QWORD PTR 2161 ; O2: lock cmpxchg8b QWORD PTR
2162 ;;; Make sure eax/ecx/edx/ebx aren't used again, e.g. as the induction variable. 2162 ;;; Make sure eax/ecx/edx/ebx aren't used again, e.g. as the induction variable.
2163 ; O2-NOT: ,{{eax|ecx|edx|ebx}} 2163 ; O2-NOT: ,{{eax|ecx|edx|ebx}}
2164 ; O2: pop ebx 2164 ; O2: pop ebx
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