[SubZero] Fix code generation of AtomicCmpxchg

src/IceTargetLoweringMIPS32.cpp

 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost
@@ skipping 4536 matching lines @@
     auto *New = Instr->getArg(2);
     auto *Expected = Instr->getArg(1);
     auto *ActualAddress = Instr->getArg(0);
 
     if (DestTy == IceType_i64) {
       InstMIPS32Label *Retry1 = InstMIPS32Label::create(Func, this);
       auto *T1 = I32Reg();
       auto *T2 = I32Reg();
       auto *T3 = I32Reg();
       auto *T4 = I32Reg();
-      _sync();
+      auto *T5 = I32Reg();
+      auto *T6 = I32Reg();
       Variable *ValHi, *ValLo, *ExpectedLo, *ExpectedHi;
       if (llvm::isa<ConstantUndef>(Expected)) {
         ExpectedLo = legalizeToReg(Ctx->getConstantZero(IceType_i32));
         ExpectedHi = legalizeToReg(Ctx->getConstantZero(IceType_i32));
       } else if (auto *Expected64 = llvm::dyn_cast<Variable64On32>(Expected)) {
         ExpectedLo = legalizeToReg(loOperand(Expected64));
         ExpectedHi = legalizeToReg(hiOperand(Expected64));
       } else if (auto *C64 = llvm::dyn_cast<ConstantInteger64>(Expected)) {
         const uint64_t Value = C64->getValue();
         uint64_t Upper32Bits = (Value >> INT32_BITS) & 0xFFFFFFFF;
@@ skipping 18 matching lines @@
       auto *Dest64 = llvm::cast<Variable64On32>(Dest);
       auto *BaseR = legalizeToReg(ActualAddress);
       auto *AddrLo = OperandMIPS32Mem::create(
           Func, IceType_i32, BaseR,
           llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(0)));
       auto *AddrHi = OperandMIPS32Mem::create(
           Func, IceType_i32, BaseR,
           llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(4)));
       lowerLoad(InstLoad::create(Func, T3, AddrLo));
       lowerLoad(InstLoad::create(Func, T4, AddrHi));
+      _sync();
       Context.insert(Retry);
       Sandboxer(this).ll(T1, AddrLo);
       _br(NoTarget, NoTarget, T1, ExpectedLo, Exit, CondMIPS32::Cond::NE);
-      Sandboxer(this).sc(ValLo, AddrLo);
-      _br(NoTarget, NoTarget, ValLo, getZero(), Retry, CondMIPS32::Cond::EQ);
+      _mov(T5, ValLo);
+      Sandboxer(this).sc(T5, AddrLo);
+      Context.insert<InstFakeUse>(ValLo);
+      Context.insert<InstFakeUse>(ExpectedLo);
+      _br(NoTarget, NoTarget, T5, getZero(), Retry, CondMIPS32::Cond::EQ);
       Context.insert(Retry1);
       Sandboxer(this).ll(T2, AddrHi);
       _br(NoTarget, NoTarget, T2, ExpectedHi, Exit, CondMIPS32::Cond::NE);
-      Sandboxer(this).sc(ValHi, AddrHi);
-      _br(NoTarget, NoTarget, ValHi, getZero(), Retry1, CondMIPS32::Cond::EQ);
+      _mov(T6, ValHi);
+      Sandboxer(this).sc(T6, AddrHi);
+      Context.insert<InstFakeUse>(ValHi);
+      Context.insert<InstFakeUse>(ExpectedHi);
+      _br(NoTarget, NoTarget, T6, getZero(), Retry1, CondMIPS32::Cond::EQ);
       Context.insert<InstFakeUse>(getZero());
       Context.insert(Exit);
       _mov(Dest64->getLo(), T3);
       _mov(Dest64->getHi(), T4);
       _sync();
     } else if (DestTy == IceType_i8 || DestTy == IceType_i16) {
       auto *NewR = legalizeToReg(New);
       auto *ExpectedR = legalizeToReg(Expected);
       auto *ActualAddressR = legalizeToReg(ActualAddress);
       const uint32_t ShiftAmount =
           (INT32_BITS - CHAR_BITS * typeWidthInBytes(DestTy));
       const uint32_t Mask = (1 << (CHAR_BITS * typeWidthInBytes(DestTy))) - 1;
       auto *RegAt = getPhysicalRegister(RegMIPS32::Reg_AT);
       auto *T1 = I32Reg();
       auto *T2 = I32Reg();
       auto *T3 = I32Reg();
       auto *T4 = I32Reg();
       auto *T5 = I32Reg();
       auto *T6 = I32Reg();
       auto *T7 = I32Reg();
       auto *T8 = I32Reg();
       auto *T9 = I32Reg();
-      _sync();
       _addiu(RegAt, getZero(), -4);
       _and(T1, ActualAddressR, RegAt);
       _andi(RegAt, ActualAddressR, 3);
       _sll(T2, RegAt, 3);
       _ori(RegAt, getZero(), Mask);
       _sllv(T3, RegAt, T2);
       _nor(T4, getZero(), T3);
       _andi(RegAt, ExpectedR, Mask);
       _sllv(T5, RegAt, T2);
       _andi(RegAt, NewR, Mask);
       _sllv(T6, RegAt, T2);
+      _sync();
       Context.insert(Retry);
       Sandboxer(this).ll(T7, formMemoryOperand(T1, DestTy));
       _and(T8, T7, T3);
       _br(NoTarget, NoTarget, T8, T5, Exit, CondMIPS32::Cond::NE);
       _and(RegAt, T7, T4);
       _or(T9, RegAt, T6);
       Sandboxer(this).sc(T9, formMemoryOperand(T1, DestTy));
+      Context.insert<InstFakeUse>(T6);
       _br(NoTarget, NoTarget, getZero(), T9, Retry, CondMIPS32::Cond::EQ);
       Context.insert<InstFakeUse>(getZero());
       Context.insert(Exit);
       _srlv(RegAt, T8, T2);
       _sll(RegAt, RegAt, ShiftAmount);
       _sra(RegAt, RegAt, ShiftAmount);
       _mov(Dest, RegAt);
       _sync();
       Context.insert<InstFakeUse>(ExpectedR);
       Context.insert<InstFakeUse>(NewR);
     } else {
       auto *T1 = I32Reg();
-      _sync();
-      Context.insert(Retry);
+      auto *T2 = I32Reg();
       auto *NewR = legalizeToReg(New);
       auto *ExpectedR = legalizeToReg(Expected);
       auto *ActualAddressR = legalizeToReg(ActualAddress);
+      _sync();
+      Context.insert(Retry);
       Sandboxer(this).ll(T1, formMemoryOperand(ActualAddressR, DestTy));
       _br(NoTarget, NoTarget, T1, ExpectedR, Exit, CondMIPS32::Cond::NE);
-      Sandboxer(this).sc(NewR, formMemoryOperand(ActualAddressR, DestTy));
-      _br(NoTarget, NoTarget, NewR, getZero(), Retry, CondMIPS32::Cond::EQ);
+      _mov(T2, NewR);
+      Sandboxer(this).sc(T2, formMemoryOperand(ActualAddressR, DestTy));
+      _br(NoTarget, NoTarget, T2, getZero(), Retry, CondMIPS32::Cond::EQ);
       Context.insert<InstFakeUse>(getZero());
       Context.insert(Exit);
       _mov(Dest, T1);
       _sync();
       Context.insert<InstFakeUse>(ExpectedR);
       Context.insert<InstFakeUse>(NewR);
     }
     return;
   }
   case Intrinsics::AtomicRMW: {
@@ skipping 1505 matching lines @@
       auto *T6 = Target->makeReg(IceType_i32, RegMIPS32::Reg_T6);
       Target->Context.insert<InstFakeDef>(T6);
       Target->_and(CallTargetR, CallTargetR, T6);
     }
   }
   return Target->Context.insert<InstMIPS32Call>(ReturnReg, CallTarget);
 }
 
 } // end of namespace MIPS32
 } // end of namespace Ice