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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include "src/compiler/code-generator.h" | 5 #include "src/compiler/code-generator.h" |
6 | 6 |
7 #include "src/arm/macro-assembler-arm.h" | 7 #include "src/arm/macro-assembler-arm.h" |
8 #include "src/compilation-info.h" | 8 #include "src/compilation-info.h" |
9 #include "src/compiler/code-generator-impl.h" | 9 #include "src/compiler/code-generator-impl.h" |
10 #include "src/compiler/gap-resolver.h" | 10 #include "src/compiler/gap-resolver.h" |
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1538 case kArmFloat32x4Add: { | 1538 case kArmFloat32x4Add: { |
1539 __ vadd(i.OutputSimd128Register(), i.InputSimd128Register(0), | 1539 __ vadd(i.OutputSimd128Register(), i.InputSimd128Register(0), |
1540 i.InputSimd128Register(1)); | 1540 i.InputSimd128Register(1)); |
1541 break; | 1541 break; |
1542 } | 1542 } |
1543 case kArmFloat32x4Sub: { | 1543 case kArmFloat32x4Sub: { |
1544 __ vsub(i.OutputSimd128Register(), i.InputSimd128Register(0), | 1544 __ vsub(i.OutputSimd128Register(), i.InputSimd128Register(0), |
1545 i.InputSimd128Register(1)); | 1545 i.InputSimd128Register(1)); |
1546 break; | 1546 break; |
1547 } | 1547 } |
1548 case kArmFloat32x4Eq: { | 1548 case kArmFloat32x4Equal: { |
1549 __ vceq(i.OutputSimd128Register(), i.InputSimd128Register(0), | 1549 __ vceq(i.OutputSimd128Register(), i.InputSimd128Register(0), |
1550 i.InputSimd128Register(1)); | 1550 i.InputSimd128Register(1)); |
1551 break; | 1551 break; |
1552 } | 1552 } |
1553 case kArmFloat32x4Ne: { | 1553 case kArmFloat32x4NotEqual: { |
1554 Simd128Register dst = i.OutputSimd128Register(); | 1554 Simd128Register dst = i.OutputSimd128Register(); |
1555 __ vceq(dst, i.InputSimd128Register(0), i.InputSimd128Register(1)); | 1555 __ vceq(dst, i.InputSimd128Register(0), i.InputSimd128Register(1)); |
1556 __ vmvn(dst, dst); | 1556 __ vmvn(dst, dst); |
1557 break; | 1557 break; |
1558 } | 1558 } |
1559 case kArmInt32x4Splat: { | 1559 case kArmInt32x4Splat: { |
1560 __ vdup(Neon32, i.OutputSimd128Register(), i.InputRegister(0)); | 1560 __ vdup(Neon32, i.OutputSimd128Register(), i.InputRegister(0)); |
1561 break; | 1561 break; |
1562 } | 1562 } |
1563 case kArmInt32x4ExtractLane: { | 1563 case kArmInt32x4ExtractLane: { |
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1600 case kArmInt32x4Min: { | 1600 case kArmInt32x4Min: { |
1601 __ vmin(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1601 __ vmin(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1602 i.InputSimd128Register(1)); | 1602 i.InputSimd128Register(1)); |
1603 break; | 1603 break; |
1604 } | 1604 } |
1605 case kArmInt32x4Max: { | 1605 case kArmInt32x4Max: { |
1606 __ vmax(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1606 __ vmax(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1607 i.InputSimd128Register(1)); | 1607 i.InputSimd128Register(1)); |
1608 break; | 1608 break; |
1609 } | 1609 } |
1610 case kArmInt32x4Eq: { | 1610 case kArmInt32x4Equal: { |
1611 __ vceq(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1611 __ vceq(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1612 i.InputSimd128Register(1)); | 1612 i.InputSimd128Register(1)); |
1613 break; | 1613 break; |
1614 } | 1614 } |
1615 case kArmInt32x4Ne: { | 1615 case kArmInt32x4NotEqual: { |
1616 Simd128Register dst = i.OutputSimd128Register(); | 1616 Simd128Register dst = i.OutputSimd128Register(); |
1617 __ vceq(Neon32, dst, i.InputSimd128Register(0), | 1617 __ vceq(Neon32, dst, i.InputSimd128Register(0), |
1618 i.InputSimd128Register(1)); | 1618 i.InputSimd128Register(1)); |
1619 __ vmvn(dst, dst); | 1619 __ vmvn(dst, dst); |
1620 break; | 1620 break; |
1621 } | 1621 } |
1622 case kArmInt32x4Gt: { | 1622 case kArmInt32x4GreaterThan: { |
1623 __ vcgt(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1623 __ vcgt(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1624 i.InputSimd128Register(1)); | 1624 i.InputSimd128Register(1)); |
1625 break; | 1625 break; |
1626 } | 1626 } |
1627 case kArmInt32x4Ge: { | 1627 case kArmInt32x4GreaterThanOrEqual: { |
1628 Simd128Register dst = i.OutputSimd128Register(); | 1628 Simd128Register dst = i.OutputSimd128Register(); |
1629 __ vcge(NeonS32, dst, i.InputSimd128Register(0), | 1629 __ vcge(NeonS32, dst, i.InputSimd128Register(0), |
1630 i.InputSimd128Register(1)); | 1630 i.InputSimd128Register(1)); |
1631 break; | 1631 break; |
1632 } | 1632 } |
1633 case kArmUint32x4Gt: { | 1633 case kArmUint32x4GreaterThan: { |
1634 __ vcgt(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1634 __ vcgt(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1635 i.InputSimd128Register(1)); | 1635 i.InputSimd128Register(1)); |
1636 break; | 1636 break; |
1637 } | 1637 } |
1638 case kArmUint32x4Ge: { | 1638 case kArmUint32x4GreaterThanOrEqual: { |
1639 Simd128Register dst = i.OutputSimd128Register(); | 1639 Simd128Register dst = i.OutputSimd128Register(); |
1640 __ vcge(NeonU32, dst, i.InputSimd128Register(0), | 1640 __ vcge(NeonU32, dst, i.InputSimd128Register(0), |
1641 i.InputSimd128Register(1)); | 1641 i.InputSimd128Register(1)); |
1642 break; | 1642 break; |
1643 } | 1643 } |
1644 case kArmSimd32x4Select: { | 1644 case kArmSimd32x4Select: { |
1645 // Select is a ternary op, so we need to move one input into the | 1645 // Select is a ternary op, so we need to move one input into the |
1646 // destination. Use vtst to canonicalize the 'boolean' input #0. | 1646 // destination. Use vtst to canonicalize the 'boolean' input #0. |
1647 __ vtst(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1647 __ vtst(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1648 i.InputSimd128Register(0)); | 1648 i.InputSimd128Register(0)); |
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1686 case kArmInt16x8Min: { | 1686 case kArmInt16x8Min: { |
1687 __ vmin(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1687 __ vmin(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1688 i.InputSimd128Register(1)); | 1688 i.InputSimd128Register(1)); |
1689 break; | 1689 break; |
1690 } | 1690 } |
1691 case kArmInt16x8Max: { | 1691 case kArmInt16x8Max: { |
1692 __ vmax(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1692 __ vmax(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1693 i.InputSimd128Register(1)); | 1693 i.InputSimd128Register(1)); |
1694 break; | 1694 break; |
1695 } | 1695 } |
1696 case kArmInt16x8Eq: { | 1696 case kArmInt16x8Equal: { |
1697 __ vceq(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1697 __ vceq(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1698 i.InputSimd128Register(1)); | 1698 i.InputSimd128Register(1)); |
1699 break; | 1699 break; |
1700 } | 1700 } |
1701 case kArmInt16x8Ne: { | 1701 case kArmInt16x8NotEqual: { |
1702 Simd128Register dst = i.OutputSimd128Register(); | 1702 Simd128Register dst = i.OutputSimd128Register(); |
1703 __ vceq(Neon16, dst, i.InputSimd128Register(0), | 1703 __ vceq(Neon16, dst, i.InputSimd128Register(0), |
1704 i.InputSimd128Register(1)); | 1704 i.InputSimd128Register(1)); |
1705 __ vmvn(dst, dst); | 1705 __ vmvn(dst, dst); |
1706 break; | 1706 break; |
1707 } | 1707 } |
1708 case kArmInt16x8Gt: { | 1708 case kArmInt16x8GreaterThan: { |
1709 __ vcgt(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1709 __ vcgt(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1710 i.InputSimd128Register(1)); | 1710 i.InputSimd128Register(1)); |
1711 break; | 1711 break; |
1712 } | 1712 } |
1713 case kArmInt16x8Ge: { | 1713 case kArmInt16x8GreaterThanOrEqual: { |
1714 Simd128Register dst = i.OutputSimd128Register(); | 1714 Simd128Register dst = i.OutputSimd128Register(); |
1715 __ vcge(NeonS16, dst, i.InputSimd128Register(0), | 1715 __ vcge(NeonS16, dst, i.InputSimd128Register(0), |
1716 i.InputSimd128Register(1)); | 1716 i.InputSimd128Register(1)); |
1717 break; | 1717 break; |
1718 } | 1718 } |
1719 case kArmUint16x8Gt: { | 1719 case kArmUint16x8GreaterThan: { |
1720 __ vcgt(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1720 __ vcgt(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1721 i.InputSimd128Register(1)); | 1721 i.InputSimd128Register(1)); |
1722 break; | 1722 break; |
1723 } | 1723 } |
1724 case kArmUint16x8Ge: { | 1724 case kArmUint16x8GreaterThanOrEqual: { |
1725 Simd128Register dst = i.OutputSimd128Register(); | 1725 Simd128Register dst = i.OutputSimd128Register(); |
1726 __ vcge(NeonU16, dst, i.InputSimd128Register(0), | 1726 __ vcge(NeonU16, dst, i.InputSimd128Register(0), |
1727 i.InputSimd128Register(1)); | 1727 i.InputSimd128Register(1)); |
1728 break; | 1728 break; |
1729 } | 1729 } |
1730 case kArmInt8x16Splat: { | 1730 case kArmInt8x16Splat: { |
1731 __ vdup(Neon8, i.OutputSimd128Register(), i.InputRegister(0)); | 1731 __ vdup(Neon8, i.OutputSimd128Register(), i.InputRegister(0)); |
1732 break; | 1732 break; |
1733 } | 1733 } |
1734 case kArmInt8x16ExtractLane: { | 1734 case kArmInt8x16ExtractLane: { |
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1763 case kArmInt8x16Min: { | 1763 case kArmInt8x16Min: { |
1764 __ vmin(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1764 __ vmin(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1765 i.InputSimd128Register(1)); | 1765 i.InputSimd128Register(1)); |
1766 break; | 1766 break; |
1767 } | 1767 } |
1768 case kArmInt8x16Max: { | 1768 case kArmInt8x16Max: { |
1769 __ vmax(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1769 __ vmax(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1770 i.InputSimd128Register(1)); | 1770 i.InputSimd128Register(1)); |
1771 break; | 1771 break; |
1772 } | 1772 } |
1773 case kArmInt8x16Eq: { | 1773 case kArmInt8x16Equal: { |
1774 __ vceq(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1774 __ vceq(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1775 i.InputSimd128Register(1)); | 1775 i.InputSimd128Register(1)); |
1776 break; | 1776 break; |
1777 } | 1777 } |
1778 case kArmInt8x16Ne: { | 1778 case kArmInt8x16NotEqual: { |
1779 Simd128Register dst = i.OutputSimd128Register(); | 1779 Simd128Register dst = i.OutputSimd128Register(); |
1780 __ vceq(Neon8, dst, i.InputSimd128Register(0), i.InputSimd128Register(1)); | 1780 __ vceq(Neon8, dst, i.InputSimd128Register(0), i.InputSimd128Register(1)); |
1781 __ vmvn(dst, dst); | 1781 __ vmvn(dst, dst); |
1782 break; | 1782 break; |
1783 } | 1783 } |
1784 case kArmInt8x16Gt: { | 1784 case kArmInt8x16GreaterThan: { |
1785 __ vcgt(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1785 __ vcgt(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1786 i.InputSimd128Register(1)); | 1786 i.InputSimd128Register(1)); |
1787 break; | 1787 break; |
1788 } | 1788 } |
1789 case kArmInt8x16Ge: { | 1789 case kArmInt8x16GreaterThanOrEqual: { |
1790 Simd128Register dst = i.OutputSimd128Register(); | 1790 Simd128Register dst = i.OutputSimd128Register(); |
1791 __ vcge(NeonS8, dst, i.InputSimd128Register(0), | 1791 __ vcge(NeonS8, dst, i.InputSimd128Register(0), |
1792 i.InputSimd128Register(1)); | 1792 i.InputSimd128Register(1)); |
1793 break; | 1793 break; |
1794 } | 1794 } |
1795 case kArmUint8x16Gt: { | 1795 case kArmUint8x16GreaterThan: { |
1796 __ vcgt(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1796 __ vcgt(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1797 i.InputSimd128Register(1)); | 1797 i.InputSimd128Register(1)); |
1798 break; | 1798 break; |
1799 } | 1799 } |
1800 case kArmUint8x16Ge: { | 1800 case kArmUint8x16GreaterThanOrEqual: { |
1801 Simd128Register dst = i.OutputSimd128Register(); | 1801 Simd128Register dst = i.OutputSimd128Register(); |
1802 __ vcge(NeonU8, dst, i.InputSimd128Register(0), | 1802 __ vcge(NeonU8, dst, i.InputSimd128Register(0), |
1803 i.InputSimd128Register(1)); | 1803 i.InputSimd128Register(1)); |
1804 break; | 1804 break; |
1805 } | 1805 } |
1806 case kCheckedLoadInt8: | 1806 case kCheckedLoadInt8: |
1807 ASSEMBLE_CHECKED_LOAD_INTEGER(ldrsb); | 1807 ASSEMBLE_CHECKED_LOAD_INTEGER(ldrsb); |
1808 break; | 1808 break; |
1809 case kCheckedLoadUint8: | 1809 case kCheckedLoadUint8: |
1810 ASSEMBLE_CHECKED_LOAD_INTEGER(ldrb); | 1810 ASSEMBLE_CHECKED_LOAD_INTEGER(ldrb); |
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2461 padding_size -= v8::internal::Assembler::kInstrSize; | 2461 padding_size -= v8::internal::Assembler::kInstrSize; |
2462 } | 2462 } |
2463 } | 2463 } |
2464 } | 2464 } |
2465 | 2465 |
2466 #undef __ | 2466 #undef __ |
2467 | 2467 |
2468 } // namespace compiler | 2468 } // namespace compiler |
2469 } // namespace internal | 2469 } // namespace internal |
2470 } // namespace v8 | 2470 } // namespace v8 |
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