[turbofan] Correct regalloc blocked register behavior

src/compiler/register-allocator.cc

Index: src/compiler/register-allocator.cc
diff --git a/src/compiler/register-allocator.cc b/src/compiler/register-allocator.cc
index 5515843612dd12759c846a7601f4e66fc806a8e7..541718cf8913b5debefca2c5f2da1c46694f0c0a 100644
--- a/src/compiler/register-allocator.cc
+++ b/src/compiler/register-allocator.cc
@@ -3278,8 +3278,32 @@ void LinearScanAllocator::AllocateBlockedReg(LiveRange* current) {
                                                    register_use->pos())) {
       SpillBetween(current, current->Start(), register_use->pos());
     } else {
-      SetLiveRangeAssignedRegister(current, reg);
-      SplitAndSpillIntersecting(current);
+      // We can't spill up to the first register use, because there is no gap
+      // where the fill before the register use may happen. This happens when
+      // there is high register pressure, we are at the beginning of an
+      // instruction, we are the input to that instruction, and we can't hold
+      // on to the register past the instruction (we likely lose due to an
+      // output or a temp).
+      // We give the `reg` register to this range, but then we need to spill
+      // until the next register use, if any.
+      LifetimePosition after_this_reg_use = register_use->pos().NextFullStart();
+      if (after_this_reg_use >= current->End()) {
+        // The range ends at this instruction, since the end is at or before
+        // the next gap. It should follow that there is no other use either.
+        DCHECK_NULL(register_use->next());
+        SetLiveRangeAssignedRegister(current, reg);
+      } else {
+        const UsePosition* next_reg_pos = register_use->next();
+        for (; next_reg_pos != nullptr; next_reg_pos = next_reg_pos->next()) {
+          if (next_reg_pos->type() == UsePositionType::kRequiresRegister) break;
+        }
+        SetLiveRangeAssignedRegister(current, reg);
+        if (next_reg_pos == nullptr) {
+          SpillAfter(current, after_this_reg_use);
+        } else {
+          SpillBetween(current, after_this_reg_use, next_reg_pos->pos());
+        }
+      }
     }
     return;
   }