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Side by Side Diff: src/compiler/arm/instruction-selector-arm.cc

Issue 2649703002: [Atomics] Make Atomics.compareExchange a builtin using TF (Closed)
Patch Set: dmb Created 3 years, 9 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/base/adapters.h" 5 #include "src/base/adapters.h"
6 #include "src/base/bits.h" 6 #include "src/base/bits.h"
7 #include "src/compiler/instruction-selector-impl.h" 7 #include "src/compiler/instruction-selector-impl.h"
8 #include "src/compiler/node-matchers.h" 8 #include "src/compiler/node-matchers.h"
9 #include "src/compiler/node-properties.h" 9 #include "src/compiler/node-properties.h"
10 10
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2210 inputs[input_count++] = g.UseUniqueRegister(index); 2210 inputs[input_count++] = g.UseUniqueRegister(index);
2211 inputs[input_count++] = g.UseUniqueRegister(value); 2211 inputs[input_count++] = g.UseUniqueRegister(value);
2212 InstructionOperand outputs[1]; 2212 InstructionOperand outputs[1];
2213 outputs[0] = g.UseUniqueRegister(node); 2213 outputs[0] = g.UseUniqueRegister(node);
2214 InstructionOperand temp[1]; 2214 InstructionOperand temp[1];
2215 temp[0] = g.TempRegister(); 2215 temp[0] = g.TempRegister();
2216 InstructionCode code = opcode | AddressingModeField::encode(addressing_mode); 2216 InstructionCode code = opcode | AddressingModeField::encode(addressing_mode);
2217 Emit(code, 1, outputs, input_count, inputs, 1, temp); 2217 Emit(code, 1, outputs, input_count, inputs, 1, temp);
2218 } 2218 }
2219 2219
2220 void InstructionSelector::VisitAtomicCompareExchange(Node* node) {
2221 ArmOperandGenerator g(this);
2222 Node* base = node->InputAt(0);
2223 Node* index = node->InputAt(1);
2224 Node* old_value = node->InputAt(2);
2225 Node* new_value = node->InputAt(3);
2226 ArchOpcode opcode = kArchNop;
2227 MachineType type = AtomicCompareExchangeRepresentationOf(node->op());
2228 if (type == MachineType::Int8()) {
2229 opcode = kAtomicCompareExchangeInt8;
2230 } else if (type == MachineType::Uint8()) {
2231 opcode = kAtomicCompareExchangeUint8;
2232 } else if (type == MachineType::Int16()) {
2233 opcode = kAtomicCompareExchangeInt16;
2234 } else if (type == MachineType::Uint16()) {
2235 opcode = kAtomicCompareExchangeUint16;
2236 } else if (type == MachineType::Int32() || type == MachineType::Uint32()) {
2237 opcode = kAtomicCompareExchangeWord32;
2238 } else {
2239 UNREACHABLE();
2240 return;
2241 }
2242
2243 AddressingMode addressing_mode = kMode_Offset_RR;
2244 InstructionOperand inputs[4];
2245 size_t input_count = 0;
2246 inputs[input_count++] = g.UseUniqueRegister(base);
2247 inputs[input_count++] = g.UseUniqueRegister(index);
2248 inputs[input_count++] = g.UseUniqueRegister(old_value);
2249 inputs[input_count++] = g.UseUniqueRegister(new_value);
2250 InstructionOperand outputs[1];
2251 outputs[0] = g.UseUniqueRegister(node);
2252 InstructionOperand temp[2];
2253 temp[0] = g.TempRegister();
2254 temp[1] = g.TempRegister();
2255 InstructionCode code = opcode | AddressingModeField::encode(addressing_mode);
2256 Emit(code, 1, outputs, input_count, inputs, 2, temp);
2257 }
2258
2220 #define SIMD_TYPE_LIST(V) \ 2259 #define SIMD_TYPE_LIST(V) \
2221 V(Float32x4) \ 2260 V(Float32x4) \
2222 V(Int32x4) \ 2261 V(Int32x4) \
2223 V(Int16x8) \ 2262 V(Int16x8) \
2224 V(Int8x16) 2263 V(Int8x16)
2225 2264
2226 #define SIMD_FORMAT_LIST(V) \ 2265 #define SIMD_FORMAT_LIST(V) \
2227 V(32x4) \ 2266 V(32x4) \
2228 V(16x8) \ 2267 V(16x8) \
2229 V(8x16) 2268 V(8x16)
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2403 Vector<MachineType> req_aligned = Vector<MachineType>::New(2); 2442 Vector<MachineType> req_aligned = Vector<MachineType>::New(2);
2404 req_aligned[0] = MachineType::Float32(); 2443 req_aligned[0] = MachineType::Float32();
2405 req_aligned[1] = MachineType::Float64(); 2444 req_aligned[1] = MachineType::Float64();
2406 return MachineOperatorBuilder::AlignmentRequirements:: 2445 return MachineOperatorBuilder::AlignmentRequirements::
2407 SomeUnalignedAccessUnsupported(req_aligned, req_aligned); 2446 SomeUnalignedAccessUnsupported(req_aligned, req_aligned);
2408 } 2447 }
2409 2448
2410 } // namespace compiler 2449 } // namespace compiler
2411 } // namespace internal 2450 } // namespace internal
2412 } // namespace v8 2451 } // namespace v8
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