Adds double load and store to arm64.

runtime/vm/disassembler_arm64.cc

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/disassembler.h"
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_ARM64.
 #if defined(TARGET_ARCH_ARM64)
 #include "platform/assert.h"
 
@@ skipping 294 matching lines @@
 int ARM64Decoder::FormatVRegister(Instr* instr, const char* format) {
   ASSERT(format[0] == 'v');
   if (format[1] == 'd') {
     int reg = instr->VdField();
     PrintVRegister(reg);
     return 2;
   } else if (format[1] == 'n') {
     int reg = instr->VnField();
     PrintVRegister(reg);
     return 2;
+  } else if (format[1] == 't') {
+    int reg = instr->VtField();
+    PrintVRegister(reg);
+    return 2;
   }
   UNREACHABLE();
   return -1;
 }
 
 
 // FormatOption takes a formatting string and interprets it based on
 // the current instructions. The format string points to the first
 // character of the option string (the option escape has already been
 // consumed by the caller.)  FormatOption returns the number of
@@ skipping 222 matching lines @@
       Format(instr, "movk'sf 'rd, 'imm16 'hw");
       break;
     default:
       Unknown(instr);
       break;
   }
 }
 
 
 void ARM64Decoder::DecodeLoadStoreReg(Instr* instr) {
-  if (instr->Bits(25, 2) != 0) {
+  if (instr->Bit(23) != 0) {
+    // 128-bit ldr/str.
     Unknown(instr);
-    return;
   }
-  if (instr->Bit(22) == 1) {
-    Format(instr, "ldr'sz 'rt, 'memop");
+  if (instr->Bit(26) == 1) {
+    if (instr->Bits(30, 2) != 3) {
+      // Only 64-bit double variant supported.
+      Unknown(instr);
+    }
+    // SIMD or FP src/dst.
+    if (instr->Bit(22) == 1) {
+      Format(instr, "fldrd 'vt, 'memop");
+    } else {
+      Format(instr, "fstrd 'vt, 'memop");
+    }
   } else {
-    Format(instr, "str'sz 'rt, 'memop");
+    // Integer src/dst.
+    if (instr->Bit(22) == 1) {
+      Format(instr, "ldr'sz 'rt, 'memop");
+    } else {
+      Format(instr, "str'sz 'rt, 'memop");
+    }
   }
 }
 
 
 void ARM64Decoder::DecodeLoadRegLiteral(Instr* instr) {
   if ((instr->Bit(31) != 0) || (instr->Bit(29) != 0) ||
       (instr->Bits(24, 3) != 0)) {
     Unknown(instr);
   }
   if (instr->Bit(30)) {
@@ skipping 459 matching lines @@
                                   human_buffer,
                                   sizeof(human_buffer),
                                   pc);
     pc += instruction_length;
   }
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM