Adds double load and store to arm64.

runtime/vm/constants_arm64.h

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_CONSTANTS_ARM64_H_
 #define VM_CONSTANTS_ARM64_H_
 
 #include "platform/assert.h"
 
 namespace dart {
@@ skipping 304 matching lines @@
 
 // C3.2.7
 enum UnconditionalBranchRegOp {
   UnconditionalBranchRegMask = 0xfe000000,
   UnconditionalBranchRegFixed = CompareBranchFixed | B31 | B30 | B25,
   BR = UnconditionalBranchRegFixed | B20 | B19 | B18 | B17 | B16,
   BLR = BR | B21,
   RET = BR | B22,
 };
 
-enum LoadStoreRegOp {
-  LoadStoreRegMask = 0x3a000000,
-  LoadStoreRegFixed = LoadStoreFixed | B29 | B28,
-  STR = LoadStoreRegFixed,
-  LDR = LoadStoreRegFixed | B22,
-};
-
 // C3.3.5
 enum LoadRegLiteralOp {
   LoadRegLiteralMask = 0x3b000000,
   LoadRegLiteralFixed = LoadStoreFixed | B28,
   LDRpc = LoadRegLiteralFixed,
 };
 
+// C3.3.7-10
+enum LoadStoreRegOp {
+  LoadStoreRegMask = 0x3a000000,
+  LoadStoreRegFixed = LoadStoreFixed | B29 | B28,
+  STR = LoadStoreRegFixed,
+  LDR = LoadStoreRegFixed | B22,
+  FSTR = STR | B26,
+  FLDR = LDR | B26,
+};
+
 // C3.4.1
 enum AddSubImmOp {
   AddSubImmMask = 0x1f000000,
   AddSubImmFixed = DPImmediateFixed | B24,
   ADDI = AddSubImmFixed,
   SUBI = AddSubImmFixed | B30,
 };
 
 // C3.4.4
 enum LogicalImmOp {
@@ skipping 168 matching lines @@
   kRmShift = 16,
   kRmBits = 5,
   kRtShift = 0,
   kRtBits = 5,
 
   // V Registers.
   kVdShift = 0,
   kVdBits = 5,
   kVnShift = 5,
   kVnBits = 5,
+  kVtShift = 0,
+  kVtBits = 5,
 
   // Immediates.
   kImm3Shift = 10,
   kImm3Bits = 3,
   kImm6Shift = 10,
   kImm6Bits = 6,
   kImm8Shift = 13,
   kImm8Bits = 8,
   kImm9Shift = 12,
   kImm9Bits = 9,
@@ skipping 148 matching lines @@
                                         Bits(kRaShift, kRaBits)); }
   inline Register RmField() const { return static_cast<Register>(
                                         Bits(kRmShift, kRmBits)); }
   inline Register RtField() const { return static_cast<Register>(
                                         Bits(kRtShift, kRtBits)); }
 
   inline VRegister VdField() const { return static_cast<VRegister>(
                                         Bits(kVdShift, kVdBits)); }
   inline VRegister VnField() const { return static_cast<VRegister>(
                                         Bits(kVnShift, kVnBits)); }
+  inline VRegister VtField() const { return static_cast<VRegister>(
+                                        Bits(kVtShift, kVtBits)); }
 
   // Immediates
   inline int Imm3Field() const { return Bits(kImm3Shift, kImm3Bits); }
   inline int Imm6Field() const { return Bits(kImm6Shift, kImm6Bits); }
   inline int Imm8Field() const { return Bits(kImm8Shift, kImm8Bits); }
   inline int Imm9Field() const { return Bits(kImm9Shift, kImm9Bits); }
   // Sign-extended Imm9Field()
   inline int64_t SImm9Field() const {
       return (static_cast<int32_t>(Imm9Field()) << 23) >> 23; }
 
@@ skipping 156 matching lines @@
   static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); }
 
  private:
   DISALLOW_ALLOCATION();
   DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
 };
 
 }  // namespace dart
 
 #endif  // VM_CONSTANTS_ARM64_H_