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Issue 2649113007: s390: TF Codegen Optimization (Closed)
Patch Set: remove 2 unnecessary unreachables Created 3 years, 10 months ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions 5 // modification, are permitted provided that the following conditions
6 // are met: 6 // are met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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1885 // Multiply Halfword Immediate (64) 1885 // Multiply Halfword Immediate (64)
1886 void Assembler::mghi(Register r1, const Operand& opnd) { 1886 void Assembler::mghi(Register r1, const Operand& opnd) {
1887 ri_form(MGHI, r1, opnd); 1887 ri_form(MGHI, r1, opnd);
1888 } 1888 }
1889 1889
1890 // Multiply Single Register-Storage (64) 1890 // Multiply Single Register-Storage (64)
1891 void Assembler::msg(Register r1, const MemOperand& opnd) { 1891 void Assembler::msg(Register r1, const MemOperand& opnd) {
1892 rxy_form(MSG, r1, opnd.rx(), opnd.rb(), opnd.offset()); 1892 rxy_form(MSG, r1, opnd.rx(), opnd.rb(), opnd.offset());
1893 } 1893 }
1894 1894
1895 void Assembler::msgf(Register r1, const MemOperand& opnd) {
1896 rxy_form(MSGF, r1, opnd.rx(), opnd.rb(), opnd.offset());
1897 }
1898
1895 // -------------------------- 1899 // --------------------------
1896 // 32-bit Divide Instructions 1900 // 32-bit Divide Instructions
1897 // -------------------------- 1901 // --------------------------
1898 // Divide Register-Storage (32<-64) 1902 // Divide Register-Storage (32<-64)
1899 void Assembler::d(Register r1, const MemOperand& opnd) { 1903 void Assembler::d(Register r1, const MemOperand& opnd) {
1900 rx_form(D, r1, opnd.rx(), opnd.rb(), opnd.offset()); 1904 rx_form(D, r1, opnd.rx(), opnd.rb(), opnd.offset());
1901 } 1905 }
1902 1906
1903 // Divide Logical Register-Storage (32<-64) 1907 // Divide Logical Register-Storage (32<-64)
1904 void Assembler::dl(Register r1, const MemOperand& opnd) { 1908 void Assembler::dl(Register r1, const MemOperand& opnd) {
1905 rx_form(DL, r1, opnd.rx(), opnd.rb(), opnd.offset()); 1909 rxy_form(DL, r1, opnd.rx(), opnd.rb(), opnd.offset());
1910 }
1911
1912 void Assembler::dsg(Register r1, const MemOperand& opnd) {
1913 rxy_form(DSG, r1, opnd.rx(), opnd.rb(), opnd.offset());
1914 }
1915
1916 void Assembler::dsgf(Register r1, const MemOperand& opnd) {
1917 rxy_form(DSGF, r1, opnd.rx(), opnd.rb(), opnd.offset());
1906 } 1918 }
1907 1919
1908 // -------------------- 1920 // --------------------
1909 // Bitwise Instructions 1921 // Bitwise Instructions
1910 // -------------------- 1922 // --------------------
1911 // AND Register-Storage (32) 1923 // AND Register-Storage (32)
1912 void Assembler::n(Register r1, const MemOperand& opnd) { 1924 void Assembler::n(Register r1, const MemOperand& opnd) {
1913 rx_form(N, r1, opnd.rx(), opnd.rb(), opnd.offset()); 1925 rx_form(N, r1, opnd.rx(), opnd.rb(), opnd.offset());
1914 } 1926 }
1915 1927
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2628 SKIP_ICACHE_FLUSH); 2640 SKIP_ICACHE_FLUSH);
2629 } 2641 }
2630 2642
2631 reloc_info_writer.Write(&rinfo); 2643 reloc_info_writer.Write(&rinfo);
2632 } 2644 }
2633 } 2645 }
2634 2646
2635 } // namespace internal 2647 } // namespace internal
2636 } // namespace v8 2648 } // namespace v8
2637 #endif // V8_TARGET_ARCH_S390 2649 #endif // V8_TARGET_ARCH_S390
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