Arm64: Ensure that csp is always aligned to 16 byte values even if jssp is not.

src/arm64/cpu-arm64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 // CPU specific code for arm independent of OS goes here.
 
 #include "v8.h"
 
 #if V8_TARGET_ARCH_ARM64
 
 #include "arm64/cpu-arm64.h"
 #include "arm64/utils-arm64.h"
 
 namespace v8 {
 namespace internal {
 
 #ifdef DEBUG
 bool CpuFeatures::initialized_ = false;
 #endif
 unsigned CpuFeatures::supported_ = 0;
+unsigned CpuFeatures::found_by_runtime_probing_only_ = 0;
 unsigned CpuFeatures::cross_compile_ = 0;
 
 
 class CacheLineSizes {
  public:
   CacheLineSizes() {
 #ifdef USE_SIMULATOR
     cache_type_register_ = 0;
 #else
     // Copy the content of the cache type register to a core register.
@@ skipping 88 matching lines @@
       [end]   "r"  (end)
     // This code does not write to memory but without the dependency gcc might
     // move this code before the code is generated.
     : "cc", "memory"
   );  // NOLINT
 #endif
 }
 
 
 void CpuFeatures::Probe(bool serializer_enabled) {
-  // AArch64 has no configuration options, no further probing is required.
-  supported_ = 0;
+  ASSERT(supported_ == 0);
+
+  if (serializer_enabled && FLAG_enable_always_align_csp) {
+    // Always align csp in snapshot code - this is safe and ensures that csp
+    // will always be aligned if it is enabled by probing at runtime.
+    supported_ |= static_cast<uint64_t>(1) << ALWAYS_ALIGN_CSP;
+  }
+
+  if (!serializer_enabled) {
+    CPU cpu;
+    // Always align csp on Nvidia cores.
+    if (cpu.implementer() == CPU::NVIDIA && FLAG_enable_always_align_csp) {
+      found_by_runtime_probing_only_ |=
+          static_cast<uint64_t>(1) << ALWAYS_ALIGN_CSP;
+    }
+
+    supported_ |= found_by_runtime_probing_only_;
+  }
 
 #ifdef DEBUG
   initialized_ = true;
 #endif
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_ARM64