Index: src/compiler/s390/instruction-selector-s390.cc |
diff --git a/src/compiler/s390/instruction-selector-s390.cc b/src/compiler/s390/instruction-selector-s390.cc |
index a1afc79ae712b1798bee5ab8512293c28f6fe7a8..b469415d2e98b5e7d10ec6de33159202f56cf956 100644 |
--- a/src/compiler/s390/instruction-selector-s390.cc |
+++ b/src/compiler/s390/instruction-selector-s390.cc |
@@ -544,6 +544,7 @@ void InstructionSelector::VisitCheckedStore(Node* node) { |
g.UseOperand(length, kUint32Imm), g.UseRegister(value)); |
} |
+#if 0 |
static inline bool IsContiguousMask32(uint32_t value, int* mb, int* me) { |
int mask_width = base::bits::CountPopulation32(value); |
int mask_msb = base::bits::CountLeadingZeros32(value); |
@@ -554,6 +555,7 @@ static inline bool IsContiguousMask32(uint32_t value, int* mb, int* me) { |
*me = mask_lsb; |
return true; |
} |
+#endif |
#if V8_TARGET_ARCH_S390X |
static inline bool IsContiguousMask64(uint64_t value, int* mb, int* me) { |
@@ -569,36 +571,6 @@ static inline bool IsContiguousMask64(uint64_t value, int* mb, int* me) { |
#endif |
void InstructionSelector::VisitWord32And(Node* node) { |
- S390OperandGenerator g(this); |
- Int32BinopMatcher m(node); |
- int mb = 0; |
- int me = 0; |
- if (m.right().HasValue() && IsContiguousMask32(m.right().Value(), &mb, &me)) { |
- int sh = 0; |
- Node* left = m.left().node(); |
- if ((m.left().IsWord32Shr() || m.left().IsWord32Shl()) && |
- CanCover(node, left)) { |
- Int32BinopMatcher mleft(m.left().node()); |
- if (mleft.right().IsInRange(0, 31)) { |
- left = mleft.left().node(); |
- sh = mleft.right().Value(); |
- if (m.left().IsWord32Shr()) { |
- // Adjust the mask such that it doesn't include any rotated bits. |
- if (mb > 31 - sh) mb = 31 - sh; |
- sh = (32 - sh) & 0x1f; |
- } else { |
- // Adjust the mask such that it doesn't include any rotated bits. |
- if (me < sh) me = sh; |
- } |
- } |
- } |
- if (mb >= me) { |
- Emit(kS390_RotLeftAndMask32, g.DefineAsRegister(node), |
- g.UseRegister(left), g.TempImmediate(sh), g.TempImmediate(mb), |
- g.TempImmediate(me)); |
- return; |
- } |
- } |
VisitBinop<Int32BinopMatcher>(this, node, kS390_And32, kUint32Imm); |
} |
@@ -690,25 +662,6 @@ void InstructionSelector::VisitWord64Xor(Node* node) { |
#endif |
void InstructionSelector::VisitWord32Shl(Node* node) { |
- S390OperandGenerator g(this); |
- Int32BinopMatcher m(node); |
- if (m.left().IsWord32And() && m.right().IsInRange(0, 31)) { |
- Int32BinopMatcher mleft(m.left().node()); |
- int sh = m.right().Value(); |
- int mb; |
- int me; |
- if (mleft.right().HasValue() && |
- IsContiguousMask32(mleft.right().Value() << sh, &mb, &me)) { |
- // Adjust the mask such that it doesn't include any rotated bits. |
- if (me < sh) me = sh; |
- if (mb >= me) { |
- Emit(kS390_RotLeftAndMask32, g.DefineAsRegister(node), |
- g.UseRegister(mleft.left().node()), g.TempImmediate(sh), |
- g.TempImmediate(mb), g.TempImmediate(me)); |
- return; |
- } |
- } |
- } |
VisitRRO(this, kS390_ShiftLeft32, node, kShift32Imm); |
} |
@@ -757,26 +710,6 @@ void InstructionSelector::VisitWord64Shl(Node* node) { |
#endif |
void InstructionSelector::VisitWord32Shr(Node* node) { |
- S390OperandGenerator g(this); |
- Int32BinopMatcher m(node); |
- if (m.left().IsWord32And() && m.right().IsInRange(0, 31)) { |
- Int32BinopMatcher mleft(m.left().node()); |
- int sh = m.right().Value(); |
- int mb; |
- int me; |
- if (mleft.right().HasValue() && |
- IsContiguousMask32((uint32_t)(mleft.right().Value()) >> sh, &mb, &me)) { |
- // Adjust the mask such that it doesn't include any rotated bits. |
- if (mb > 31 - sh) mb = 31 - sh; |
- sh = (32 - sh) & 0x1f; |
- if (mb >= me) { |
- Emit(kS390_RotLeftAndMask32, g.DefineAsRegister(node), |
- g.UseRegister(mleft.left().node()), g.TempImmediate(sh), |
- g.TempImmediate(mb), g.TempImmediate(me)); |
- return; |
- } |
- } |
- } |
VisitRRO(this, kS390_ShiftRight32, node, kShift32Imm); |
} |