[Turbofan] Add other integer SIMD types, add more integer ops.

src/compiler/arm/instruction-selector-arm.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/base/adapters.h"
 #include "src/base/bits.h"
 #include "src/compiler/instruction-selector-impl.h"
 #include "src/compiler/node-matchers.h"
 #include "src/compiler/node-properties.h"
 
@@ skipping 2268 matching lines @@
   AddressingMode addressing_mode = kMode_Offset_RR;
   InstructionOperand inputs[4];
   size_t input_count = 0;
   inputs[input_count++] = g.UseUniqueRegister(base);
   inputs[input_count++] = g.UseUniqueRegister(index);
   inputs[input_count++] = g.UseUniqueRegister(value);
   InstructionCode code = opcode | AddressingModeField::encode(addressing_mode);
   Emit(code, 0, nullptr, input_count, inputs);
 }
 
+// TODO(bbudge) Macro-ize SIMD methods.
 void InstructionSelector::VisitCreateFloat32x4(Node* node) {
   ArmOperandGenerator g(this);
   Emit(kArmFloat32x4Splat, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
 }
 
 void InstructionSelector::VisitFloat32x4ExtractLane(Node* node) {
   ArmOperandGenerator g(this);
   int32_t lane = OpParameter<int32_t>(node);
   Emit(kArmFloat32x4ExtractLane, g.DefineAsRegister(node),
        g.UseRegister(node->InputAt(0)), g.UseImmediate(lane));
@@ skipping 80 matching lines @@
   Emit(kArmInt32x4FromFloat32x4, g.DefineAsRegister(node),
        g.UseRegister(node->InputAt(0)));
 }
 
 void InstructionSelector::VisitUint32x4FromFloat32x4(Node* node) {
   ArmOperandGenerator g(this);
   Emit(kArmUint32x4FromFloat32x4, g.DefineAsRegister(node),
        g.UseRegister(node->InputAt(0)));
 }
 
+void InstructionSelector::VisitInt32x4Neg(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmInt32x4Neg, g.DefineAsRegister(node),
+       g.UseRegister(node->InputAt(0)));
+}
+
 void InstructionSelector::VisitInt32x4Add(Node* node) {
   ArmOperandGenerator g(this);
   Emit(kArmInt32x4Add, g.DefineAsRegister(node),
        g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
 }
 
 void InstructionSelector::VisitInt32x4Sub(Node* node) {
   ArmOperandGenerator g(this);
   Emit(kArmInt32x4Sub, g.DefineAsRegister(node),
        g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
 }
 
+void InstructionSelector::VisitInt32x4Mul(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmInt32x4Mul, g.DefineAsRegister(node),
+       g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
+}
+
+void InstructionSelector::VisitInt32x4Min(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmInt32x4Min, g.DefineAsRegister(node),
+       g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
+}
+
+void InstructionSelector::VisitInt32x4Max(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmInt32x4Max, g.DefineAsRegister(node),
+       g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
+}
+
 void InstructionSelector::VisitInt32x4Equal(Node* node) {
   ArmOperandGenerator g(this);
   Emit(kArmInt32x4Eq, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
        g.UseRegister(node->InputAt(1)));
 }
 
 void InstructionSelector::VisitInt32x4NotEqual(Node* node) {
   ArmOperandGenerator g(this);
   Emit(kArmInt32x4Ne, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
        g.UseRegister(node->InputAt(1)));
 }
 
+void InstructionSelector::VisitInt32x4GreaterThan(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmInt32x4Gt, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
+       g.UseRegister(node->InputAt(1)));
+}
+
+void InstructionSelector::VisitInt32x4GreaterThanOrEqual(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmInt32x4Ge, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
+       g.UseRegister(node->InputAt(1)));
+}
+
+void InstructionSelector::VisitUint32x4GreaterThan(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmUint32x4Gt, g.DefineAsRegister(node),
+       g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
+}
+
+void InstructionSelector::VisitUint32x4GreaterThanOrEqual(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmUint32x4Ge, g.DefineAsRegister(node),
+       g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
+}
+
 void InstructionSelector::VisitSimd32x4Select(Node* node) {
   ArmOperandGenerator g(this);
   Emit(kArmSimd32x4Select, g.DefineAsRegister(node),
        g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)),
        g.UseRegister(node->InputAt(2)));
 }
 
+void InstructionSelector::VisitCreateInt16x8(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmInt16x8Splat, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
+}
+
+void InstructionSelector::VisitInt16x8ExtractLane(Node* node) {
+  ArmOperandGenerator g(this);
+  int32_t lane = OpParameter<int32_t>(node);
+  Emit(kArmInt16x8ExtractLane, g.DefineAsRegister(node),
+       g.UseRegister(node->InputAt(0)), g.UseImmediate(lane));
+}
+
+void InstructionSelector::VisitInt16x8ReplaceLane(Node* node) {
+  ArmOperandGenerator g(this);
+  int32_t lane = OpParameter<int32_t>(node);
+  Emit(kArmInt16x8ReplaceLane, g.DefineAsRegister(node),
+       g.UseRegister(node->InputAt(0)), g.UseImmediate(lane),
+       g.Use(node->InputAt(1)));
+}
+
+void InstructionSelector::VisitInt16x8Neg(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmInt16x8Neg, g.DefineAsRegister(node),
+       g.UseRegister(node->InputAt(0)));
+}
+
+void InstructionSelector::VisitInt16x8Add(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmInt16x8Add, g.DefineAsRegister(node),
+       g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
+}
+
+void InstructionSelector::VisitInt16x8Sub(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmInt16x8Sub, g.DefineAsRegister(node),
+       g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
+}
+
+void InstructionSelector::VisitInt16x8Mul(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmInt16x8Mul, g.DefineAsRegister(node),
+       g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
+}
+
+void InstructionSelector::VisitInt16x8Min(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmInt16x8Min, g.DefineAsRegister(node),
+       g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
+}
+
+void InstructionSelector::VisitInt16x8Max(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmInt16x8Max, g.DefineAsRegister(node),
+       g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
+}
+
+void InstructionSelector::VisitInt16x8Equal(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmInt16x8Eq, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
+       g.UseRegister(node->InputAt(1)));
+}
+
+void InstructionSelector::VisitInt16x8NotEqual(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmInt16x8Ne, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
+       g.UseRegister(node->InputAt(1)));
+}
+
+void InstructionSelector::VisitInt16x8GreaterThan(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmInt16x8Gt, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
+       g.UseRegister(node->InputAt(1)));
+}
+
+void InstructionSelector::VisitInt16x8GreaterThanOrEqual(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmInt16x8Ge, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
+       g.UseRegister(node->InputAt(1)));
+}
+
+void InstructionSelector::VisitUint16x8GreaterThan(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmUint16x8Gt, g.DefineAsRegister(node),
+       g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
+}
+
+void InstructionSelector::VisitUint16x8GreaterThanOrEqual(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmUint16x8Ge, g.DefineAsRegister(node),
+       g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
+}
+
+void InstructionSelector::VisitCreateInt8x16(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmInt8x16Splat, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
+}
+
+void InstructionSelector::VisitInt8x16ExtractLane(Node* node) {
+  ArmOperandGenerator g(this);
+  int32_t lane = OpParameter<int32_t>(node);
+  Emit(kArmInt8x16ExtractLane, g.DefineAsRegister(node),
+       g.UseRegister(node->InputAt(0)), g.UseImmediate(lane));
+}
+
+void InstructionSelector::VisitInt8x16ReplaceLane(Node* node) {
+  ArmOperandGenerator g(this);
+  int32_t lane = OpParameter<int32_t>(node);
+  Emit(kArmInt8x16ReplaceLane, g.DefineAsRegister(node),
+       g.UseRegister(node->InputAt(0)), g.UseImmediate(lane),
+       g.Use(node->InputAt(1)));
+}
+
+void InstructionSelector::VisitInt8x16Neg(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmInt8x16Neg, g.DefineAsRegister(node),
+       g.UseRegister(node->InputAt(0)));
+}
+
+void InstructionSelector::VisitInt8x16Add(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmInt8x16Add, g.DefineAsRegister(node),
+       g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
+}
+
+void InstructionSelector::VisitInt8x16Sub(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmInt8x16Sub, g.DefineAsRegister(node),
+       g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
+}
+
+void InstructionSelector::VisitInt8x16Mul(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmInt8x16Mul, g.DefineAsRegister(node),
+       g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
+}
+
+void InstructionSelector::VisitInt8x16Min(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmInt8x16Min, g.DefineAsRegister(node),
+       g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
+}
+
+void InstructionSelector::VisitInt8x16Max(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmInt8x16Max, g.DefineAsRegister(node),
+       g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
+}
+
+void InstructionSelector::VisitInt8x16Equal(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmInt8x16Eq, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
+       g.UseRegister(node->InputAt(1)));
+}
+
+void InstructionSelector::VisitInt8x16NotEqual(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmInt8x16Ne, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
+       g.UseRegister(node->InputAt(1)));
+}
+
+void InstructionSelector::VisitInt8x16GreaterThan(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmInt8x16Gt, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
+       g.UseRegister(node->InputAt(1)));
+}
+
+void InstructionSelector::VisitInt8x16GreaterThanOrEqual(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmInt8x16Ge, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
+       g.UseRegister(node->InputAt(1)));
+}
+
+void InstructionSelector::VisitUint8x16GreaterThan(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmUint8x16Gt, g.DefineAsRegister(node),
+       g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
+}
+
+void InstructionSelector::VisitUint8x16GreaterThanOrEqual(Node* node) {
+  ArmOperandGenerator g(this);
+  Emit(kArmUint8x16Ge, g.DefineAsRegister(node),
+       g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
+}
+
 // static
 MachineOperatorBuilder::Flags
 InstructionSelector::SupportedMachineOperatorFlags() {
   MachineOperatorBuilder::Flags flags;
   if (CpuFeatures::IsSupported(SUDIV)) {
     // The sdiv and udiv instructions correctly return 0 if the divisor is 0,
     // but the fall-back implementation does not.
     flags |= MachineOperatorBuilder::kInt32DivIsSafe |
              MachineOperatorBuilder::kUint32DivIsSafe;
   }
@@ skipping 20 matching lines @@
   Vector<MachineType> req_aligned = Vector<MachineType>::New(2);
   req_aligned[0] = MachineType::Float32();
   req_aligned[1] = MachineType::Float64();
   return MachineOperatorBuilder::AlignmentRequirements::
       SomeUnalignedAccessUnsupported(req_aligned, req_aligned);
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8