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Side by Side Diff: runtime/vm/simulator_arm.cc

Issue 26345002: Last cleanup int -> intptr_t. Also removed a hack. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 7 years, 2 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include <math.h> // for isnan. 5 #include <math.h> // for isnan.
6 #include <setjmp.h> 6 #include <setjmp.h>
7 #include <stdlib.h> 7 #include <stdlib.h>
8 8
9 #include "vm/globals.h" 9 #include "vm/globals.h"
10 #if defined(TARGET_ARCH_ARM) 10 #if defined(TARGET_ARCH_ARM)
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1009 1009
1010 void Simulator::UnimplementedInstruction(Instr* instr) { 1010 void Simulator::UnimplementedInstruction(Instr* instr) {
1011 char buffer[64]; 1011 char buffer[64];
1012 snprintf(buffer, sizeof(buffer), "Unimplemented instruction: pc=%p\n", instr); 1012 snprintf(buffer, sizeof(buffer), "Unimplemented instruction: pc=%p\n", instr);
1013 SimulatorDebugger dbg(this); 1013 SimulatorDebugger dbg(this);
1014 dbg.Stop(instr, buffer); 1014 dbg.Stop(instr, buffer);
1015 FATAL("Cannot continue execution after unimplemented instruction."); 1015 FATAL("Cannot continue execution after unimplemented instruction.");
1016 } 1016 }
1017 1017
1018 1018
1019 int Simulator::ReadW(uword addr, Instr* instr) { 1019 intptr_t Simulator::ReadW(uword addr, Instr* instr) {
1020 static StatsCounter counter_read_w("Simulated word reads"); 1020 static StatsCounter counter_read_w("Simulated word reads");
1021 counter_read_w.Increment(); 1021 counter_read_w.Increment();
1022 if ((addr & 3) == 0) { 1022 if ((addr & 3) == 0) {
1023 intptr_t* ptr = reinterpret_cast<intptr_t*>(addr); 1023 intptr_t* ptr = reinterpret_cast<intptr_t*>(addr);
1024 return *ptr; 1024 return *ptr;
1025 } 1025 }
1026 UnalignedAccess("read", addr, instr); 1026 UnalignedAccess("read", addr, instr);
1027 return 0; 1027 return 0;
1028 } 1028 }
1029 1029
1030 1030
1031 void Simulator::WriteW(uword addr, int value, Instr* instr) { 1031 void Simulator::WriteW(uword addr, intptr_t value, Instr* instr) {
1032 static StatsCounter counter_write_w("Simulated word writes"); 1032 static StatsCounter counter_write_w("Simulated word writes");
1033 counter_write_w.Increment(); 1033 counter_write_w.Increment();
1034 if ((addr & 3) == 0) { 1034 if ((addr & 3) == 0) {
1035 intptr_t* ptr = reinterpret_cast<intptr_t*>(addr); 1035 intptr_t* ptr = reinterpret_cast<intptr_t*>(addr);
1036 *ptr = value; 1036 *ptr = value;
1037 return; 1037 return;
1038 } 1038 }
1039 UnalignedAccess("write", addr, instr); 1039 UnalignedAccess("write", addr, instr);
1040 } 1040 }
1041 1041
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1102 1102
1103 // Synchronization primitives support. 1103 // Synchronization primitives support.
1104 void Simulator::ClearExclusive() { 1104 void Simulator::ClearExclusive() {
1105 // This lock is initialized in Simulator::InitOnce(). 1105 // This lock is initialized in Simulator::InitOnce().
1106 MutexLocker ml(exclusive_access_lock_); 1106 MutexLocker ml(exclusive_access_lock_);
1107 // Set exclusive access to open state for this isolate. 1107 // Set exclusive access to open state for this isolate.
1108 HasExclusiveAccessAndOpen(NULL); 1108 HasExclusiveAccessAndOpen(NULL);
1109 } 1109 }
1110 1110
1111 1111
1112 int Simulator::ReadExclusiveW(uword addr, Instr* instr) { 1112 intptr_t Simulator::ReadExclusiveW(uword addr, Instr* instr) {
1113 // This lock is initialized in Simulator::InitOnce(). 1113 // This lock is initialized in Simulator::InitOnce().
1114 MutexLocker ml(exclusive_access_lock_); 1114 MutexLocker ml(exclusive_access_lock_);
1115 SetExclusiveAccess(addr); 1115 SetExclusiveAccess(addr);
1116 return ReadW(addr, instr); 1116 return ReadW(addr, instr);
1117 } 1117 }
1118 1118
1119 1119
1120 int Simulator::WriteExclusiveW(uword addr, int value, Instr* instr) { 1120 intptr_t Simulator::WriteExclusiveW(uword addr, intptr_t value, Instr* instr) {
1121 // This lock is initialized in Simulator::InitOnce(). 1121 // This lock is initialized in Simulator::InitOnce().
1122 MutexLocker ml(exclusive_access_lock_); 1122 MutexLocker ml(exclusive_access_lock_);
1123 bool write_allowed = HasExclusiveAccessAndOpen(addr); 1123 bool write_allowed = HasExclusiveAccessAndOpen(addr);
1124 if (write_allowed) { 1124 if (write_allowed) {
1125 WriteW(addr, value, instr); 1125 WriteW(addr, value, instr);
1126 return 0; // Success. 1126 return 0; // Success.
1127 } 1127 }
1128 return 1; // Failure. 1128 return 1; // Failure.
1129 } 1129 }
1130 1130
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3705 set_register(kExceptionObjectReg, bit_cast<int32_t>(raw_exception)); 3705 set_register(kExceptionObjectReg, bit_cast<int32_t>(raw_exception));
3706 set_register(kStackTraceObjectReg, bit_cast<int32_t>(raw_stacktrace)); 3706 set_register(kStackTraceObjectReg, bit_cast<int32_t>(raw_stacktrace));
3707 buf->Longjmp(); 3707 buf->Longjmp();
3708 } 3708 }
3709 3709
3710 } // namespace dart 3710 } // namespace dart
3711 3711
3712 #endif // !defined(HOST_ARCH_ARM) 3712 #endif // !defined(HOST_ARCH_ARM)
3713 3713
3714 #endif // defined TARGET_ARCH_ARM 3714 #endif // defined TARGET_ARCH_ARM
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