| OLD | NEW |
| 1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 | 4 |
| 5 #include <math.h> // for isnan. | 5 #include <math.h> // for isnan. |
| 6 #include <setjmp.h> | 6 #include <setjmp.h> |
| 7 #include <stdlib.h> | 7 #include <stdlib.h> |
| 8 | 8 |
| 9 #include "vm/globals.h" | 9 #include "vm/globals.h" |
| 10 #if defined(TARGET_ARCH_ARM64) | 10 #if defined(TARGET_ARCH_ARM64) |
| (...skipping 1897 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 1908 break; | 1908 break; |
| 1909 } | 1909 } |
| 1910 default: | 1910 default: |
| 1911 UnimplementedInstruction(instr); | 1911 UnimplementedInstruction(instr); |
| 1912 break; | 1912 break; |
| 1913 } | 1913 } |
| 1914 } | 1914 } |
| 1915 | 1915 |
| 1916 | 1916 |
| 1917 void Simulator::DecodeMiscDP3Source(Instr* instr) { | 1917 void Simulator::DecodeMiscDP3Source(Instr* instr) { |
| 1918 const Register rd = instr->RdField(); |
| 1919 const Register rn = instr->RnField(); |
| 1920 const Register rm = instr->RmField(); |
| 1921 const Register ra = instr->RaField(); |
| 1918 if ((instr->Bits(29, 2) == 0) && (instr->Bits(21, 3) == 0) && | 1922 if ((instr->Bits(29, 2) == 0) && (instr->Bits(21, 3) == 0) && |
| 1919 (instr->Bit(15) == 0)) { | 1923 (instr->Bit(15) == 0)) { |
| 1920 // Format(instr, "madd'sf 'rd, 'rn, 'rm, 'ra"); | 1924 // Format(instr, "madd'sf 'rd, 'rn, 'rm, 'ra"); |
| 1921 const Register rd = instr->RdField(); | |
| 1922 const Register rn = instr->RnField(); | |
| 1923 const Register rm = instr->RmField(); | |
| 1924 const Register ra = instr->RaField(); | |
| 1925 if (instr->SFField() == 1) { | 1925 if (instr->SFField() == 1) { |
| 1926 const int64_t rn_val = get_register(rn, R31IsZR); | 1926 const int64_t rn_val = get_register(rn, R31IsZR); |
| 1927 const int64_t rm_val = get_register(rm, R31IsZR); | 1927 const int64_t rm_val = get_register(rm, R31IsZR); |
| 1928 const int64_t ra_val = get_register(ra, R31IsZR); | 1928 const int64_t ra_val = get_register(ra, R31IsZR); |
| 1929 const int64_t alu_out = ra_val + (rn_val * rm_val); | 1929 const int64_t alu_out = ra_val + (rn_val * rm_val); |
| 1930 set_register(rd, alu_out, R31IsZR); | 1930 set_register(rd, alu_out, R31IsZR); |
| 1931 } else { | 1931 } else { |
| 1932 const int32_t rn_val = get_wregister(rn, R31IsZR); | 1932 const int32_t rn_val = get_wregister(rn, R31IsZR); |
| 1933 const int32_t rm_val = get_wregister(rm, R31IsZR); | 1933 const int32_t rm_val = get_wregister(rm, R31IsZR); |
| 1934 const int32_t ra_val = get_wregister(ra, R31IsZR); | 1934 const int32_t ra_val = get_wregister(ra, R31IsZR); |
| 1935 const int32_t alu_out = ra_val + (rn_val * rm_val); | 1935 const int32_t alu_out = ra_val + (rn_val * rm_val); |
| 1936 set_wregister(rd, alu_out, R31IsZR); | 1936 set_wregister(rd, alu_out, R31IsZR); |
| 1937 } | 1937 } |
| 1938 } else if ((instr->Bits(29, 2) == 0) && (instr->Bits(21, 3) == 0) && |
| 1939 (instr->Bit(15) == 1)) { |
| 1940 // Format(instr, "msub'sf 'rd, 'rn, 'rm, 'ra"); |
| 1941 if (instr->SFField() == 1) { |
| 1942 const int64_t rn_val = get_register(rn, R31IsZR); |
| 1943 const int64_t rm_val = get_register(rm, R31IsZR); |
| 1944 const int64_t ra_val = get_register(ra, R31IsZR); |
| 1945 const int64_t alu_out = ra_val - (rn_val * rm_val); |
| 1946 set_register(rd, alu_out, R31IsZR); |
| 1947 } else { |
| 1948 const int32_t rn_val = get_wregister(rn, R31IsZR); |
| 1949 const int32_t rm_val = get_wregister(rm, R31IsZR); |
| 1950 const int32_t ra_val = get_wregister(ra, R31IsZR); |
| 1951 const int32_t alu_out = ra_val - (rn_val * rm_val); |
| 1952 set_wregister(rd, alu_out, R31IsZR); |
| 1953 } |
| 1954 } else if ((instr->Bits(29, 2) == 0) && (instr->Bits(21, 3) == 2) && |
| 1955 (instr->Bit(15) == 0)) { |
| 1956 // Format(instr, "smulh 'rd, 'rn, 'rm"); |
| 1957 const int64_t rn_val = get_register(rn, R31IsZR); |
| 1958 const int64_t rm_val = get_register(rm, R31IsZR); |
| 1959 const __int128 res = |
| 1960 static_cast<__int128>(rn_val) * static_cast<__int128>(rm_val); |
| 1961 const int64_t alu_out = static_cast<int64_t>(res >> 64); |
| 1962 set_register(rd, alu_out, R31IsZR); |
| 1938 } else { | 1963 } else { |
| 1939 UnimplementedInstruction(instr); | 1964 UnimplementedInstruction(instr); |
| 1940 } | 1965 } |
| 1941 } | 1966 } |
| 1942 | 1967 |
| 1943 | 1968 |
| 1944 void Simulator::DecodeConditionalSelect(Instr* instr) { | 1969 void Simulator::DecodeConditionalSelect(Instr* instr) { |
| 1945 if ((instr->Bits(29, 2) == 0) && (instr->Bits(10, 2) == 0)) { | 1970 if ((instr->Bits(29, 2) == 0) && (instr->Bits(10, 2) == 0)) { |
| 1946 // Format(instr, "mov'sf'cond 'rd, 'rn, 'rm"); | 1971 // Format(instr, "mov'sf'cond 'rd, 'rn, 'rm"); |
| 1947 const Register rd = instr->RdField(); | 1972 const Register rd = instr->RdField(); |
| (...skipping 81 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 2029 const VRegister vd = instr->VdField(); | 2054 const VRegister vd = instr->VdField(); |
| 2030 const Register rn = instr->RnField(); | 2055 const Register rn = instr->RnField(); |
| 2031 const int64_t rn_val = get_register(rn, R31IsZR); | 2056 const int64_t rn_val = get_register(rn, R31IsZR); |
| 2032 set_vregisterd(vd, rn_val); | 2057 set_vregisterd(vd, rn_val); |
| 2033 } else { | 2058 } else { |
| 2034 UnimplementedInstruction(instr); | 2059 UnimplementedInstruction(instr); |
| 2035 } | 2060 } |
| 2036 } | 2061 } |
| 2037 | 2062 |
| 2038 | 2063 |
| 2064 void Simulator::DecodeFPOneSource(Instr* instr) { |
| 2065 const int opc = instr->Bits(15, 2); |
| 2066 const VRegister vd = instr->VdField(); |
| 2067 const VRegister vn = instr->VnField(); |
| 2068 switch (opc) { |
| 2069 case 0: |
| 2070 // Format("fmovdd 'vd, 'vn"); |
| 2071 set_vregisterd(vd, get_vregisterd(vn)); |
| 2072 break; |
| 2073 default: |
| 2074 UnimplementedInstruction(instr); |
| 2075 break; |
| 2076 } |
| 2077 } |
| 2078 |
| 2079 |
| 2039 void Simulator::DecodeFP(Instr* instr) { | 2080 void Simulator::DecodeFP(Instr* instr) { |
| 2040 if (instr->IsFPImmOp()) { | 2081 if (instr->IsFPImmOp()) { |
| 2041 DecodeFPImm(instr); | 2082 DecodeFPImm(instr); |
| 2042 } else if (instr->IsFPIntCvtOp()) { | 2083 } else if (instr->IsFPIntCvtOp()) { |
| 2043 DecodeFPIntCvt(instr); | 2084 DecodeFPIntCvt(instr); |
| 2085 } else if (instr->IsFPOneSourceOp()) { |
| 2086 DecodeFPOneSource(instr); |
| 2044 } else { | 2087 } else { |
| 2045 UnimplementedInstruction(instr); | 2088 UnimplementedInstruction(instr); |
| 2046 } | 2089 } |
| 2047 } | 2090 } |
| 2048 | 2091 |
| 2049 | 2092 |
| 2050 void Simulator::DecodeDPSimd2(Instr* instr) { | 2093 void Simulator::DecodeDPSimd2(Instr* instr) { |
| 2051 if (instr->IsFPOp()) { | 2094 if (instr->IsFPOp()) { |
| 2052 DecodeFP(instr); | 2095 DecodeFP(instr); |
| 2053 } else { | 2096 } else { |
| (...skipping 189 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 2243 set_register(kExceptionObjectReg, bit_cast<int64_t>(raw_exception)); | 2286 set_register(kExceptionObjectReg, bit_cast<int64_t>(raw_exception)); |
| 2244 set_register(kStackTraceObjectReg, bit_cast<int64_t>(raw_stacktrace)); | 2287 set_register(kStackTraceObjectReg, bit_cast<int64_t>(raw_stacktrace)); |
| 2245 buf->Longjmp(); | 2288 buf->Longjmp(); |
| 2246 } | 2289 } |
| 2247 | 2290 |
| 2248 } // namespace dart | 2291 } // namespace dart |
| 2249 | 2292 |
| 2250 #endif // !defined(HOST_ARCH_ARM64) | 2293 #endif // !defined(HOST_ARCH_ARM64) |
| 2251 | 2294 |
| 2252 #endif // defined TARGET_ARCH_ARM64 | 2295 #endif // defined TARGET_ARCH_ARM64 |
| OLD | NEW |