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Side by Side Diff: runtime/vm/constants_arm64.h

Issue 263243002: Enables many language tests for arm64. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 6 years, 7 months ago
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1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #ifndef VM_CONSTANTS_ARM64_H_ 5 #ifndef VM_CONSTANTS_ARM64_H_
6 #define VM_CONSTANTS_ARM64_H_ 6 #define VM_CONSTANTS_ARM64_H_
7 7
8 #include "platform/assert.h" 8 #include "platform/assert.h"
9 9
10 namespace dart { 10 namespace dart {
(...skipping 79 matching lines...) Expand 10 before | Expand all | Expand 10 after
90 V27 = 27, 90 V27 = 27,
91 V28 = 28, 91 V28 = 28,
92 V29 = 29, 92 V29 = 29,
93 V30 = 30, 93 V30 = 30,
94 V31 = 31, 94 V31 = 31,
95 kNumberOfVRegisters = 32, 95 kNumberOfVRegisters = 32,
96 kNoVRegister = -1, 96 kNoVRegister = -1,
97 }; 97 };
98 98
99 // Register alias for floating point scratch register. 99 // Register alias for floating point scratch register.
100 const VRegister VTMP0 = V30; 100 const VRegister VTMP = V31;
101 const VRegister VTMP1 = V31;
102 101
103 // Architecture independent aliases. 102 // Architecture independent aliases.
104 typedef VRegister FpuRegister; 103 typedef VRegister FpuRegister;
105 const FpuRegister FpuTMP = VTMP0; 104 const FpuRegister FpuTMP = VTMP;
106 const int kNumberOfFpuRegisters = kNumberOfVRegisters; 105 const int kNumberOfFpuRegisters = kNumberOfVRegisters;
107 const FpuRegister kNoFpuRegister = kNoVRegister; 106 const FpuRegister kNoFpuRegister = kNoVRegister;
108 107
109 // Register aliases. 108 // Register aliases.
110 const Register TMP = R16; // Used as scratch register by assembler. 109 const Register TMP = R16; // Used as scratch register by assembler.
111 const Register TMP2 = R17; 110 const Register TMP2 = R17;
112 const Register CTX = R28; // Caches current context in generated code. 111 const Register CTX = R28; // Caches current context in generated code.
113 const Register PP = R27; // Caches object pool pointer in generated code. 112 const Register PP = R27; // Caches object pool pointer in generated code.
114 const Register kNoPP = kNoRegister; 113 const Register kNoPP = kNoRegister;
115 const Register FPREG = FP; // Frame pointer register. 114 const Register FPREG = FP; // Frame pointer register.
(...skipping 280 matching lines...) Expand 10 before | Expand all | Expand 10 after
396 LSLV = MiscDP2SourceFixed | B13, 395 LSLV = MiscDP2SourceFixed | B13,
397 LSRV = MiscDP2SourceFixed | B13 | B10, 396 LSRV = MiscDP2SourceFixed | B13 | B10,
398 ASRV = MiscDP2SourceFixed | B13 | B11, 397 ASRV = MiscDP2SourceFixed | B13 | B11,
399 }; 398 };
400 399
401 // C3.5.9 400 // C3.5.9
402 enum MiscDP3SourceOp { 401 enum MiscDP3SourceOp {
403 MiscDP3SourceMask = 0x1f000000, 402 MiscDP3SourceMask = 0x1f000000,
404 MiscDP3SourceFixed = DPRegisterFixed | B28 | B24, 403 MiscDP3SourceFixed = DPRegisterFixed | B28 | B24,
405 MADD = MiscDP3SourceFixed, 404 MADD = MiscDP3SourceFixed,
405 MSUB = MiscDP3SourceFixed | B15,
406 SMULH = MiscDP3SourceFixed | B31 | B22,
406 }; 407 };
407 408
408 // C3.5.10 409 // C3.5.10
409 enum LogicalShiftOp { 410 enum LogicalShiftOp {
410 LogicalShiftMask = 0x1f000000, 411 LogicalShiftMask = 0x1f000000,
411 LogicalShiftFixed = DPRegisterFixed, 412 LogicalShiftFixed = DPRegisterFixed,
412 AND = LogicalShiftFixed, 413 AND = LogicalShiftFixed,
413 BIC = LogicalShiftFixed | B21, 414 BIC = LogicalShiftFixed | B21,
414 ORR = LogicalShiftFixed | B29, 415 ORR = LogicalShiftFixed | B29,
415 ORN = LogicalShiftFixed | B29 | B21, 416 ORN = LogicalShiftFixed | B29 | B21,
416 EOR = LogicalShiftFixed | B30, 417 EOR = LogicalShiftFixed | B30,
417 EON = LogicalShiftFixed | B30 | B21, 418 EON = LogicalShiftFixed | B30 | B21,
418 ANDS = LogicalShiftFixed | B30 | B29, 419 ANDS = LogicalShiftFixed | B30 | B29,
419 BICS = LogicalShiftFixed | B30 | B29 | B21, 420 BICS = LogicalShiftFixed | B30 | B29 | B21,
420 }; 421 };
421 422
423 // C3.6.25
424 enum FPOneSourceOp {
425 FPOneSourceMask = 0x5f207c00,
426 FPOneSourceFixed = FPFixed | B21 | B14,
427 FMOVDD = FPOneSourceFixed | B22,
428 };
429
422 // C3.6.28 430 // C3.6.28
423 enum FPImmOp { 431 enum FPImmOp {
424 FPImmMask = 0x5f201c00, 432 FPImmMask = 0x5f201c00,
425 FPImmFixed = FPFixed | B21 | B12, 433 FPImmFixed = FPFixed | B21 | B12,
426 FMOVSI = FPImmFixed, 434 FMOVSI = FPImmFixed,
427 FMOVDI = FPImmFixed | B22, 435 FMOVDI = FPImmFixed | B22,
428 }; 436 };
429 437
430 // C3.6.29 438 // C3.6.29
431 enum FPIntCvtOp { 439 enum FPIntCvtOp {
(...skipping 23 matching lines...) Expand all
455 _V(LoadRegLiteral) \ 463 _V(LoadRegLiteral) \
456 _V(AddSubImm) \ 464 _V(AddSubImm) \
457 _V(LogicalImm) \ 465 _V(LogicalImm) \
458 _V(MoveWide) \ 466 _V(MoveWide) \
459 _V(PCRel) \ 467 _V(PCRel) \
460 _V(AddSubShiftExt) \ 468 _V(AddSubShiftExt) \
461 _V(ConditionalSelect) \ 469 _V(ConditionalSelect) \
462 _V(MiscDP2Source) \ 470 _V(MiscDP2Source) \
463 _V(MiscDP3Source) \ 471 _V(MiscDP3Source) \
464 _V(LogicalShift) \ 472 _V(LogicalShift) \
473 _V(FPOneSource) \
465 _V(FPImm) \ 474 _V(FPImm) \
466 _V(FPIntCvt) \ 475 _V(FPIntCvt) \
467 476
468 477
469 enum Shift { 478 enum Shift {
470 kNoShift = -1, 479 kNoShift = -1,
471 LSL = 0, // Logical shift left 480 LSL = 0, // Logical shift left
472 LSR = 1, // Logical shift right 481 LSR = 1, // Logical shift right
473 ASR = 2, // Arithmetic shift right 482 ASR = 2, // Arithmetic shift right
474 ROR = 3, // Rotate right 483 ROR = 3, // Rotate right
(...skipping 391 matching lines...) Expand 10 before | Expand all | Expand 10 after
866 static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); } 875 static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); }
867 876
868 private: 877 private:
869 DISALLOW_ALLOCATION(); 878 DISALLOW_ALLOCATION();
870 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr); 879 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
871 }; 880 };
872 881
873 } // namespace dart 882 } // namespace dart
874 883
875 #endif // VM_CONSTANTS_ARM64_H_ 884 #endif // VM_CONSTANTS_ARM64_H_
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