[ARM] Add Neon shift instructions vshl, vshr.

test/cctest/test-assembler-arm.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 1283 matching lines @@
     float vabsf[4], vnegf[4];
     uint32_t vabs_s8[4], vabs_s16[4], vabs_s32[4];
     uint32_t vneg_s8[4], vneg_s16[4], vneg_s32[4];
     uint32_t veor[4], vand[4], vorr[4];
     float vdupf[4], vaddf[4], vsubf[4], vmulf[4];
     uint32_t vmin_s8[4], vmin_u16[4], vmin_s32[4];
     uint32_t vmax_s8[4], vmax_u16[4], vmax_s32[4];
     uint32_t vadd8[4], vadd16[4], vadd32[4];
     uint32_t vsub8[4], vsub16[4], vsub32[4];
     uint32_t vmul8[4], vmul16[4], vmul32[4];
+    uint32_t vshl8[4], vshl16[4], vshl32[5];
+    uint32_t vshr_s8[4], vshr_u16[4], vshr_s32[5];
     uint32_t vceq[4], vceqf[4], vcgef[4], vcgtf[4];
     uint32_t vcge_s8[4], vcge_u16[4], vcge_s32[4];
     uint32_t vcgt_s8[4], vcgt_u16[4], vcgt_s32[4];
     float vrecpe[4], vrecps[4], vrsqrte[4], vrsqrts[4];
     float vminf[4], vmaxf[4];
     uint32_t vtst[4], vbsl[4];
     uint32_t vext[4];
     uint32_t vzip8a[4], vzip8b[4], vzip16a[4], vzip16b[4], vzip32a[4],
         vzip32b[4];
     uint32_t vrev64_32[4], vrev64_16[4], vrev64_8[4];
@@ skipping 350 matching lines @@
     __ vdup(Neon16, q0, r4);
     __ vmul(Neon16, q1, q0, q0);
     __ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, vmul16))));
     __ vst1(Neon8, NeonListOperand(q1), NeonMemOperand(r4));
     __ mov(r4, Operand(0x00000002));
     __ vdup(Neon32, q0, r4);
     __ vmul(Neon32, q1, q0, q0);
     __ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, vmul32))));
     __ vst1(Neon8, NeonListOperand(q1), NeonMemOperand(r4));
 
+    // vshl.
+    __ mov(r4, Operand(0x55));
+    __ vdup(Neon8, q0, r4);
+    __ vshl(NeonS8, q1, q0, 1);
+    __ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, vshl8))));
+    __ vst1(Neon8, NeonListOperand(q1), NeonMemOperand(r4));
+    __ vshl(NeonU16, q1, q0, 9);
+    __ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, vshl16))));
+    __ vst1(Neon8, NeonListOperand(q1), NeonMemOperand(r4));
+    __ vshl(NeonS32, q1, q0, 17);
+    __ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, vshl32))));
+    __ vst1(Neon8, NeonListOperand(q1), NeonMemOperand(r4));
+
+    // vshr.s, vshr.u.
+    __ mov(r4, Operand(0x80));
+    __ vdup(Neon8, q0, r4);
+    __ vshr(NeonS8, q1, q0, 1);
+    __ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, vshr_s8))));
+    __ vst1(Neon8, NeonListOperand(q1), NeonMemOperand(r4));
+    __ vshr(NeonU16, q1, q0, 9);
+    __ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, vshr_u16))));
+    __ vst1(Neon8, NeonListOperand(q1), NeonMemOperand(r4));
+    __ vshr(NeonS32, q1, q0, 17);
+    __ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, vshr_s32))));
+    __ vst1(Neon8, NeonListOperand(q1), NeonMemOperand(r4));
+
     // vceq.
     __ mov(r4, Operand(0x03));
     __ vdup(Neon8, q0, r4);
     __ vdup(Neon16, q1, r4);
     __ vceq(Neon8, q1, q0, q1);
     __ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, vceq))));
     __ vst1(Neon8, NeonListOperand(q1), NeonMemOperand(r4));
 
     // vcge/vcgt (integer).
     __ mov(r4, Operand(0x03));
@@ skipping 235 matching lines @@
     CHECK_EQ_SPLAT(vmax_s32, 0xffu);
     CHECK_EQ_SPLAT(vadd8, 0x03030303u);
     CHECK_EQ_SPLAT(vadd16, 0x00030003u);
     CHECK_EQ_SPLAT(vadd32, 0x00000003u);
     CHECK_EQ_SPLAT(vsub8, 0xfefefefeu);
     CHECK_EQ_SPLAT(vsub16, 0xfffefffeu);
     CHECK_EQ_SPLAT(vsub32, 0xfffffffeu);
     CHECK_EQ_SPLAT(vmul8, 0x04040404u);
     CHECK_EQ_SPLAT(vmul16, 0x00040004u);
     CHECK_EQ_SPLAT(vmul32, 0x00000004u);
+    CHECK_EQ_SPLAT(vshl8, 0xaaaaaaaau);
+    CHECK_EQ_SPLAT(vshl16, 0xaa00aa00u);
+    CHECK_EQ_SPLAT(vshl32, 0xaaaa0000u);
+    CHECK_EQ_SPLAT(vshr_s8, 0xc0c0c0c0u);
+    CHECK_EQ_SPLAT(vshr_u16, 0x00400040u);
+    CHECK_EQ_SPLAT(vshr_s32, 0xffffc040u);
     CHECK_EQ_SPLAT(vceq, 0x00ff00ffu);
     // [0, 3, 0, 3, ...] >= [3, 3, 3, 3, ...]
     CHECK_EQ_SPLAT(vcge_s8, 0x00ff00ffu);
     CHECK_EQ_SPLAT(vcgt_s8, 0u);
     // [0x00ff, 0x00ff, ...] >= [0xffff, 0xffff, ...]
     CHECK_EQ_SPLAT(vcge_u16, 0u);
     CHECK_EQ_SPLAT(vcgt_u16, 0u);
     // [0x000000ff, 0x000000ff, ...] >= [0xffffffff, 0xffffffff, ...]
     CHECK_EQ_SPLAT(vcge_s32, 0xffffffffu);
     CHECK_EQ_SPLAT(vcgt_s32, 0xffffffffu);
@@ skipping 1699 matching lines @@
   HandleScope scope(isolate);
 
   Assembler assm(isolate, NULL, 0);
   __ mov(r0, Operand(isolate->factory()->infinity_value()));
   __ BlockConstPoolFor(1019);
   for (int i = 0; i < 1019; ++i) __ nop();
   __ vldr(d0, MemOperand(r0, 0));
 }
 
 #undef __