Convert BinadryDoubleOp to MathUnaryInstr double-square if both inputs are the same. Uses less regi…

runtime/vm/intermediate_language_x64.cc

Index: runtime/vm/intermediate_language_x64.cc
===================================================================
--- runtime/vm/intermediate_language_x64.cc	(revision 35690)
+++ runtime/vm/intermediate_language_x64.cc	(working copy)
@@ -4407,8 +4407,7 @@
 
 
 LocationSummary* MathUnaryInstr::MakeLocationSummary(bool opt) const {
-  if ((kind() == MethodRecognizer::kMathSin) ||
-      (kind() == MethodRecognizer::kMathCos)) {
+  if ((kind() == MathUnaryInstr::kSin) || (kind() == MathUnaryInstr::kCos)) {
     // Calling convention on x64 uses XMM0 and XMM1 to pass the first two
     // double arguments and XMM0 to return the result. Unfortunately
     // currently we can't specify these registers because ParallelMoveResolver
@@ -4424,23 +4423,32 @@
     summary->set_out(0, Location::FpuRegisterLocation(XMM1));
     return summary;
   }
-  ASSERT(kind() == MethodRecognizer::kMathSqrt);
+  ASSERT((kind() == MathUnaryInstr::kSqrt) ||
+      (kind() == MathUnaryInstr::kDoubleSquare));

[Cutch, 2014/05/02 21:24:48]

and here

[srdjan, 2014/05/02 22:05:21]

Done.

   const intptr_t kNumInputs = 1;
   const intptr_t kNumTemps = 0;
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_in(0, Location::RequiresFpuRegister());
-  summary->set_out(0, Location::RequiresFpuRegister());
+  if (kind() == MathUnaryInstr::kDoubleSquare) {
+    summary->set_out(0, Location::SameAsFirstInput());
+  } else {
+    summary->set_out(0, Location::RequiresFpuRegister());
+  }
   return summary;
 }
 
 
 void MathUnaryInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  if (kind() == MethodRecognizer::kMathSqrt) {
+  if (kind() == MathUnaryInstr::kSqrt) {
     __ sqrtsd(locs()->out(0).fpu_reg(), locs()->in(0).fpu_reg());
+  } else if (kind() == MathUnaryInstr::kDoubleSquare) {
+    XmmRegister value_reg = locs()->in(0).fpu_reg();
+    __ mulsd(value_reg, value_reg);
+    ASSERT(value_reg == locs()->out(0).fpu_reg());
   } else {
-    ASSERT((kind() == MethodRecognizer::kMathSin) ||
-           (kind() == MethodRecognizer::kMathCos));
+    ASSERT((kind() == MathUnaryInstr::kSin) ||
+           (kind() == MathUnaryInstr::kCos));
     // Save RSP.
     __ movq(locs()->temp(0).reg(), RSP);
     __ ReserveAlignedFrameSpace(0);