OLD | NEW |
1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file |
2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
4 | 4 |
5 #ifndef RUNTIME_VM_CONSTANTS_ARM64_H_ | 5 #ifndef RUNTIME_VM_CONSTANTS_ARM64_H_ |
6 #define RUNTIME_VM_CONSTANTS_ARM64_H_ | 6 #define RUNTIME_VM_CONSTANTS_ARM64_H_ |
7 | 7 |
8 #include "platform/assert.h" | 8 #include "platform/assert.h" |
9 | 9 |
10 namespace dart { | 10 namespace dart { |
(...skipping 792 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
803 kHintOp2Bits = 3, | 803 kHintOp2Bits = 3, |
804 }; | 804 }; |
805 | 805 |
806 | 806 |
807 // Helper functions for decoding logical immediates. | 807 // Helper functions for decoding logical immediates. |
808 static inline uint64_t RotateRight(uint64_t value, | 808 static inline uint64_t RotateRight(uint64_t value, |
809 uint8_t rotate, | 809 uint8_t rotate, |
810 uint8_t width) { | 810 uint8_t width) { |
811 ASSERT(width <= 64); | 811 ASSERT(width <= 64); |
812 rotate &= 63; | 812 rotate &= 63; |
813 return ((value & ((1UL << rotate) - 1UL)) << (width - rotate)) | | 813 return ((value & ((1ULL << rotate) - 1ULL)) << (width - rotate)) | |
814 (value >> rotate); | 814 (value >> rotate); |
815 } | 815 } |
816 | 816 |
817 static inline uint64_t RepeatBitsAcrossReg(uint8_t reg_size, | 817 static inline uint64_t RepeatBitsAcrossReg(uint8_t reg_size, |
818 uint64_t value, | 818 uint64_t value, |
819 uint8_t width) { | 819 uint8_t width) { |
820 ASSERT((width == 2) || (width == 4) || (width == 8) || (width == 16) || | 820 ASSERT((width == 2) || (width == 4) || (width == 8) || (width == 16) || |
821 (width == 32)); | 821 (width == 32)); |
822 ASSERT((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits)); | 822 ASSERT((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits)); |
823 uint64_t result = value & ((1UL << width) - 1UL); | 823 uint64_t result = value & ((1ULL << width) - 1ULL); |
824 for (unsigned i = width; i < reg_size; i *= 2) { | 824 for (unsigned i = width; i < reg_size; i *= 2) { |
825 result |= (result << i); | 825 result |= (result << i); |
826 } | 826 } |
827 return result; | 827 return result; |
828 } | 828 } |
829 | 829 |
830 // The class Instr enables access to individual fields defined in the ARM | 830 // The class Instr enables access to individual fields defined in the ARM |
831 // architecture instruction set encoding as described in figure A3-1. | 831 // architecture instruction set encoding as described in figure A3-1. |
832 // | 832 // |
833 // Example: Test whether the instruction at ptr sets the condition code bits. | 833 // Example: Test whether the instruction at ptr sets the condition code bits. |
(...skipping 246 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1080 // (s bits must not be all set) | 1080 // (s bits must not be all set) |
1081 // | 1081 // |
1082 // A pattern is constructed of size bits, where the least significant S+1 | 1082 // A pattern is constructed of size bits, where the least significant S+1 |
1083 // bits are set. The pattern is rotated right by R, and repeated across a | 1083 // bits are set. The pattern is rotated right by R, and repeated across a |
1084 // 32 or 64-bit value, depending on destination register width. | 1084 // 32 or 64-bit value, depending on destination register width. |
1085 | 1085 |
1086 if (n == 1) { | 1086 if (n == 1) { |
1087 if (imm_s == 0x3F) { | 1087 if (imm_s == 0x3F) { |
1088 return 0; | 1088 return 0; |
1089 } | 1089 } |
1090 uint64_t bits = (1UL << (imm_s + 1)) - 1; | 1090 uint64_t bits = (1ULL << (imm_s + 1)) - 1; |
1091 return RotateRight(bits, imm_r, 64); | 1091 return RotateRight(bits, imm_r, 64); |
1092 } else { | 1092 } else { |
1093 if ((imm_s >> 1) == 0x1F) { | 1093 if ((imm_s >> 1) == 0x1F) { |
1094 return 0; | 1094 return 0; |
1095 } | 1095 } |
1096 for (int width = 0x20; width >= 0x2; width >>= 1) { | 1096 for (int width = 0x20; width >= 0x2; width >>= 1) { |
1097 if ((imm_s & width) == 0) { | 1097 if ((imm_s & width) == 0) { |
1098 int mask = width - 1; | 1098 int mask = width - 1; |
1099 if ((imm_s & mask) == mask) { | 1099 if ((imm_s & mask) == mask) { |
1100 return 0; | 1100 return 0; |
1101 } | 1101 } |
1102 uint64_t bits = (1UL << ((imm_s & mask) + 1)) - 1; | 1102 uint64_t bits = (1ULL << ((imm_s & mask) + 1)) - 1; |
1103 return RepeatBitsAcrossReg( | 1103 return RepeatBitsAcrossReg( |
1104 reg_size, RotateRight(bits, imm_r & mask, width), width); | 1104 reg_size, RotateRight(bits, imm_r & mask, width), width); |
1105 } | 1105 } |
1106 } | 1106 } |
1107 } | 1107 } |
1108 UNREACHABLE(); | 1108 UNREACHABLE(); |
1109 return 0; | 1109 return 0; |
1110 } | 1110 } |
1111 | 1111 |
1112 static int64_t VFPExpandImm(uint8_t imm8) { | 1112 static int64_t VFPExpandImm(uint8_t imm8) { |
(...skipping 12 matching lines...) Expand all Loading... |
1125 static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); } | 1125 static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); } |
1126 | 1126 |
1127 private: | 1127 private: |
1128 DISALLOW_ALLOCATION(); | 1128 DISALLOW_ALLOCATION(); |
1129 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr); | 1129 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr); |
1130 }; | 1130 }; |
1131 | 1131 |
1132 } // namespace dart | 1132 } // namespace dart |
1133 | 1133 |
1134 #endif // RUNTIME_VM_CONSTANTS_ARM64_H_ | 1134 #endif // RUNTIME_VM_CONSTANTS_ARM64_H_ |
OLD | NEW |