Uses double load/store on arm64, enables tests.

runtime/vm/intermediate_language_arm64.cc

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_ARM64.
 #if defined(TARGET_ARCH_ARM64)
 
 #include "vm/intermediate_language.h"
 
 #include "vm/dart_entry.h"
@@ skipping 592 matching lines @@
     case kTypedDataUint16ArrayCid:
       locs->set_in(2, Location::WritableRegister());
       break;
     case kTypedDataInt32ArrayCid:
     case kTypedDataUint32ArrayCid:
       // Mints are stored in Q registers. For smis, use a writable register
       // because the value must be untagged before storing.
       if (value()->IsSmiValue()) {
         locs->set_in(2, Location::WritableRegister());
       } else {
-        // TODO(zra): Implement when we add fpu loads and stores.
+        // TODO(zra): Implement when we add simd loads and stores.
         UNIMPLEMENTED();
       }
       break;
     case kTypedDataFloat32ArrayCid:
+      // TODO(zra): Implement when we add float store.
+      UNIMPLEMENTED();
+      break;
     case kTypedDataFloat64ArrayCid:  // TODO(srdjan): Support Float64 constants.
+      locs->set_in(2, Location::RequiresFpuRegister());
+      break;
     case kTypedDataInt32x4ArrayCid:
     case kTypedDataFloat32x4ArrayCid:
     case kTypedDataFloat64x2ArrayCid:
-      // TODO(zra): Implement when we add fpu loads and stores.
+      // TODO(zra): Implement when we add simd loads and stores.
       UNIMPLEMENTED();
       break;
     default:
       UNREACHABLE();
       return NULL;
   }
   return locs;
 }
 
 
@@ skipping 102 matching lines @@
       break;
     }
     case kTypedDataInt32ArrayCid:
     case kTypedDataUint32ArrayCid: {
       if (value()->IsSmiValue()) {
         ASSERT(RequiredInputRepresentation(2) == kTagged);
         Register value = locs()->in(2).reg();
         __ SmiUntag(value);
         __ str(value, element_address);
       } else {
-        // TODO(zra): Implement when we add fpu loads and stores.
+        // TODO(zra): Implement when we add simd loads and stores.
         UNIMPLEMENTED();
       }
       break;
     }
     case kTypedDataFloat32ArrayCid:
-    case kTypedDataFloat64ArrayCid:
+      // TODO(zra): Implement when we add float store.
+      UNIMPLEMENTED();
+      break;
+    case kTypedDataFloat64ArrayCid: {
+      VRegister in2 = locs()->in(2).fpu_reg();
+      __ add(index.reg(), index.reg(), Operand(array));
+      __ StoreDFieldToOffset(in2, index.reg(), 0);
+      break;
+    }
     case kTypedDataFloat64x2ArrayCid:
     case kTypedDataInt32x4ArrayCid:
     case kTypedDataFloat32x4ArrayCid: {
-      // TODO(zra): Implement when we add fpu loads and stores.
+      // TODO(zra): Implement when we add simd loads and stores.
       UNIMPLEMENTED();
       break;
     }
     default:
       UNREACHABLE();
   }
 }
 
 
 static void LoadValueCid(FlowGraphCompiler* compiler,
@@ skipping 120 matching lines @@
           __ CompareImmediate(TMP, 0, PP);
           __ b(&skip_length_check, LT);
           __ CompareImmediate(value_cid_reg, kNullCid, PP);
           __ b(&no_fixed_length, EQ);
           // Check for typed data array.
           __ CompareImmediate(value_cid_reg, kTypedDataInt32x4ArrayCid, PP);
           __ b(&no_fixed_length, GT);
           __ CompareImmediate(value_cid_reg, kTypedDataInt8ArrayCid, PP);
           // Could still be a regular array.
           __ b(&check_array, LT);
-          __ LoadFromOffset(temp_reg, value_reg, TypedData::length_offset());
+          __ LoadFieldFromOffset(
+              temp_reg, value_reg, TypedData::length_offset());
           __ ldr(TMP, field_length_operand);
           __ CompareRegisters(temp_reg, TMP);
           __ b(&length_compared);
           // Check for regular array.
           __ Bind(&check_array);
           __ CompareImmediate(value_cid_reg, kImmutableArrayCid, PP);
           __ b(&no_fixed_length, GT);
           __ CompareImmediate(value_cid_reg, kArrayCid, PP);
           __ b(&no_fixed_length, LT);
           __ LoadFieldFromOffset(temp_reg, value_reg, Array::length_offset());
@@ skipping 228 matching lines @@
   const intptr_t kNumTemps = 0;
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps,
           !field().IsNull() &&
           ((field().guarded_cid() == kIllegalCid) || is_initialization_)
           ? LocationSummary::kCallOnSlowPath
           : LocationSummary::kNoCall);
 
   summary->set_in(0, Location::RequiresRegister());
   if (IsUnboxedStore() && opt) {
-    // TODO(zra): Implement when we add fpu loads and stores.
-    UNIMPLEMENTED();
+    summary->set_in(1, Location::RequiresFpuRegister());
+    summary->AddTemp(Location::RequiresRegister());
+    summary->AddTemp(Location::RequiresRegister());
   } else if (IsPotentialUnboxedStore()) {
       summary->set_in(1, ShouldEmitStoreBarrier()
           ? Location::WritableRegister()
           :  Location::RequiresRegister());
       summary->AddTemp(Location::RequiresRegister());
       summary->AddTemp(Location::RequiresRegister());
+      summary->AddTemp(opt ? Location::RequiresFpuRegister()
+                           : Location::FpuRegisterLocation(V1));
   } else {
     summary->set_in(1, ShouldEmitStoreBarrier()
                        ? Location::WritableRegister()
                        : Location::RegisterOrConstant(value()));
   }
   return summary;
 }
 
 
 void StoreInstanceFieldInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
   Label skip_store;
 
   Register instance_reg = locs()->in(0).reg();
 
   if (IsUnboxedStore() && compiler->is_optimizing()) {
-    UNIMPLEMENTED();
+    const VRegister value = locs()->in(1).fpu_reg();
+    const Register temp = locs()->temp(0).reg();
+    const Register temp2 = locs()->temp(1).reg();
+    const intptr_t cid = field().UnboxedFieldCid();
+
+    if (is_initialization_) {
+      const Class* cls = NULL;
+      switch (cid) {
+        case kDoubleCid:
+          cls = &compiler->double_class();
+          break;
+        // TODO(zra): Implement these when we add fpu loads and stores.
+        case kFloat32x4Cid:
+        case kFloat64x2Cid:
+          UNIMPLEMENTED();
+          break;
+        default:
+          UNREACHABLE();
+      }
+
+      StoreInstanceFieldSlowPath* slow_path =
+          new StoreInstanceFieldSlowPath(this, *cls);
+      compiler->AddSlowPathCode(slow_path);
+
+      __ TryAllocate(*cls,
+                     slow_path->entry_label(),
+                     temp,
+                     temp2,
+                     PP);
+      __ Bind(slow_path->exit_label());
+      __ mov(temp2, temp);
+      __ StoreIntoObject(instance_reg,
+                         FieldAddress(instance_reg, offset_in_bytes_),
+                         temp2);
+    } else {
+      __ LoadFieldFromOffset(temp, instance_reg, offset_in_bytes_);
+    }
+    switch (cid) {
+      case kDoubleCid:
+        __ Comment("UnboxedDoubleStoreInstanceFieldInstr");
+        __ StoreDFieldToOffset(value, temp, Double::value_offset());
+        break;
+      case kFloat32x4Cid:
+      case kFloat64x2Cid:
+        UNIMPLEMENTED();
+        break;
+      default:
+        UNREACHABLE();
+    }
+
+    return;
   }
 
   if (IsPotentialUnboxedStore()) {
+    const Register value_reg = locs()->in(1).reg();
     const Register temp = locs()->temp(0).reg();
     const Register temp2 = locs()->temp(1).reg();
+    const VRegister fpu_temp = locs()->temp(2).fpu_reg();
 
     Label store_pointer;
     Label store_double;
     Label store_float32x4;
     Label store_float64x2;
 
     __ LoadObject(temp, Field::ZoneHandle(field().raw()), PP);
 
     __ LoadFieldFromOffset(temp2, temp, Field::is_nullable_offset());
     __ CompareImmediate(temp2, kNullCid, PP);
@@ skipping 17 matching lines @@
     __ b(&store_float64x2, EQ);
 
     // Fall through.
     __ b(&store_pointer);
 
     if (!compiler->is_optimizing()) {
         locs()->live_registers()->Add(locs()->in(0));
         locs()->live_registers()->Add(locs()->in(1));
     }
 
-    // TODO(zra): Implement these when we add fpu loads and stores.
     {
       __ Bind(&store_double);
-      __ hlt(0);  // Unimplemented.
+      Label copy_double;
+      StoreInstanceFieldSlowPath* slow_path =
+          new StoreInstanceFieldSlowPath(this, compiler->double_class());
+      compiler->AddSlowPathCode(slow_path);
+
+      __ LoadFieldFromOffset(temp, instance_reg, offset_in_bytes_);
+      __ CompareObject(temp, Object::null_object(), PP);
+      __ b(&copy_double, NE);
+
+      __ TryAllocate(compiler->double_class(),
+                     slow_path->entry_label(),
+                     temp,
+                     temp2,
+                     PP);
+      __ Bind(slow_path->exit_label());
+      __ mov(temp2, temp);
+      __ StoreIntoObject(instance_reg,
+                         FieldAddress(instance_reg, offset_in_bytes_),
+                         temp2);
+      __ Bind(&copy_double);
+      __ LoadDFieldFromOffset(fpu_temp, value_reg, Double::value_offset());
+      __ StoreDFieldToOffset(fpu_temp, temp, Double::value_offset());
+      __ b(&skip_store);
     }
 
+    // TODO(zra): Implement these when we add simd loads and stores.
     {
       __ Bind(&store_float32x4);
       __ hlt(0);  // Unimplemented.
     }
 
     {
       __ Bind(&store_float64x2);
       __ hlt(0);  // Unimplemented.
     }
 
@@ skipping 97 matching lines @@
   ASSERT(locs()->in(kElementTypePos).reg() == R1);
   ASSERT(locs()->in(kLengthPos).reg() == R2);
   compiler->GenerateCall(token_pos(),
                          &StubCode::AllocateArrayLabel(),
                          PcDescriptors::kOther,
                          locs());
   ASSERT(locs()->out(0).reg() == R0);
 }
 
 
+class BoxDoubleSlowPath : public SlowPathCode {
+ public:
+  explicit BoxDoubleSlowPath(Instruction* instruction)
+      : instruction_(instruction) { }
+
+  virtual void EmitNativeCode(FlowGraphCompiler* compiler) {
+    __ Comment("BoxDoubleSlowPath");
+    __ Bind(entry_label());
+    const Class& double_class = compiler->double_class();
+    const Code& stub =
+        Code::Handle(StubCode::GetAllocationStubForClass(double_class));
+    const ExternalLabel label(double_class.ToCString(), stub.EntryPoint());
+
+    LocationSummary* locs = instruction_->locs();
+    locs->live_registers()->Remove(locs->out(0));
+
+    compiler->SaveLiveRegisters(locs);
+    compiler->GenerateCall(Scanner::kNoSourcePos,  // No token position.
+                           &label,
+                           PcDescriptors::kOther,
+                           locs);
+    __ mov(locs->out(0).reg(), R0);
+    compiler->RestoreLiveRegisters(locs);
+
+    __ b(exit_label());
+  }
+
+ private:
+  Instruction* instruction_;
+};
+
+
 LocationSummary* LoadFieldInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 1;
   const intptr_t kNumTemps = 0;
   LocationSummary* locs =
       new LocationSummary(
           kNumInputs, kNumTemps,
           (opt && !IsPotentialUnboxedLoad())
           ? LocationSummary::kNoCall
           : LocationSummary::kCallOnSlowPath);
 
   locs->set_in(0, Location::RequiresRegister());
 
   if (IsUnboxedLoad() && opt) {
-    // TODO(zra): Implement when we add fpu loads and stores.
-    UNIMPLEMENTED();
+    locs->AddTemp(Location::RequiresRegister());
   } else if (IsPotentialUnboxedLoad()) {
+    locs->AddTemp(opt ? Location::RequiresFpuRegister()
+                      : Location::FpuRegisterLocation(V1));
     locs->AddTemp(Location::RequiresRegister());
   }
   locs->set_out(0, Location::RequiresRegister());
   return locs;
 }
 
 
 void LoadFieldInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
   Register instance_reg = locs()->in(0).reg();
   if (IsUnboxedLoad() && compiler->is_optimizing()) {
-    UNIMPLEMENTED();
+    const VRegister result = locs()->out(0).fpu_reg();
+    const Register temp = locs()->temp(0).reg();
+    __ LoadFieldFromOffset(temp, instance_reg, offset_in_bytes());
+    const intptr_t cid = field()->UnboxedFieldCid();
+    switch (cid) {
+      case kDoubleCid:
+        __ Comment("UnboxedDoubleLoadFieldInstr");
+        __ LoadDFieldFromOffset(result, temp, Double::value_offset());
+        break;
+      case kFloat32x4Cid:
+      case kFloat64x2Cid:
+        UNIMPLEMENTED();
+        break;
+      default:
+        UNREACHABLE();
+    }
+    return;
   }
 
   Label done;
   Register result_reg = locs()->out(0).reg();
   if (IsPotentialUnboxedLoad()) {
-    const Register temp = locs()->temp(0).reg();
+    const Register temp = locs()->temp(1).reg();
+    const VRegister value = locs()->temp(0).fpu_reg();
 
     Label load_pointer;
     Label load_double;
     Label load_float32x4;
     Label load_float64x2;
 
     __ LoadObject(result_reg, Field::ZoneHandle(field()->raw()), PP);
 
     FieldAddress field_cid_operand(result_reg, Field::guarded_cid_offset());
     FieldAddress field_nullability_operand(result_reg,
@@ skipping 15 matching lines @@
     __ CompareImmediate(temp, kFloat64x2Cid, PP);
     __ b(&load_float64x2, EQ);
 
     // Fall through.
     __ b(&load_pointer);
 
     if (!compiler->is_optimizing()) {
       locs()->live_registers()->Add(locs()->in(0));
     }
 
-    // TODO(zra): Implement these when we add fpu loads and stores.
     {
       __ Bind(&load_double);
-      __ hlt(0);  // Unimplemented.
+      BoxDoubleSlowPath* slow_path = new BoxDoubleSlowPath(this);
+      compiler->AddSlowPathCode(slow_path);
+
+      __ TryAllocate(compiler->double_class(),
+                     slow_path->entry_label(),
+                     result_reg,
+                     temp,
+                     PP);
+      __ Bind(slow_path->exit_label());
+      __ LoadFieldFromOffset(temp, instance_reg, offset_in_bytes());
+      __ LoadDFieldFromOffset(value, temp, Double::value_offset());
+      __ StoreDFieldToOffset(value, result_reg, Double::value_offset());
+      __ b(&done);
     }
 
+    // TODO(zra): Implement these when we add simd loads and stores.
     {
       __ Bind(&load_float32x4);
       __ hlt(0);  // Unimplemented.
     }
 
     {
       __ Bind(&load_float64x2);
       __ hlt(0);  // Unimplemented.
     }
 
     __ Bind(&load_pointer);
   }
-  __ LoadFromOffset(
-      result_reg, instance_reg, offset_in_bytes() - kHeapObjectTag);
+  __ LoadFieldFromOffset(result_reg, instance_reg, offset_in_bytes());
   __ Bind(&done);
 }
 
 
 LocationSummary* InstantiateTypeInstr::MakeLocationSummary(bool opt) const {
   UNIMPLEMENTED();
   return NULL;
 }
 
 
@@ skipping 1205 matching lines @@
   compiler->GenerateCall(token_pos(),
                          &label,
                          PcDescriptors::kOther,
                          locs());
   __ Drop(ArgumentCount());  // Discard arguments.
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM64