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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 // A Disassembler object is used to disassemble a block of code instruction by | 5 // A Disassembler object is used to disassemble a block of code instruction by |
6 // instruction. The default implementation of the NameConverter object can be | 6 // instruction. The default implementation of the NameConverter object can be |
7 // overriden to modify register names or to do symbol lookup on addresses. | 7 // overriden to modify register names or to do symbol lookup on addresses. |
8 // | 8 // |
9 // The example below will disassemble a block of code and print it to stdout. | 9 // The example below will disassemble a block of code and print it to stdout. |
10 // | 10 // |
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555 case SRAW: { | 555 case SRAW: { |
556 Format(instr, "sraw'. 'ra, 'rs, 'rb"); | 556 Format(instr, "sraw'. 'ra, 'rs, 'rb"); |
557 return; | 557 return; |
558 } | 558 } |
559 #if V8_TARGET_ARCH_PPC64 | 559 #if V8_TARGET_ARCH_PPC64 |
560 case SRAD: { | 560 case SRAD: { |
561 Format(instr, "srad'. 'ra, 'rs, 'rb"); | 561 Format(instr, "srad'. 'ra, 'rs, 'rb"); |
562 return; | 562 return; |
563 } | 563 } |
564 #endif | 564 #endif |
| 565 case MODSW: { |
| 566 Format(instr, "modsw 'rt, 'ra, 'rb"); |
| 567 return; |
| 568 } |
| 569 case MODUW: { |
| 570 Format(instr, "moduw 'rt, 'ra, 'rb"); |
| 571 return; |
| 572 } |
| 573 #if V8_TARGET_ARCH_PPC64 |
| 574 case MODSD: { |
| 575 Format(instr, "modsd 'rt, 'ra, 'rb"); |
| 576 return; |
| 577 } |
| 578 case MODUD: { |
| 579 Format(instr, "modud 'rt, 'ra, 'rb"); |
| 580 return; |
| 581 } |
| 582 #endif |
565 case SRAWIX: { | 583 case SRAWIX: { |
566 Format(instr, "srawi'. 'ra,'rs,'sh"); | 584 Format(instr, "srawi'. 'ra,'rs,'sh"); |
567 return; | 585 return; |
568 } | 586 } |
569 case EXTSH: { | 587 case EXTSH: { |
570 Format(instr, "extsh'. 'ra, 'rs"); | 588 Format(instr, "extsh'. 'ra, 'rs"); |
571 return; | 589 return; |
572 } | 590 } |
573 #if V8_TARGET_ARCH_PPC64 | 591 #if V8_TARGET_ARCH_PPC64 |
574 case EXTSW: { | 592 case EXTSW: { |
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1491 pc += d.InstructionDecode(buffer, pc); | 1509 pc += d.InstructionDecode(buffer, pc); |
1492 v8::internal::PrintF(f, "%p %08x %s\n", static_cast<void*>(prev_pc), | 1510 v8::internal::PrintF(f, "%p %08x %s\n", static_cast<void*>(prev_pc), |
1493 *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); | 1511 *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); |
1494 } | 1512 } |
1495 } | 1513 } |
1496 | 1514 |
1497 | 1515 |
1498 } // namespace disasm | 1516 } // namespace disasm |
1499 | 1517 |
1500 #endif // V8_TARGET_ARCH_PPC | 1518 #endif // V8_TARGET_ARCH_PPC |
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