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1 // Copyright 2006-2013 the V8 project authors. All rights reserved. | 1 // Copyright 2006-2013 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 // This module contains the architecture-specific code. This make the rest of | 5 // This module contains the architecture-specific code. This make the rest of |
6 // the code less dependent on differences between different processor | 6 // the code less dependent on differences between different processor |
7 // architecture. | 7 // architecture. |
8 // The classes have the same definition for all architectures. The | 8 // The classes have the same definition for all architectures. The |
9 // implementation for a particular architecture is put in cpu_<arch>.cc. | 9 // implementation for a particular architecture is put in cpu_<arch>.cc. |
10 // The build system then uses the implementation for the target architecture. | 10 // The build system then uses the implementation for the target architecture. |
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62 | 62 |
63 // Denver-specific part code | 63 // Denver-specific part code |
64 static const int NVIDIA_DENVER_V10 = 0x002; | 64 static const int NVIDIA_DENVER_V10 = 0x002; |
65 | 65 |
66 // PPC-specific part codes | 66 // PPC-specific part codes |
67 enum { | 67 enum { |
68 PPC_POWER5, | 68 PPC_POWER5, |
69 PPC_POWER6, | 69 PPC_POWER6, |
70 PPC_POWER7, | 70 PPC_POWER7, |
71 PPC_POWER8, | 71 PPC_POWER8, |
| 72 PPC_POWER9, |
72 PPC_G4, | 73 PPC_G4, |
73 PPC_G5, | 74 PPC_G5, |
74 PPC_PA6T | 75 PPC_PA6T |
75 }; | 76 }; |
76 | 77 |
77 // General features | 78 // General features |
78 bool has_fpu() const { return has_fpu_; } | 79 bool has_fpu() const { return has_fpu_; } |
79 int icache_line_size() const { return icache_line_size_; } | 80 int icache_line_size() const { return icache_line_size_; } |
80 int dcache_line_size() const { return dcache_line_size_; } | 81 int dcache_line_size() const { return dcache_line_size_; } |
81 static const int UNKNOWN_CACHE_LINE_SIZE = 0; | 82 static const int UNKNOWN_CACHE_LINE_SIZE = 0; |
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152 bool has_vfp3_; | 153 bool has_vfp3_; |
153 bool has_vfp3_d32_; | 154 bool has_vfp3_d32_; |
154 bool is_fp64_mode_; | 155 bool is_fp64_mode_; |
155 bool has_non_stop_time_stamp_counter_; | 156 bool has_non_stop_time_stamp_counter_; |
156 }; | 157 }; |
157 | 158 |
158 } // namespace base | 159 } // namespace base |
159 } // namespace v8 | 160 } // namespace v8 |
160 | 161 |
161 #endif // V8_BASE_CPU_H_ | 162 #endif // V8_BASE_CPU_H_ |
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