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Side by Side Diff: src/compiler/mips/instruction-selector-mips.cc

Issue 2623633003: [Atomics] Make Atomics.exchange a builtin using TF (Closed)
Patch Set: remove 0 extend for arm Created 3 years, 9 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/base/adapters.h" 5 #include "src/base/adapters.h"
6 #include "src/base/bits.h" 6 #include "src/base/bits.h"
7 #include "src/compiler/instruction-selector-impl.h" 7 #include "src/compiler/instruction-selector-impl.h"
8 #include "src/compiler/node-matchers.h" 8 #include "src/compiler/node-matchers.h"
9 #include "src/compiler/node-properties.h" 9 #include "src/compiler/node-properties.h"
10 10
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1878 } else { 1878 } else {
1879 InstructionOperand addr_reg = g.TempRegister(); 1879 InstructionOperand addr_reg = g.TempRegister();
1880 Emit(kMipsAdd | AddressingModeField::encode(kMode_None), addr_reg, 1880 Emit(kMipsAdd | AddressingModeField::encode(kMode_None), addr_reg,
1881 g.UseRegister(index), g.UseRegister(base)); 1881 g.UseRegister(index), g.UseRegister(base));
1882 // Emit desired store opcode, using temp addr_reg. 1882 // Emit desired store opcode, using temp addr_reg.
1883 Emit(opcode | AddressingModeField::encode(kMode_MRI), g.NoOutput(), 1883 Emit(opcode | AddressingModeField::encode(kMode_MRI), g.NoOutput(),
1884 addr_reg, g.TempImmediate(0), g.UseRegisterOrImmediateZero(value)); 1884 addr_reg, g.TempImmediate(0), g.UseRegisterOrImmediateZero(value));
1885 } 1885 }
1886 } 1886 }
1887 1887
1888 void InstructionSelector::VisitAtomicExchange(Node* node) { UNIMPLEMENTED(); }
1889
1888 // static 1890 // static
1889 MachineOperatorBuilder::Flags 1891 MachineOperatorBuilder::Flags
1890 InstructionSelector::SupportedMachineOperatorFlags() { 1892 InstructionSelector::SupportedMachineOperatorFlags() {
1891 MachineOperatorBuilder::Flags flags = MachineOperatorBuilder::kNoFlags; 1893 MachineOperatorBuilder::Flags flags = MachineOperatorBuilder::kNoFlags;
1892 if ((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) && 1894 if ((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
1893 IsFp64Mode()) { 1895 IsFp64Mode()) {
1894 flags |= MachineOperatorBuilder::kFloat64RoundDown | 1896 flags |= MachineOperatorBuilder::kFloat64RoundDown |
1895 MachineOperatorBuilder::kFloat64RoundUp | 1897 MachineOperatorBuilder::kFloat64RoundUp |
1896 MachineOperatorBuilder::kFloat64RoundTruncate | 1898 MachineOperatorBuilder::kFloat64RoundTruncate |
1897 MachineOperatorBuilder::kFloat64RoundTiesEven; 1899 MachineOperatorBuilder::kFloat64RoundTiesEven;
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1920 DCHECK(IsMipsArchVariant(kLoongson) || IsMipsArchVariant(kMips32r1) || 1922 DCHECK(IsMipsArchVariant(kLoongson) || IsMipsArchVariant(kMips32r1) ||
1921 IsMipsArchVariant(kMips32r2)); 1923 IsMipsArchVariant(kMips32r2));
1922 return MachineOperatorBuilder::AlignmentRequirements:: 1924 return MachineOperatorBuilder::AlignmentRequirements::
1923 NoUnalignedAccessSupport(); 1925 NoUnalignedAccessSupport();
1924 } 1926 }
1925 } 1927 }
1926 1928
1927 } // namespace compiler 1929 } // namespace compiler
1928 } // namespace internal 1930 } // namespace internal
1929 } // namespace v8 1931 } // namespace v8
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