Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(798)

Side by Side Diff: src/compiler/ia32/instruction-codes-ia32.h

Issue 2623633003: [Atomics] Make Atomics.exchange a builtin using TF (Closed)
Patch Set: remove 0 extend for arm Created 3 years, 9 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
OLDNEW
1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ 5 #ifndef V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_
6 #define V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ 6 #define V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 92 matching lines...) Expand 10 before | Expand all | Expand 10 after
103 V(IA32Movl) \ 103 V(IA32Movl) \
104 V(IA32Movss) \ 104 V(IA32Movss) \
105 V(IA32Movsd) \ 105 V(IA32Movsd) \
106 V(IA32BitcastFI) \ 106 V(IA32BitcastFI) \
107 V(IA32BitcastIF) \ 107 V(IA32BitcastIF) \
108 V(IA32Lea) \ 108 V(IA32Lea) \
109 V(IA32Push) \ 109 V(IA32Push) \
110 V(IA32PushFloat32) \ 110 V(IA32PushFloat32) \
111 V(IA32PushFloat64) \ 111 V(IA32PushFloat64) \
112 V(IA32Poke) \ 112 V(IA32Poke) \
113 V(IA32StackCheck) \ 113 V(IA32StackCheck)
114 V(IA32Xchgb) \
115 V(IA32Xchgw) \
116 V(IA32Xchgl)
117 114
118 // Addressing modes represent the "shape" of inputs to an instruction. 115 // Addressing modes represent the "shape" of inputs to an instruction.
119 // Many instructions support multiple addressing modes. Addressing modes 116 // Many instructions support multiple addressing modes. Addressing modes
120 // are encoded into the InstructionCode of the instruction and tell the 117 // are encoded into the InstructionCode of the instruction and tell the
121 // code generator after register allocation which assembler method to call. 118 // code generator after register allocation which assembler method to call.
122 // 119 //
123 // We use the following local notation for addressing modes: 120 // We use the following local notation for addressing modes:
124 // 121 //
125 // M = memory operand 122 // M = memory operand
126 // R = base register 123 // R = base register
(...skipping 19 matching lines...) Expand all
146 V(M2I) /* [ %r2*2 + K] */ \ 143 V(M2I) /* [ %r2*2 + K] */ \
147 V(M4I) /* [ %r2*4 + K] */ \ 144 V(M4I) /* [ %r2*4 + K] */ \
148 V(M8I) /* [ %r2*8 + K] */ \ 145 V(M8I) /* [ %r2*8 + K] */ \
149 V(MI) /* [ K] */ 146 V(MI) /* [ K] */
150 147
151 } // namespace compiler 148 } // namespace compiler
152 } // namespace internal 149 } // namespace internal
153 } // namespace v8 150 } // namespace v8
154 151
155 #endif // V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ 152 #endif // V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_
OLDNEW

Powered by Google App Engine
This is Rietveld 408576698