[Atomics] Make Atomics.exchange a builtin using TF

src/compiler/x64/instruction-selector-x64.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <algorithm>
 
 #include "src/base/adapters.h"
 #include "src/compiler/instruction-selector-impl.h"
 #include "src/compiler/node-matchers.h"
 #include "src/compiler/node-properties.h"
@@ skipping 2372 matching lines @@
     addressing_mode = kMode_MRI;
   } else {
     inputs[input_count++] = g.UseUniqueRegister(index);
     addressing_mode = kMode_MR1;
   }
   inputs[input_count++] = g.UseUniqueRegister(value);
   InstructionCode code = opcode | AddressingModeField::encode(addressing_mode);
   Emit(code, 0, static_cast<InstructionOperand*>(nullptr), input_count, inputs);
 }
 
+void InstructionSelector::VisitAtomicExchange(Node* node) {
+  X64OperandGenerator g(this);
+  Node* base = node->InputAt(0);
+  Node* index = node->InputAt(1);
+  Node* value = node->InputAt(2);
+
+  MachineType type = AtomicExchangeRepresentationOf(node->op());
+  ArchOpcode opcode = kArchNop;
+  if (type == MachineType::Uint8() || type == MachineType::Int8()) {

[binji, 2017/01/13 00:08:50]

Looks like it is more common to do a switch on the MachineRepresentation.

[aseemgarg, 2017/01/14 01:48:19]

Changed a little. We can't use MachineRepresentation now as signed and unsigned
have different behaviors.

[binji, 2017/01/17 21:45:50]

Take a look at GetLoadOpcode/VisitCheckedLoad/VisitChangeInt32ToInt64, etc., it
looks like it is common to use a switch on MachineRepresentation, then check
rep.IsSigned().

+    opcode = kX64Xchgb;
+  } else if (type == MachineType::Uint16() || type == MachineType::Int16()) {
+    opcode = kX64Xchgw;
+  } else if (type == MachineType::Uint32() || type == MachineType::Int32()) {
+    opcode = kX64Xchgl;
+  } else {
+    UNREACHABLE();
+    return;
+  }
+  InstructionOperand outputs[1];
+  outputs[0] = g.DefineAsRegister(node);
+  AddressingMode addressing_mode;
+  InstructionOperand inputs[4];
+  size_t input_count = 0;
+  inputs[input_count++] = g.UseUniqueRegister(base);
+  if (g.CanBeImmediate(index)) {
+    inputs[input_count++] = g.UseImmediate(index);
+    addressing_mode = kMode_MRI;
+  } else {
+    inputs[input_count++] = g.UseUniqueRegister(index);
+    addressing_mode = kMode_MR1;
+  }
+  inputs[input_count++] = g.UseUniqueRegister(value);
+  InstructionCode code = opcode | AddressingModeField::encode(addressing_mode);
+  Emit(code, 1, outputs, input_count, inputs);
+}
+
 void InstructionSelector::VisitCreateInt32x4(Node* node) {
   X64OperandGenerator g(this);
   Emit(kX64Int32x4Create, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
 }
 
 void InstructionSelector::VisitInt32x4ExtractLane(Node* node) {
   X64OperandGenerator g(this);
   int32_t lane = OpParameter<int32_t>(node);
   Emit(kX64Int32x4ExtractLane, g.DefineAsRegister(node),
        g.UseRegister(node->InputAt(0)), g.UseImmediate(lane));
@@ skipping 45 matching lines @@
 // static
 MachineOperatorBuilder::AlignmentRequirements
 InstructionSelector::AlignmentRequirements() {
   return MachineOperatorBuilder::AlignmentRequirements::
       FullUnalignedAccessSupport();
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8