Adds arm64 double arithmetic instructions.

runtime/vm/constants_arm64.h

Index: runtime/vm/constants_arm64.h
===================================================================
--- runtime/vm/constants_arm64.h	(revision 35810)
+++ runtime/vm/constants_arm64.h	(working copy)
@@ -384,6 +384,7 @@
   ConditionalSelectMask = 0x1fe00000,
   ConditionalSelectFixed = DPRegisterFixed | B28 | B23,
   CSEL = ConditionalSelectFixed,
+  CSINC = ConditionalSelectFixed | B10,
 };
 
 // C3.5.8
@@ -420,6 +421,14 @@
   BICS = LogicalShiftFixed | B30 | B29 | B21,
 };
 
+// C.3.6.22
+enum FPCompareOp {
+  FPCompareMask = 0xffa0fc07,
+  FPCompareFixed = FPFixed | B21 | B13,
+  FCMPD = FPCompareFixed | B22,
+  FCMPZD = FPCompareFixed | B22 | B3,
+};
+
 // C3.6.25
 enum FPOneSourceOp {
   FPOneSourceMask = 0x5f207c00,
@@ -427,6 +436,16 @@
   FMOVDD = FPOneSourceFixed | B22,
 };
 
+// C3.6.26
+enum FPTwoSourceOp {
+  FPTwoSourceMask = 0xff200c00,
+  FPTwoSourceFixed = FPFixed | B21 | B11,
+  FMULD = FPTwoSourceFixed | B22,
+  FDIVD = FPTwoSourceFixed | B22 | B12,
+  FADDD = FPTwoSourceFixed | B22 | B13,
+  FSUBD = FPTwoSourceFixed | B22 | B13 | B12,
+};
+
 // C3.6.28
 enum FPImmOp {
   FPImmMask = 0x5f201c00,
@@ -435,12 +454,14 @@
   FMOVDI = FPImmFixed | B22,
 };
 
-// C3.6.29
+// C3.6.30
 enum FPIntCvtOp {
   FPIntCvtMask = 0x5f20fc00,
   FPIntCvtFixed = FPFixed | B21,
   FMOVRD = FPIntCvtFixed | B31 | B22 | B18 | B17,
   FMOVDR = FPIntCvtFixed | B31 | B22 | B18 | B17 | B16,
+  FCVTZDS = FPIntCvtFixed | B31 | B22 | B20 | B19,
+  SCVTFD = FPIntCvtFixed | B31 | B22 | B17,
 };
 
 
@@ -471,8 +492,10 @@
 _V(MiscDP3Source)                                                              \
 _V(LogicalShift)                                                               \
 _V(FPOneSource)                                                                \
+_V(FPTwoSource)                                                                \
 _V(FPImm)                                                                      \
 _V(FPIntCvt)                                                                   \
+_V(FPCompare)                                                                  \
 
 
 enum Shift {
@@ -534,6 +557,8 @@
   kVdBits = 5,
   kVnShift = 5,
   kVnBits = 5,
+  kVmShift = 16,
+  kVmBits = 5,
   kVtShift = 0,
   kVtBits = 5,
 
@@ -704,6 +729,8 @@
                                         Bits(kVdShift, kVdBits)); }
   inline VRegister VnField() const { return static_cast<VRegister>(
                                         Bits(kVnShift, kVnBits)); }
+  inline VRegister VmField() const { return static_cast<VRegister>(
+                                        Bits(kVmShift, kVmBits)); }
   inline VRegister VtField() const { return static_cast<VRegister>(
                                         Bits(kVtShift, kVtBits)); }