Adds arm64 double arithmetic instructions.

runtime/vm/constants_arm64.h

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_CONSTANTS_ARM64_H_
 #define VM_CONSTANTS_ARM64_H_
 
 #include "platform/assert.h"
 
 namespace dart {
@@ skipping 175 matching lines @@
   LS =  9,  // unsigned lower or same
   GE = 10,  // signed greater than or equal
   LT = 11,  // signed less than
   GT = 12,  // signed greater than
   LE = 13,  // signed less than or equal
   AL = 14,  // always (unconditional)
   NV = 15,  // special condition (refer to section C1.2.3)
   kMaxCondition = 16,
 };
 
+static inline Condition InvertCondition(Condition c) {
+  const int32_t i = static_cast<int32_t>(c) ^ 0x1;
+  return static_cast<Condition>(i);
+}
+
 enum Bits {
   B0  =  (1 << 0), B1  =  (1 << 1), B2  =  (1 << 2), B3  =  (1 << 3),
   B4  =  (1 << 4), B5  =  (1 << 5), B6  =  (1 << 6), B7  =  (1 << 7),
   B8  =  (1 << 8), B9  =  (1 << 9), B10 = (1 << 10), B11 = (1 << 11),
   B12 = (1 << 12), B13 = (1 << 13), B14 = (1 << 14), B15 = (1 << 15),
   B16 = (1 << 16), B17 = (1 << 17), B18 = (1 << 18), B19 = (1 << 19),
   B20 = (1 << 20), B21 = (1 << 21), B22 = (1 << 22), B23 = (1 << 23),
   B24 = (1 << 24), B25 = (1 << 25), B26 = (1 << 26), B27 = (1 << 27),
   B28 = (1 << 28), B29 = (1 << 29), B30 = (1 << 30), B31 = (1 << 31),
 };
@@ skipping 171 matching lines @@
   AddSubShiftExtFixed = DPRegisterFixed | B24,
   ADD = AddSubShiftExtFixed,
   SUB = AddSubShiftExtFixed | B30,
 };
 
 // C3.5.6
 enum ConditionalSelectOp {
   ConditionalSelectMask = 0x1fe00000,
   ConditionalSelectFixed = DPRegisterFixed | B28 | B23,
   CSEL = ConditionalSelectFixed,
+  CSINC = ConditionalSelectFixed | B10,
 };
 
 // C3.5.8
 enum MiscDP2SourceOp {
   MiscDP2SourceMask = 0x5fe00000,
   MiscDP2SourceFixed = DPRegisterFixed | B28 | B23 | B22,
   UDIV = MiscDP2SourceFixed | B11,
   SDIV = MiscDP2SourceFixed | B11 | B10,
   LSLV = MiscDP2SourceFixed | B13,
   LSRV = MiscDP2SourceFixed | B13 | B10,
@@ skipping 16 matching lines @@
   AND = LogicalShiftFixed,
   BIC = LogicalShiftFixed | B21,
   ORR = LogicalShiftFixed | B29,
   ORN = LogicalShiftFixed | B29 | B21,
   EOR = LogicalShiftFixed | B30,
   EON = LogicalShiftFixed | B30 | B21,
   ANDS = LogicalShiftFixed | B30 | B29,
   BICS = LogicalShiftFixed | B30 | B29 | B21,
 };
 
+// C.3.6.22
+enum FPCompareOp {
+  FPCompareMask = 0xffa0fc07,
+  FPCompareFixed = FPFixed | B21 | B13,
+  FCMPD = FPCompareFixed | B22,
+  FCMPZD = FPCompareFixed | B22 | B3,
+};
+
 // C3.6.25
 enum FPOneSourceOp {
   FPOneSourceMask = 0x5f207c00,
   FPOneSourceFixed = FPFixed | B21 | B14,
   FMOVDD = FPOneSourceFixed | B22,
 };
 
+// C3.6.26
+enum FPTwoSourceOp {
+  FPTwoSourceMask = 0xff200c00,
+  FPTwoSourceFixed = FPFixed | B21 | B11,
+  FMULD = FPTwoSourceFixed | B22,
+  FDIVD = FPTwoSourceFixed | B22 | B12,
+  FADDD = FPTwoSourceFixed | B22 | B13,
+  FSUBD = FPTwoSourceFixed | B22 | B13 | B12,
+};
+
 // C3.6.28
 enum FPImmOp {
   FPImmMask = 0x5f201c00,
   FPImmFixed = FPFixed | B21 | B12,
   FMOVSI = FPImmFixed,
   FMOVDI = FPImmFixed | B22,
 };
 
-// C3.6.29
+// C3.6.30
 enum FPIntCvtOp {
   FPIntCvtMask = 0x5f20fc00,
   FPIntCvtFixed = FPFixed | B21,
   FMOVRD = FPIntCvtFixed | B31 | B22 | B18 | B17,
   FMOVDR = FPIntCvtFixed | B31 | B22 | B18 | B17 | B16,
+  FCVTZDS = FPIntCvtFixed | B31 | B22 | B20 | B19,
+  SCVTFD = FPIntCvtFixed | B31 | B22 | B17,
 };
 
 
 #define APPLY_OP_LIST(_V)                                                      \
 _V(DPImmediate)                                                                \
 _V(CompareBranch)                                                              \
 _V(LoadStore)                                                                  \
 _V(DPRegister)                                                                 \
 _V(DPSimd1)                                                                    \
 _V(DPSimd2)                                                                    \
@@ skipping 10 matching lines @@
 _V(AddSubImm)                                                                  \
 _V(LogicalImm)                                                                 \
 _V(MoveWide)                                                                   \
 _V(PCRel)                                                                      \
 _V(AddSubShiftExt)                                                             \
 _V(ConditionalSelect)                                                          \
 _V(MiscDP2Source)                                                              \
 _V(MiscDP3Source)                                                              \
 _V(LogicalShift)                                                               \
 _V(FPOneSource)                                                                \
+_V(FPTwoSource)                                                                \
 _V(FPImm)                                                                      \
 _V(FPIntCvt)                                                                   \
+_V(FPCompare)                                                                  \
 
 
 enum Shift {
   kNoShift = -1,
   LSL = 0,  // Logical shift left
   LSR = 1,  // Logical shift right
   ASR = 2,  // Arithmetic shift right
   ROR = 3,  // Rotate right
   kMaxShift = 4,
 };
@@ skipping 41 matching lines @@
   kRmShift = 16,
   kRmBits = 5,
   kRtShift = 0,
   kRtBits = 5,
 
   // V Registers.
   kVdShift = 0,
   kVdBits = 5,
   kVnShift = 5,
   kVnBits = 5,
+  kVmShift = 16,
+  kVmBits = 5,
   kVtShift = 0,
   kVtBits = 5,
 
   // Immediates.
   kImm3Shift = 10,
   kImm3Bits = 3,
   kImm6Shift = 10,
   kImm6Bits = 6,
   kImm8Shift = 13,
   kImm8Bits = 8,
@@ skipping 150 matching lines @@
                                         Bits(kRaShift, kRaBits)); }
   inline Register RmField() const { return static_cast<Register>(
                                         Bits(kRmShift, kRmBits)); }
   inline Register RtField() const { return static_cast<Register>(
                                         Bits(kRtShift, kRtBits)); }
 
   inline VRegister VdField() const { return static_cast<VRegister>(
                                         Bits(kVdShift, kVdBits)); }
   inline VRegister VnField() const { return static_cast<VRegister>(
                                         Bits(kVnShift, kVnBits)); }
+  inline VRegister VmField() const { return static_cast<VRegister>(
+                                        Bits(kVmShift, kVmBits)); }
   inline VRegister VtField() const { return static_cast<VRegister>(
                                         Bits(kVtShift, kVtBits)); }
 
   // Immediates
   inline int Imm3Field() const { return Bits(kImm3Shift, kImm3Bits); }
   inline int Imm6Field() const { return Bits(kImm6Shift, kImm6Bits); }
   inline int Imm8Field() const { return Bits(kImm8Shift, kImm8Bits); }
   inline int Imm9Field() const { return Bits(kImm9Shift, kImm9Bits); }
   // Sign-extended Imm9Field()
   inline int64_t SImm9Field() const {
@@ skipping 158 matching lines @@
   static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); }
 
  private:
   DISALLOW_ALLOCATION();
   DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
 };
 
 }  // namespace dart
 
 #endif  // VM_CONSTANTS_ARM64_H_