Adds arm64 double arithmetic instructions.

runtime/vm/assembler_arm64.h

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_ARM64_H_
 #define VM_ASSEMBLER_ARM64_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_arm64.h directly; use assembler.h instead.
 #endif
@@ skipping 542 matching lines @@
     }
   }
   void str(Register rt, Address a, OperandSize sz = kDoubleWord) {
     EmitLoadStoreReg(STR, rt, a, sz);
   }
 
   // Conditional select.
   void csel(Register rd, Register rn, Register rm, Condition cond) {
     EmitCoditionalSelect(CSEL, rd, rn, rm, cond, kDoubleWord);
   }
+  void csinc(Register rd, Register rn, Register rm, Condition cond) {
+    EmitCoditionalSelect(CSINC, rd, rn, rm, cond, kDoubleWord);
+  }
+  void cinc(Register rd, Register rn, Condition cond) {
+    csinc(rd, rn, rn, InvertCondition(cond));
+  }
+  void cset(Register rd, Condition cond) {
+    csinc(rd, ZR, ZR, InvertCondition(cond));
+  }
 
   // Comparison.
   // rn cmp o.
   // For add and sub, to use SP for rn, o must be of type Operand::Extend.
   // For an unmodified rm in this case, use Operand(rm, UXTX, 0);
   void cmp(Register rn, Operand o) {
     subs(ZR, rn, o);
   }
   // rn cmp -o.
   void cmn(Register rn, Operand o) {
@@ skipping 43 matching lines @@
     const uint8_t bit30 = (imm64 >> 48) & 0xf;
     const uint8_t imm8 = (bit7 << 7) | (bit6 << 6) | (bit54 << 4) | bit30;
     const int64_t expimm8 = Instr::VFPExpandImm(imm8);
     if (imm64 != expimm8) {
       return false;
     }
     EmitFPImm(FMOVDI, vd, imm8);
     return true;
   }
   void fmovdr(VRegister vd, Register rn) {
-    EmitFPIntCvtOp(FMOVDR, static_cast<Register>(vd), rn);
+    ASSERT(rn != R31);
+    ASSERT(rn != SP);
+    const Register crn = ConcreteRegister(rn);
+    EmitFPIntCvtOp(FMOVDR, static_cast<Register>(vd), crn);
   }
   void fmovrd(Register rd, VRegister vn) {
-    EmitFPIntCvtOp(FMOVRD, rd, static_cast<Register>(vn));
+    ASSERT(rd != R31);
+    ASSERT(rd != SP);
+    const Register crd = ConcreteRegister(rd);
+    EmitFPIntCvtOp(FMOVRD, crd, static_cast<Register>(vn));
+  }
+  void scvtfd(VRegister vd, Register rn) {
+    ASSERT(rn != R31);
+    ASSERT(rn != SP);
+    const Register crn = ConcreteRegister(rn);
+    EmitFPIntCvtOp(SCVTFD, static_cast<Register>(vd), crn);
+  }
+  void fcvtzds(Register rd, VRegister vn) {
+    ASSERT(rd != R31);
+    ASSERT(rd != SP);
+    const Register crd = ConcreteRegister(rd);
+    EmitFPIntCvtOp(FCVTZDS, crd, static_cast<Register>(vn));
   }
   void fmovdd(VRegister vd, VRegister vn) {
     EmitFPOneSourceOp(FMOVDD, vd, vn);
   }
-
   void fldrd(VRegister vt, Address a) {
     ASSERT(a.type() != Address::PCOffset);
     EmitLoadStoreReg(FLDR, static_cast<Register>(vt), a, kDoubleWord);
   }
   void fstrd(VRegister vt, Address a) {
     ASSERT(a.type() != Address::PCOffset);
     EmitLoadStoreReg(FSTR, static_cast<Register>(vt), a, kDoubleWord);
   }
+  void fcmpd(VRegister vn, VRegister vm) {
+    EmitFPCompareOp(FCMPD, vn, vm);
+  }
+  void fcmpzd(VRegister vn) {
+    EmitFPCompareOp(FCMPZD, vn, V0);
+  }
+  void fmuld(VRegister vd, VRegister vn, VRegister vm) {
+    EmitFPTwoSourceOp(FMULD, vd, vn, vm);
+  }
+  void fdivd(VRegister vd, VRegister vn, VRegister vm) {
+    EmitFPTwoSourceOp(FDIVD, vd, vn, vm);
+  }
+  void faddd(VRegister vd, VRegister vn, VRegister vm) {
+    EmitFPTwoSourceOp(FADDD, vd, vn, vm);
+  }
+  void fsubd(VRegister vd, VRegister vn, VRegister vm) {
+    EmitFPTwoSourceOp(FSUBD, vd, vn, vm);
+  }
 
   // Aliases.
   void mov(Register rd, Register rn) {
     if ((rd == SP) || (rn == SP)) {
       add(rd, rn, Operand(0));
     } else {
       orr(rd, ZR, Operand(rn));
     }
   }
   void mvn(Register rd, Register rm) {
@@ skipping 542 matching lines @@
   void EmitFPIntCvtOp(FPIntCvtOp op, Register rd, Register rn) {
     const int32_t encoding =
         op |
         (static_cast<int32_t>(rd) << kRdShift) |
         (static_cast<int32_t>(rn) << kRnShift);
     Emit(encoding);
   }
 
   void EmitFPOneSourceOp(FPOneSourceOp op, VRegister vd, VRegister vn) {
     const int32_t encoding =
-      op |
-      (static_cast<int32_t>(vd) << kVdShift) |
-      (static_cast<int32_t>(vn) << kVnShift);
+        op |
+        (static_cast<int32_t>(vd) << kVdShift) |
+        (static_cast<int32_t>(vn) << kVnShift);
+    Emit(encoding);
+  }
+
+  void EmitFPTwoSourceOp(FPTwoSourceOp op,
+                         VRegister vd, VRegister vn, VRegister vm) {
+    const int32_t encoding =
+        op |
+        (static_cast<int32_t>(vd) << kVdShift) |
+        (static_cast<int32_t>(vn) << kVnShift) |
+        (static_cast<int32_t>(vm) << kVmShift);
+    Emit(encoding);
+  }
+
+  void EmitFPCompareOp(FPCompareOp op, VRegister vn, VRegister vm) {
+    const int32_t encoding =
+        op |
+        (static_cast<int32_t>(vn) << kVnShift) |
+        (static_cast<int32_t>(vm) << kVmShift);
     Emit(encoding);
   }
 
   void StoreIntoObjectFilter(Register object, Register value, Label* no_update);
 
   // Shorter filtering sequence that assumes that value is not a smi.
   void StoreIntoObjectFilterNoSmi(Register object,
                                   Register value,
                                   Label* no_update);
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_ARM64_H_