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Side by Side Diff: runtime/vm/intermediate_language_arm.cc

Issue 262333007: Adds arm64 double arithmetic instructions. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 6 years, 7 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM. 5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM.
6 #if defined(TARGET_ARCH_ARM) 6 #if defined(TARGET_ARCH_ARM)
7 7
8 #include "vm/intermediate_language.h" 8 #include "vm/intermediate_language.h"
9 9
10 #include "vm/cpu.h" 10 #include "vm/cpu.h"
(...skipping 273 matching lines...) Expand 10 before | Expand all | Expand 10 after
284 locs->set_out(0, Location::RequiresFpuRegister()); 284 locs->set_out(0, Location::RequiresFpuRegister());
285 locs->set_temp(0, Location::RequiresRegister()); 285 locs->set_temp(0, Location::RequiresRegister());
286 return locs; 286 return locs;
287 } 287 }
288 288
289 289
290 void UnboxedConstantInstr::EmitNativeCode(FlowGraphCompiler* compiler) { 290 void UnboxedConstantInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
291 // The register allocator drops constant definitions that have no uses. 291 // The register allocator drops constant definitions that have no uses.
292 if (!locs()->out(0).IsInvalid()) { 292 if (!locs()->out(0).IsInvalid()) {
293 if (Utils::DoublesBitEqual(Double::Cast(value()).value(), 0.0)) { 293 if (Utils::DoublesBitEqual(Double::Cast(value()).value(), 0.0)) {
294 QRegister dst = locs()->out(0).fpu_reg(); 294 const QRegister dst = locs()->out(0).fpu_reg();
295 __ veorq(dst, dst, dst); 295 __ veorq(dst, dst, dst);
296 } else { 296 } else {
297 DRegister dst = EvenDRegisterOf(locs()->out(0).fpu_reg()); 297 const DRegister dst = EvenDRegisterOf(locs()->out(0).fpu_reg());
298 Register temp = locs()->temp(0).reg(); 298 const Register temp = locs()->temp(0).reg();
299 __ LoadDImmediate(dst, Double::Cast(value()).value(), temp); 299 __ LoadDImmediate(dst, Double::Cast(value()).value(), temp);
300 } 300 }
301 } 301 }
302 } 302 }
303 303
304 304
305 LocationSummary* AssertAssignableInstr::MakeLocationSummary(bool opt) const { 305 LocationSummary* AssertAssignableInstr::MakeLocationSummary(bool opt) const {
306 const intptr_t kNumInputs = 3; 306 const intptr_t kNumInputs = 3;
307 const intptr_t kNumTemps = 0; 307 const intptr_t kNumTemps = 0;
308 LocationSummary* summary = 308 LocationSummary* summary =
(...skipping 3293 matching lines...) Expand 10 before | Expand all | Expand 10 after
3602 LocationSummary* summary = 3602 LocationSummary* summary =
3603 new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall); 3603 new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
3604 summary->set_in(0, Location::RequiresFpuRegister()); 3604 summary->set_in(0, Location::RequiresFpuRegister());
3605 summary->set_in(1, Location::RequiresFpuRegister()); 3605 summary->set_in(1, Location::RequiresFpuRegister());
3606 summary->set_out(0, Location::RequiresFpuRegister()); 3606 summary->set_out(0, Location::RequiresFpuRegister());
3607 return summary; 3607 return summary;
3608 } 3608 }
3609 3609
3610 3610
3611 void BinaryDoubleOpInstr::EmitNativeCode(FlowGraphCompiler* compiler) { 3611 void BinaryDoubleOpInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
3612 DRegister left = EvenDRegisterOf(locs()->in(0).fpu_reg()); 3612 const DRegister left = EvenDRegisterOf(locs()->in(0).fpu_reg());
3613 DRegister right = EvenDRegisterOf(locs()->in(1).fpu_reg()); 3613 const DRegister right = EvenDRegisterOf(locs()->in(1).fpu_reg());
3614 DRegister result = EvenDRegisterOf(locs()->out(0).fpu_reg()); 3614 const DRegister result = EvenDRegisterOf(locs()->out(0).fpu_reg());
3615 switch (op_kind()) { 3615 switch (op_kind()) {
3616 case Token::kADD: __ vaddd(result, left, right); break; 3616 case Token::kADD: __ vaddd(result, left, right); break;
3617 case Token::kSUB: __ vsubd(result, left, right); break; 3617 case Token::kSUB: __ vsubd(result, left, right); break;
3618 case Token::kMUL: __ vmuld(result, left, right); break; 3618 case Token::kMUL: __ vmuld(result, left, right); break;
3619 case Token::kDIV: __ vdivd(result, left, right); break; 3619 case Token::kDIV: __ vdivd(result, left, right); break;
3620 default: UNREACHABLE(); 3620 default: UNREACHABLE();
3621 } 3621 }
3622 } 3622 }
3623 3623
3624 3624
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6081 compiler->GenerateCall(token_pos(), 6081 compiler->GenerateCall(token_pos(),
6082 &label, 6082 &label,
6083 PcDescriptors::kOther, 6083 PcDescriptors::kOther,
6084 locs()); 6084 locs());
6085 __ Drop(ArgumentCount()); // Discard arguments. 6085 __ Drop(ArgumentCount()); // Discard arguments.
6086 } 6086 }
6087 6087
6088 } // namespace dart 6088 } // namespace dart
6089 6089
6090 #endif // defined TARGET_ARCH_ARM 6090 #endif // defined TARGET_ARCH_ARM
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