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Side by Side Diff: runtime/vm/disassembler_arm64.cc

Issue 262333007: Adds arm64 double arithmetic instructions. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 6 years, 7 months ago
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1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/disassembler.h" 5 #include "vm/disassembler.h"
6 6
7 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM64. 7 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM64.
8 #if defined(TARGET_ARCH_ARM64) 8 #if defined(TARGET_ARCH_ARM64)
9 #include "platform/assert.h" 9 #include "platform/assert.h"
10 10
(...skipping 294 matching lines...) Expand 10 before | Expand all | Expand 10 after
305 int ARM64Decoder::FormatVRegister(Instr* instr, const char* format) { 305 int ARM64Decoder::FormatVRegister(Instr* instr, const char* format) {
306 ASSERT(format[0] == 'v'); 306 ASSERT(format[0] == 'v');
307 if (format[1] == 'd') { 307 if (format[1] == 'd') {
308 int reg = instr->VdField(); 308 int reg = instr->VdField();
309 PrintVRegister(reg); 309 PrintVRegister(reg);
310 return 2; 310 return 2;
311 } else if (format[1] == 'n') { 311 } else if (format[1] == 'n') {
312 int reg = instr->VnField(); 312 int reg = instr->VnField();
313 PrintVRegister(reg); 313 PrintVRegister(reg);
314 return 2; 314 return 2;
315 } else if (format[1] == 'm') {
316 int reg = instr->VmField();
317 PrintVRegister(reg);
318 return 2;
315 } else if (format[1] == 't') { 319 } else if (format[1] == 't') {
316 int reg = instr->VtField(); 320 int reg = instr->VtField();
317 PrintVRegister(reg); 321 PrintVRegister(reg);
318 return 2; 322 return 2;
319 } 323 }
320 UNREACHABLE(); 324 UNREACHABLE();
321 return -1; 325 return -1;
322 } 326 }
323 327
324 328
(...skipping 584 matching lines...) Expand 10 before | Expand all | Expand 10 after
909 Format(instr, "smulh 'rd, 'rn, 'rm"); 913 Format(instr, "smulh 'rd, 'rn, 'rm");
910 } else { 914 } else {
911 Unknown(instr); 915 Unknown(instr);
912 } 916 }
913 } 917 }
914 918
915 919
916 void ARM64Decoder::DecodeConditionalSelect(Instr* instr) { 920 void ARM64Decoder::DecodeConditionalSelect(Instr* instr) {
917 if ((instr->Bits(29, 2) == 0) && (instr->Bits(10, 2) == 0)) { 921 if ((instr->Bits(29, 2) == 0) && (instr->Bits(10, 2) == 0)) {
918 Format(instr, "mov'sf'cond 'rd, 'rn, 'rm"); 922 Format(instr, "mov'sf'cond 'rd, 'rn, 'rm");
923 } else if ((instr->Bits(29, 2) == 0) && (instr->Bits(10, 2) == 1)) {
924 Format(instr, "inc'sf'cond 'rd, 'rn, 'rm");
919 } else { 925 } else {
920 Unknown(instr); 926 Unknown(instr);
921 } 927 }
922 } 928 }
923 929
924 930
925 void ARM64Decoder::DecodeDPRegister(Instr* instr) { 931 void ARM64Decoder::DecodeDPRegister(Instr* instr) {
926 if (instr->IsAddSubShiftExtOp()) { 932 if (instr->IsAddSubShiftExtOp()) {
927 DecodeAddSubShiftExt(instr); 933 DecodeAddSubShiftExt(instr);
928 } else if (instr->IsLogicalShiftOp()) { 934 } else if (instr->IsLogicalShiftOp()) {
(...skipping 30 matching lines...) Expand all
959 } 965 }
960 } 966 }
961 967
962 968
963 void ARM64Decoder::DecodeFPIntCvt(Instr* instr) { 969 void ARM64Decoder::DecodeFPIntCvt(Instr* instr) {
964 if ((instr->SFField() != 1) || (instr->Bit(29) != 0) || 970 if ((instr->SFField() != 1) || (instr->Bit(29) != 0) ||
965 (instr->Bits(22, 2) != 1)) { 971 (instr->Bits(22, 2) != 1)) {
966 Unknown(instr); 972 Unknown(instr);
967 return; 973 return;
968 } 974 }
969 if (instr->Bits(16, 3) == 6) { 975 if (instr->Bits(16, 5) == 2) {
976 Format(instr, "scvtfd 'vd, 'vn");
977 } else if (instr->Bits(16, 5) == 6) {
970 Format(instr, "fmovrd 'rd, 'vn"); 978 Format(instr, "fmovrd 'rd, 'vn");
971 } else if (instr->Bits(16, 3) == 7) { 979 } else if (instr->Bits(16, 5) == 7) {
972 Format(instr, "fmovdr 'vd, 'rn"); 980 Format(instr, "fmovdr 'vd, 'rn");
981 } else if (instr->Bits(16, 5) == 24) {
982 Format(instr, "fcvtzds 'rd, 'vn");
973 } else { 983 } else {
974 Unknown(instr); 984 Unknown(instr);
975 } 985 }
976 } 986 }
977 987
978 988
979 void ARM64Decoder::DecodeFPOneSource(Instr* instr) { 989 void ARM64Decoder::DecodeFPOneSource(Instr* instr) {
980 const int opc = instr->Bits(15, 2); 990 const int opc = instr->Bits(15, 2);
981 991
982 switch (opc) { 992 switch (opc) {
983 case 0: 993 case 0:
984 Format(instr, "fmovdd 'vd, 'vn"); 994 Format(instr, "fmovdd 'vd, 'vn");
985 break; 995 break;
986 default: 996 default:
987 Unknown(instr); 997 Unknown(instr);
988 break; 998 break;
989 } 999 }
990 } 1000 }
991 1001
992 1002
1003 void ARM64Decoder::DecodeFPTwoSource(Instr* instr) {
1004 if (instr->Bits(22, 2) != 1) {
1005 Unknown(instr);
1006 return;
1007 }
1008 const int opc = instr->Bits(12, 4);
1009
1010 switch (opc) {
1011 case 0:
1012 Format(instr, "fmuld 'vd, 'vn, 'vm");
1013 break;
1014 case 1:
1015 Format(instr, "fdivd 'vd, 'vn, 'vm");
1016 break;
1017 case 2:
1018 Format(instr, "faddd 'vd, 'vn, 'vm");
1019 break;
1020 case 3:
1021 Format(instr, "fsubd 'vd, 'vn, 'vm");
1022 break;
1023 default:
1024 Unknown(instr);
1025 break;
1026 }
1027 }
1028
1029
1030 void ARM64Decoder::DecodeFPCompare(Instr* instr) {
1031 if ((instr->Bit(22) == 1) && (instr->Bits(3, 2) == 0)) {
1032 Format(instr, "fcmpd 'vn, 'vm");
1033 } else if ((instr->Bit(22) == 1) && (instr->Bits(3, 2) == 1)) {
1034 if (instr->VmField() == V0) {
1035 Format(instr, "fcmpd 'vn, #0.0");
1036 } else {
1037 Unknown(instr);
1038 }
1039 } else {
1040 Unknown(instr);
1041 }
1042 }
1043
1044
993 void ARM64Decoder::DecodeFP(Instr* instr) { 1045 void ARM64Decoder::DecodeFP(Instr* instr) {
994 if (instr->IsFPImmOp()) { 1046 if (instr->IsFPImmOp()) {
995 DecodeFPImm(instr); 1047 DecodeFPImm(instr);
996 } else if (instr->IsFPIntCvtOp()) { 1048 } else if (instr->IsFPIntCvtOp()) {
997 DecodeFPIntCvt(instr); 1049 DecodeFPIntCvt(instr);
998 } else if (instr->IsFPOneSourceOp()) { 1050 } else if (instr->IsFPOneSourceOp()) {
999 DecodeFPOneSource(instr); 1051 DecodeFPOneSource(instr);
1052 } else if (instr->IsFPTwoSourceOp()) {
1053 DecodeFPTwoSource(instr);
1054 } else if (instr->IsFPCompareOp()) {
1055 DecodeFPCompare(instr);
1000 } else { 1056 } else {
1001 Unknown(instr); 1057 Unknown(instr);
1002 } 1058 }
1003 } 1059 }
1004 1060
1005 1061
1006 void ARM64Decoder::DecodeDPSimd2(Instr* instr) { 1062 void ARM64Decoder::DecodeDPSimd2(Instr* instr) {
1007 if (instr->IsFPOp()) { 1063 if (instr->IsFPOp()) {
1008 DecodeFP(instr); 1064 DecodeFP(instr);
1009 } else { 1065 } else {
(...skipping 64 matching lines...) Expand 10 before | Expand all | Expand 10 after
1074 human_buffer, 1130 human_buffer,
1075 sizeof(human_buffer), 1131 sizeof(human_buffer),
1076 pc); 1132 pc);
1077 pc += instruction_length; 1133 pc += instruction_length;
1078 } 1134 }
1079 } 1135 }
1080 1136
1081 } // namespace dart 1137 } // namespace dart
1082 1138
1083 #endif // defined TARGET_ARCH_ARM 1139 #endif // defined TARGET_ARCH_ARM
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