Adds arm64 double arithmetic instructions.

runtime/vm/assembler_arm64_test.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM64)
 
 #include "vm/assembler.h"
 #include "vm/cpu.h"
 #include "vm/os.h"
@@ skipping 698 matching lines @@
   __ ret();
 }
 
 
 ASSEMBLER_TEST_RUN(CmpLtBranchNotTaken, test) {
   typedef int (*SimpleCode)();
   EXPECT_EQ(42, EXECUTE_TEST_CODE_INT64(SimpleCode, test->entry()));
 }
 
 
+
+
+ASSEMBLER_TEST_GENERATE(FcmpEqBranch, assembler) {
+  Label l;
+
+  __ LoadDImmediate(V0, 42.0, kNoPP);
+  __ LoadDImmediate(V1, 234.0, kNoPP);
+  __ LoadDImmediate(V2, 234.0, kNoPP);
+
+  __ fcmpd(V1, V2);
+  __ b(&l, EQ);
+  __ LoadDImmediate(V0, 0.0, kNoPP);
+  __ Bind(&l);
+  __ ret();
+}
+
+
+ASSEMBLER_TEST_RUN(FcmpEqBranch, test) {
+  typedef int (*SimpleCode)();
+  EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(SimpleCode, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(FcmpEqBranchNotTaken, assembler) {
+  Label l;
+
+  __ LoadDImmediate(V0, 0.0, kNoPP);
+  __ LoadDImmediate(V1, 233.0, kNoPP);
+  __ LoadDImmediate(V2, 234.0, kNoPP);
+
+  __ fcmpd(V1, V2);
+  __ b(&l, EQ);
+  __ LoadDImmediate(V0, 42.0, kNoPP);
+  __ Bind(&l);
+  __ ret();
+}
+
+
+ASSEMBLER_TEST_RUN(FcmpEqBranchNotTaken, test) {
+  typedef int (*SimpleCode)();
+  EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(SimpleCode, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(FcmpLtBranch, assembler) {
+  Label l;
+
+  __ LoadDImmediate(V0, 42.0, kNoPP);
+  __ LoadDImmediate(V1, 233.0, kNoPP);
+  __ LoadDImmediate(V2, 234.0, kNoPP);
+
+  __ fcmpd(V1, V2);
+  __ b(&l, LT);
+  __ LoadDImmediate(V0, 0.0, kNoPP);
+  __ Bind(&l);
+  __ ret();
+}
+
+
+ASSEMBLER_TEST_RUN(FcmpLtBranch, test) {
+  typedef int (*SimpleCode)();
+  EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(SimpleCode, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(FcmpLtBranchNotTaken, assembler) {
+  Label l;
+
+  __ LoadDImmediate(V0, 0.0, kNoPP);
+  __ LoadDImmediate(V1, 235.0, kNoPP);
+  __ LoadDImmediate(V2, 234.0, kNoPP);
+
+  __ fcmpd(V1, V2);
+  __ b(&l, LT);
+  __ LoadDImmediate(V0, 42.0, kNoPP);
+  __ Bind(&l);
+  __ ret();
+}
+
+
+ASSEMBLER_TEST_RUN(FcmpLtBranchNotTaken, test) {
+  typedef int (*SimpleCode)();
+  EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(SimpleCode, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(FcmpzGtBranch, assembler) {
+  Label l;
+
+  __ LoadDImmediate(V0, 235.0, kNoPP);
+  __ LoadDImmediate(V1, 233.0, kNoPP);
+
+  __ fcmpzd(V1);
+  __ b(&l, GT);
+  __ LoadDImmediate(V0, 0.0, kNoPP);
+  __ ret();
+  __ Bind(&l);
+  __ LoadDImmediate(V0, 42.0, kNoPP);
+  __ ret();
+}
+
+
+ASSEMBLER_TEST_RUN(FcmpzGtBranch, test) {
+  typedef int (*SimpleCode)();
+  EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(SimpleCode, test->entry()));
+}
+
+
 ASSEMBLER_TEST_GENERATE(AndsBranch, assembler) {
   Label l;
 
   __ movz(R0, 42, 0);
   __ movz(R1, 2, 0);
   __ movz(R2, 1, 0);
 
   __ ands(R3, R1, Operand(R2));
   __ b(&l, EQ);
   __ movz(R0, 0, 0);
@@ skipping 609 matching lines @@
   __ ret();
 }
 
 
 ASSEMBLER_TEST_RUN(CSelFalse, test) {
   typedef int (*SimpleCode)();
   EXPECT_EQ(1234, EXECUTE_TEST_CODE_INT64(SimpleCode, test->entry()));
 }
 
 
+ASSEMBLER_TEST_GENERATE(CsincTrue, assembler) {
+  __ LoadImmediate(R1, 42, kNoRegister);
+  __ LoadImmediate(R2, 1234, kNoRegister);
+  __ CompareRegisters(R1, R2);
+  __ csinc(R0, R1, R2, LT);
+  __ ret();
+}
+
+
+ASSEMBLER_TEST_RUN(CsincTrue, test) {
+  typedef int (*SimpleCode)();
+  EXPECT_EQ(43, EXECUTE_TEST_CODE_INT64(SimpleCode, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(CsincFalse, assembler) {
+  __ LoadImmediate(R1, 42, kNoRegister);
+  __ LoadImmediate(R2, 1234, kNoRegister);
+  __ CompareRegisters(R1, R2);
+  __ csinc(R0, R1, R2, GE);
+  __ ret();
+}
+
+
+ASSEMBLER_TEST_RUN(CsincFalse, test) {
+  typedef int (*SimpleCode)();
+  EXPECT_EQ(1234, EXECUTE_TEST_CODE_INT64(SimpleCode, test->entry()));
+}
+
+
 // Floating point move immediate, to/from integer register.
 ASSEMBLER_TEST_GENERATE(Fmovdi, assembler) {
   __ LoadDImmediate(V0, 1.0, kNoPP);
   __ ret();
 }
 
 
 ASSEMBLER_TEST_RUN(Fmovdi, test) {
   typedef int (*SimpleCode)();
   EXPECT_EQ(1.0, EXECUTE_TEST_CODE_DOUBLE(SimpleCode, test->entry()));
@@ skipping 48 matching lines @@
   __ ret();
 }
 
 
 ASSEMBLER_TEST_RUN(FldrdFstrdPrePostIndex, test) {
   typedef int (*SimpleCode)();
   EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(SimpleCode, test->entry()));
 }
 
 
+ASSEMBLER_TEST_GENERATE(Fcvtzds, assembler) {
+  __ LoadDImmediate(V0, 42.0, kNoPP);
+  __ fcvtzds(R0, V0);
+  __ ret();
+}
+
+
+ASSEMBLER_TEST_RUN(Fcvtzds, test) {
+  typedef int (*SimpleCode)();
+  EXPECT_EQ(42, EXECUTE_TEST_CODE_INT64(SimpleCode, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(Scvtfd, assembler) {
+  __ LoadImmediate(R0, 42, kNoPP);
+  __ scvtfd(V0, R0);
+  __ ret();
+}
+
+
+ASSEMBLER_TEST_RUN(Scvtfd, test) {
+  typedef int (*SimpleCode)();
+  EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(SimpleCode, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(Fmuld, assembler) {
+  __ LoadDImmediate(V1, 84.0, kNoPP);
+  __ LoadDImmediate(V2, 0.5, kNoPP);
+  __ fmuld(V0, V1, V2);
+  __ ret();
+}
+
+
+ASSEMBLER_TEST_RUN(Fmuld, test) {
+  typedef int (*SimpleCode)();
+  EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(SimpleCode, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(Fdivd, assembler) {
+  __ LoadDImmediate(V1, 84.0, kNoPP);
+  __ LoadDImmediate(V2, 2.0, kNoPP);
+  __ fdivd(V0, V1, V2);
+  __ ret();
+}
+
+
+ASSEMBLER_TEST_RUN(Fdivd, test) {
+  typedef int (*SimpleCode)();
+  EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(SimpleCode, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(Faddd, assembler) {
+  __ LoadDImmediate(V1, 41.5, kNoPP);
+  __ LoadDImmediate(V2, 0.5, kNoPP);
+  __ faddd(V0, V1, V2);
+  __ ret();
+}
+
+
+ASSEMBLER_TEST_RUN(Faddd, test) {
+  typedef int (*SimpleCode)();
+  EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(SimpleCode, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(Fsubd, assembler) {
+  __ LoadDImmediate(V1, 42.5, kNoPP);
+  __ LoadDImmediate(V2, 0.5, kNoPP);
+  __ fsubd(V0, V1, V2);
+  __ ret();
+}
+
+
+ASSEMBLER_TEST_RUN(Fsubd, test) {
+  typedef int (*SimpleCode)();
+  EXPECT_EQ(42.0, EXECUTE_TEST_CODE_DOUBLE(SimpleCode, test->entry()));
+}
+
+
 ASSEMBLER_TEST_GENERATE(FldrdFstrdHeapTag, assembler) {
   __ LoadDImmediate(V0, 43.0, kNoPP);
   __ LoadDImmediate(V1, 42.0, kNoPP);
   __ AddImmediate(SP, SP, -1 * kWordSize, kNoPP);
   __ add(R2, SP, Operand(1));
   __ fstrd(V1, Address(R2, -1));
   __ fldrd(V0, Address(R2, -1));
   __ AddImmediate(SP, SP, 1 * kWordSize, kNoPP);
   __ ret();
 }
@@ skipping 97 matching lines @@
                      R1);
   __ Pop(LR);
   __ Pop(CTX);
   __ PopAndUntagPP();
   __ ret();
 }
 
 }  // namespace dart
 
 #endif  // defined(TARGET_ARCH_ARM64)