ARM64: Add NEON support

test/cctest/test-utils-arm64.cc

Index: test/cctest/test-utils-arm64.cc
diff --git a/test/cctest/test-utils-arm64.cc b/test/cctest/test-utils-arm64.cc
index c1732a2f83d14ad0044f23c74fa4ade657c75c4c..6c2229b1a71eb32cebca6eed11e96ff4752a0e7a 100644
--- a/test/cctest/test-utils-arm64.cc
+++ b/test/cctest/test-utils-arm64.cc
@@ -59,19 +59,30 @@ bool Equal64(uint64_t expected, const RegisterDump*, uint64_t result) {
   return expected == result;
 }
 
+bool Equal128(vec128_t expected, const RegisterDump*, vec128_t result) {
+  if ((result.h != expected.h) || (result.l != expected.l)) {
+    printf("Expected 0x%016" PRIx64 "%016" PRIx64
+           "\t "
+           "Found 0x%016" PRIx64 "%016" PRIx64 "\n",
+           expected.h, expected.l, result.h, result.l);
+  }
+
+  return ((expected.h == result.h) && (expected.l == result.l));
+}
 
 bool EqualFP32(float expected, const RegisterDump*, float result) {
-  if (float_to_rawbits(expected) == float_to_rawbits(result)) {
+  if (bit_cast<uint32_t>(expected) == bit_cast<uint32_t>(result)) {
     return true;
   } else {
     if (std::isnan(expected) || (expected == 0.0)) {
       printf("Expected 0x%08" PRIx32 "\t Found 0x%08" PRIx32 "\n",
-             float_to_rawbits(expected), float_to_rawbits(result));
+             bit_cast<uint32_t>(expected), bit_cast<uint32_t>(result));
     } else {
-      printf("Expected %.9f (0x%08" PRIx32 ")\t "
+      printf("Expected %.9f (0x%08" PRIx32
+             ")\t "
              "Found %.9f (0x%08" PRIx32 ")\n",
-             expected, float_to_rawbits(expected),
-             result, float_to_rawbits(result));
+             expected, bit_cast<uint32_t>(expected), result,
+             bit_cast<uint32_t>(result));
     }
     return false;
   }
@@ -79,18 +90,19 @@ bool EqualFP32(float expected, const RegisterDump*, float result) {
 
 
 bool EqualFP64(double expected, const RegisterDump*, double result) {
-  if (double_to_rawbits(expected) == double_to_rawbits(result)) {
+  if (bit_cast<uint64_t>(expected) == bit_cast<uint64_t>(result)) {
     return true;
   }
 
   if (std::isnan(expected) || (expected == 0.0)) {
     printf("Expected 0x%016" PRIx64 "\t Found 0x%016" PRIx64 "\n",
-           double_to_rawbits(expected), double_to_rawbits(result));
+           bit_cast<uint64_t>(expected), bit_cast<uint64_t>(result));
   } else {
-    printf("Expected %.17f (0x%016" PRIx64 ")\t "
+    printf("Expected %.17f (0x%016" PRIx64
+           ")\t "
            "Found %.17f (0x%016" PRIx64 ")\n",
-           expected, double_to_rawbits(expected),
-           result, double_to_rawbits(result));
+           expected, bit_cast<uint64_t>(expected), result,
+           bit_cast<uint64_t>(result));
   }
   return false;
 }
@@ -119,27 +131,31 @@ bool Equal64(uint64_t expected,
   return Equal64(expected, core, result);
 }
 
+bool Equal128(uint64_t expected_h, uint64_t expected_l,
+              const RegisterDump* core, const VRegister& vreg) {
+  CHECK(vreg.Is128Bits());
+  vec128_t expected = {expected_l, expected_h};
+  vec128_t result = core->qreg(vreg.code());
+  return Equal128(expected, core, result);
+}
 
-bool EqualFP32(float expected,
-               const RegisterDump* core,
-               const FPRegister& fpreg) {
+bool EqualFP32(float expected, const RegisterDump* core,
+               const VRegister& fpreg) {
   CHECK(fpreg.Is32Bits());
   // Retrieve the corresponding D register so we can check that the upper part
   // was properly cleared.
   uint64_t result_64 = core->dreg_bits(fpreg.code());
   if ((result_64 & 0xffffffff00000000L) != 0) {
     printf("Expected 0x%08" PRIx32 " (%f)\t Found 0x%016" PRIx64 "\n",
-           float_to_rawbits(expected), expected, result_64);
+           bit_cast<uint32_t>(expected), expected, result_64);
     return false;
   }
 
   return EqualFP32(expected, core, core->sreg(fpreg.code()));
 }
 
-
-bool EqualFP64(double expected,
-               const RegisterDump* core,
-               const FPRegister& fpreg) {
+bool EqualFP64(double expected, const RegisterDump* core,
+               const VRegister& fpreg) {
   CHECK(fpreg.Is64Bits());
   return EqualFP64(expected, core, core->dreg(fpreg.code()));
 }
@@ -198,7 +214,7 @@ bool EqualRegisters(const RegisterDump* a, const RegisterDump* b) {
     }
   }
 
-  for (unsigned i = 0; i < kNumberOfFPRegisters; i++) {
+  for (unsigned i = 0; i < kNumberOfVRegisters; i++) {
     uint64_t a_bits = a->dreg_bits(i);
     uint64_t b_bits = b->dreg_bits(i);
     if (a_bits != b_bits) {
@@ -238,29 +254,28 @@ RegList PopulateRegisterArray(Register* w, Register* x, Register* r,
   return list;
 }
 
-
-RegList PopulateFPRegisterArray(FPRegister* s, FPRegister* d, FPRegister* v,
-                                int reg_size, int reg_count, RegList allowed) {
+RegList PopulateVRegisterArray(VRegister* s, VRegister* d, VRegister* v,
+                               int reg_size, int reg_count, RegList allowed) {
   RegList list = 0;
   int i = 0;
-  for (unsigned n = 0; (n < kNumberOfFPRegisters) && (i < reg_count); n++) {
+  for (unsigned n = 0; (n < kNumberOfVRegisters) && (i < reg_count); n++) {
     if (((1UL << n) & allowed) != 0) {
       // Only assigned allowed registers.
       if (v) {
-        v[i] = FPRegister::Create(n, reg_size);
+        v[i] = VRegister::Create(n, reg_size);
       }
       if (d) {
-        d[i] = FPRegister::Create(n, kDRegSizeInBits);
+        d[i] = VRegister::Create(n, kDRegSizeInBits);
       }
       if (s) {
-        s[i] = FPRegister::Create(n, kSRegSizeInBits);
+        s[i] = VRegister::Create(n, kSRegSizeInBits);
       }
       list |= (1UL << n);
       i++;
     }
   }
   // Check that we got enough registers.
-  CHECK(CountSetBits(list, kNumberOfFPRegisters) == reg_count);
+  CHECK(CountSetBits(list, kNumberOfVRegisters) == reg_count);
 
   return list;
 }
@@ -290,10 +305,10 @@ void Clobber(MacroAssembler* masm, RegList reg_list, uint64_t const value) {
 
 
 void ClobberFP(MacroAssembler* masm, RegList reg_list, double const value) {
-  FPRegister first = NoFPReg;
-  for (unsigned i = 0; i < kNumberOfFPRegisters; i++) {
+  VRegister first = NoVReg;
+  for (unsigned i = 0; i < kNumberOfVRegisters; i++) {
     if (reg_list & (1UL << i)) {
-      FPRegister dn = FPRegister::Create(i, kDRegSizeInBits);
+      VRegister dn = VRegister::Create(i, kDRegSizeInBits);
       if (!first.IsValid()) {
         // This is the first register we've hit, so construct the literal.
         __ Fmov(dn, value);
@@ -312,7 +327,7 @@ void Clobber(MacroAssembler* masm, CPURegList reg_list) {
   if (reg_list.type() == CPURegister::kRegister) {
     // This will always clobber X registers.
     Clobber(masm, reg_list.list());
-  } else if (reg_list.type() == CPURegister::kFPRegister) {
+  } else if (reg_list.type() == CPURegister::kVRegister) {
     // This will always clobber D registers.
     ClobberFP(masm, reg_list.list());
   } else {
@@ -343,6 +358,7 @@ void RegisterDump::Dump(MacroAssembler* masm) {
   const int w_offset = offsetof(dump_t, w_);
   const int d_offset = offsetof(dump_t, d_);
   const int s_offset = offsetof(dump_t, s_);
+  const int q_offset = offsetof(dump_t, q_);
   const int sp_offset = offsetof(dump_t, sp_);
   const int wsp_offset = offsetof(dump_t, wsp_);
   const int flags_offset = offsetof(dump_t, flags_);
@@ -377,18 +393,25 @@ void RegisterDump::Dump(MacroAssembler* masm) {
 
   // Dump D registers.
   __ Add(dump, dump_base, d_offset);
-  for (unsigned i = 0; i < kNumberOfFPRegisters; i += 2) {
-    __ Stp(FPRegister::DRegFromCode(i), FPRegister::DRegFromCode(i + 1),
+  for (unsigned i = 0; i < kNumberOfVRegisters; i += 2) {
+    __ Stp(VRegister::DRegFromCode(i), VRegister::DRegFromCode(i + 1),
            MemOperand(dump, i * kDRegSize));
   }
 
   // Dump S registers.
   __ Add(dump, dump_base, s_offset);
-  for (unsigned i = 0; i < kNumberOfFPRegisters; i += 2) {
-    __ Stp(FPRegister::SRegFromCode(i), FPRegister::SRegFromCode(i + 1),
+  for (unsigned i = 0; i < kNumberOfVRegisters; i += 2) {
+    __ Stp(VRegister::SRegFromCode(i), VRegister::SRegFromCode(i + 1),
            MemOperand(dump, i * kSRegSize));
   }
 
+  // Dump Q registers.
+  __ Add(dump, dump_base, q_offset);
+  for (unsigned i = 0; i < kNumberOfVRegisters; i += 2) {
+    __ Stp(VRegister::QRegFromCode(i), VRegister::QRegFromCode(i + 1),
+           MemOperand(dump, i * kQRegSize));
+  }
+
   // Dump the flags.
   __ Mrs(tmp, NZCV);
   __ Str(tmp, MemOperand(dump_base, flags_offset));