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Side by Side Diff: src/arm64/constants-arm64.h

Issue 2622643005: ARM64: Add NEON support (Closed)
Patch Set: Created 3 years, 11 months ago
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1 // Copyright 2013 the V8 project authors. All rights reserved. 1 // Copyright 2013 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_ARM64_CONSTANTS_ARM64_H_ 5 #ifndef V8_ARM64_CONSTANTS_ARM64_H_
6 #define V8_ARM64_CONSTANTS_ARM64_H_ 6 #define V8_ARM64_CONSTANTS_ARM64_H_
7 7
8 #include "src/base/macros.h" 8 #include "src/base/macros.h"
9 #include "src/globals.h" 9 #include "src/globals.h"
10 10
(...skipping 15 matching lines...) Expand all
26 namespace v8 { 26 namespace v8 {
27 namespace internal { 27 namespace internal {
28 28
29 29
30 const unsigned kInstructionSize = 4; 30 const unsigned kInstructionSize = 4;
31 const unsigned kInstructionSizeLog2 = 2; 31 const unsigned kInstructionSizeLog2 = 2;
32 const unsigned kLoadLiteralScaleLog2 = 2; 32 const unsigned kLoadLiteralScaleLog2 = 2;
33 const unsigned kMaxLoadLiteralRange = 1 * MB; 33 const unsigned kMaxLoadLiteralRange = 1 * MB;
34 34
35 const int kNumberOfRegisters = 32; 35 const int kNumberOfRegisters = 32;
36 const int kNumberOfFPRegisters = 32; 36 const int kNumberOfVRegisters = 32;
37 // Callee saved registers are x19-x30(lr). 37 // Callee saved registers are x19-x30(lr).
38 const int kNumberOfCalleeSavedRegisters = 11; 38 const int kNumberOfCalleeSavedRegisters = 11;
39 const int kFirstCalleeSavedRegisterIndex = 19; 39 const int kFirstCalleeSavedRegisterIndex = 19;
40 // Callee saved FP registers are d8-d15. 40 // Callee saved FP registers are d8-d15.
41 const int kNumberOfCalleeSavedFPRegisters = 8; 41 const int kNumberOfCalleeSavedVRegisters = 8;
42 const int kFirstCalleeSavedFPRegisterIndex = 8; 42 const int kFirstCalleeSavedVRegisterIndex = 8;
43 // Callee saved registers with no specific purpose in JS are x19-x25. 43 // Callee saved registers with no specific purpose in JS are x19-x25.
44 const unsigned kJSCalleeSavedRegList = 0x03f80000; 44 const unsigned kJSCalleeSavedRegList = 0x03f80000;
45 const int kWRegSizeInBits = 32; 45 const int kWRegSizeInBits = 32;
46 const int kWRegSizeInBitsLog2 = 5; 46 const int kWRegSizeInBitsLog2 = 5;
47 const int kWRegSize = kWRegSizeInBits >> 3; 47 const int kWRegSize = kWRegSizeInBits >> 3;
48 const int kWRegSizeLog2 = kWRegSizeInBitsLog2 - 3; 48 const int kWRegSizeLog2 = kWRegSizeInBitsLog2 - 3;
49 const int kXRegSizeInBits = 64; 49 const int kXRegSizeInBits = 64;
50 const int kXRegSizeInBitsLog2 = 6; 50 const int kXRegSizeInBitsLog2 = 6;
51 const int kXRegSize = kXRegSizeInBits >> 3; 51 const int kXRegSize = kXRegSizeInBits >> 3;
52 const int kXRegSizeLog2 = kXRegSizeInBitsLog2 - 3; 52 const int kXRegSizeLog2 = kXRegSizeInBitsLog2 - 3;
53 const int kSRegSizeInBits = 32; 53 const int kSRegSizeInBits = 32;
54 const int kSRegSizeInBitsLog2 = 5; 54 const int kSRegSizeInBitsLog2 = 5;
55 const int kSRegSize = kSRegSizeInBits >> 3; 55 const int kSRegSize = kSRegSizeInBits >> 3;
56 const int kSRegSizeLog2 = kSRegSizeInBitsLog2 - 3; 56 const int kSRegSizeLog2 = kSRegSizeInBitsLog2 - 3;
57 const int kDRegSizeInBits = 64; 57 const int kDRegSizeInBits = 64;
58 const int kDRegSizeInBitsLog2 = 6; 58 const int kDRegSizeInBitsLog2 = 6;
59 const int kDRegSize = kDRegSizeInBits >> 3; 59 const int kDRegSize = kDRegSizeInBits >> 3;
60 const int kDRegSizeLog2 = kDRegSizeInBitsLog2 - 3; 60 const int kDRegSizeLog2 = kDRegSizeInBitsLog2 - 3;
61 const int kDRegSizeInBytesLog2 = kDRegSizeInBitsLog2 - 3;
62 const int kBRegSizeInBits = 8;
63 const int kBRegSize = kBRegSizeInBits >> 3;
64 const int kHRegSizeInBits = 16;
65 const int kHRegSize = kHRegSizeInBits >> 3;
66 const int kQRegSizeInBits = 128;
67 const int kQRegSizeInBitsLog2 = 7;
68 const int kQRegSize = kQRegSizeInBits >> 3;
69 const int kQRegSizeLog2 = kQRegSizeInBitsLog2 - 3;
70 const int kVRegSizeInBits = kQRegSizeInBits;
71 const int kVRegSize = kVRegSizeInBits >> 3;
61 const int64_t kWRegMask = 0x00000000ffffffffL; 72 const int64_t kWRegMask = 0x00000000ffffffffL;
62 const int64_t kXRegMask = 0xffffffffffffffffL; 73 const int64_t kXRegMask = 0xffffffffffffffffL;
63 const int64_t kSRegMask = 0x00000000ffffffffL; 74 const int64_t kSRegMask = 0x00000000ffffffffL;
64 const int64_t kDRegMask = 0xffffffffffffffffL; 75 const int64_t kDRegMask = 0xffffffffffffffffL;
65 // TODO(all) check if the expression below works on all compilers or if it 76 // TODO(all) check if the expression below works on all compilers or if it
66 // triggers an overflow error. 77 // triggers an overflow error.
67 const int64_t kDSignBit = 63; 78 const int64_t kDSignBit = 63;
68 const int64_t kDSignMask = 0x1L << kDSignBit; 79 const int64_t kDSignMask = 0x1L << kDSignBit;
69 const int64_t kSSignBit = 31; 80 const int64_t kSSignBit = 31;
70 const int64_t kSSignMask = 0x1L << kSSignBit; 81 const int64_t kSSignMask = 0x1L << kSSignBit;
(...skipping 32 matching lines...) Expand 10 before | Expand all | Expand 10 after
103 const unsigned kHalfWordSizeInBytes = kHalfWordSize >> 3; 114 const unsigned kHalfWordSizeInBytes = kHalfWordSize >> 3;
104 const unsigned kHalfWordSizeInBytesLog2 = kHalfWordSizeLog2 - 3; 115 const unsigned kHalfWordSizeInBytesLog2 = kHalfWordSizeLog2 - 3;
105 const unsigned kWordSize = 32; 116 const unsigned kWordSize = 32;
106 const unsigned kWordSizeLog2 = 5; 117 const unsigned kWordSizeLog2 = 5;
107 const unsigned kWordSizeInBytes = kWordSize >> 3; 118 const unsigned kWordSizeInBytes = kWordSize >> 3;
108 const unsigned kWordSizeInBytesLog2 = kWordSizeLog2 - 3; 119 const unsigned kWordSizeInBytesLog2 = kWordSizeLog2 - 3;
109 const unsigned kDoubleWordSize = 64; 120 const unsigned kDoubleWordSize = 64;
110 const unsigned kDoubleWordSizeInBytes = kDoubleWordSize >> 3; 121 const unsigned kDoubleWordSizeInBytes = kDoubleWordSize >> 3;
111 const unsigned kQuadWordSize = 128; 122 const unsigned kQuadWordSize = 128;
112 const unsigned kQuadWordSizeInBytes = kQuadWordSize >> 3; 123 const unsigned kQuadWordSizeInBytes = kQuadWordSize >> 3;
124
125 const unsigned kAddressTagOffset = 56;
126 const unsigned kAddressTagWidth = 8;
127 const uint64_t kAddressTagMask = ((UINT64_C(1) << kAddressTagWidth) - 1)
128 << kAddressTagOffset;
129 static_assert(kAddressTagMask == UINT64_C(0xff00000000000000),
130 "AddressTagMask must represent most-significant eight bits.");
131
113 // AArch64 floating-point specifics. These match IEEE-754. 132 // AArch64 floating-point specifics. These match IEEE-754.
114 const unsigned kDoubleMantissaBits = 52; 133 const unsigned kDoubleMantissaBits = 52;
115 const unsigned kDoubleExponentBits = 11; 134 const unsigned kDoubleExponentBits = 11;
116 const unsigned kDoubleExponentBias = 1023; 135 const unsigned kDoubleExponentBias = 1023;
117 const unsigned kFloatMantissaBits = 23; 136 const unsigned kFloatMantissaBits = 23;
118 const unsigned kFloatExponentBits = 8; 137 const unsigned kFloatExponentBits = 8;
138 const unsigned kFloatExponentBias = 127;
139 const unsigned kFloat16MantissaBits = 10;
140 const unsigned kFloat16ExponentBits = 5;
141 const unsigned kFloat16ExponentBias = 15;
142
143 typedef uint16_t float16;
119 144
120 #define INSTRUCTION_FIELDS_LIST(V_) \ 145 #define INSTRUCTION_FIELDS_LIST(V_) \
121 /* Register fields */ \ 146 /* Register fields */ \
122 V_(Rd, 4, 0, Bits) /* Destination register. */ \ 147 V_(Rd, 4, 0, Bits) /* Destination register. */ \
123 V_(Rn, 9, 5, Bits) /* First source register. */ \ 148 V_(Rn, 9, 5, Bits) /* First source register. */ \
124 V_(Rm, 20, 16, Bits) /* Second source register. */ \ 149 V_(Rm, 20, 16, Bits) /* Second source register. */ \
125 V_(Ra, 14, 10, Bits) /* Third source register. */ \ 150 V_(Ra, 14, 10, Bits) /* Third source register. */ \
126 V_(Rt, 4, 0, Bits) /* Load dest / store source. */ \ 151 V_(Rt, 4, 0, Bits) /* Load dest / store source. */ \
127 V_(Rt2, 14, 10, Bits) /* Load second dest / */ \ 152 V_(Rt2, 14, 10, Bits) /* Load second dest / */ \
128 /* store second source. */ \ 153 /* store second source. */ \
129 V_(Rs, 20, 16, Bits) /* Store-exclusive status */ \ 154 V_(Rs, 20, 16, Bits) /* Store-exclusive status */ \
130 V_(PrefetchMode, 4, 0, Bits) \ 155 V_(PrefetchMode, 4, 0, Bits) \
131 \ 156 \
132 /* Common bits */ \ 157 /* Common bits */ \
133 V_(SixtyFourBits, 31, 31, Bits) \ 158 V_(SixtyFourBits, 31, 31, Bits) \
134 V_(FlagsUpdate, 29, 29, Bits) \ 159 V_(FlagsUpdate, 29, 29, Bits) \
135 \ 160 \
136 /* PC relative addressing */ \ 161 /* PC relative addressing */ \
137 V_(ImmPCRelHi, 23, 5, SignedBits) \ 162 V_(ImmPCRelHi, 23, 5, SignedBits) \
138 V_(ImmPCRelLo, 30, 29, Bits) \ 163 V_(ImmPCRelLo, 30, 29, Bits) \
139 \ 164 \
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174 \ 199 \
175 /* Floating point */ \ 200 /* Floating point */ \
176 V_(FPType, 23, 22, Bits) \ 201 V_(FPType, 23, 22, Bits) \
177 V_(ImmFP, 20, 13, Bits) \ 202 V_(ImmFP, 20, 13, Bits) \
178 V_(FPScale, 15, 10, Bits) \ 203 V_(FPScale, 15, 10, Bits) \
179 \ 204 \
180 /* Load Store */ \ 205 /* Load Store */ \
181 V_(ImmLS, 20, 12, SignedBits) \ 206 V_(ImmLS, 20, 12, SignedBits) \
182 V_(ImmLSUnsigned, 21, 10, Bits) \ 207 V_(ImmLSUnsigned, 21, 10, Bits) \
183 V_(ImmLSPair, 21, 15, SignedBits) \ 208 V_(ImmLSPair, 21, 15, SignedBits) \
184 V_(SizeLS, 31, 30, Bits) \
185 V_(ImmShiftLS, 12, 12, Bits) \ 209 V_(ImmShiftLS, 12, 12, Bits) \
210 V_(LSOpc, 23, 22, Bits) \
211 V_(LSVector, 26, 26, Bits) \
212 V_(LSSize, 31, 30, Bits) \
213 \
214 /* NEON generic fields */ \
215 V_(NEONQ, 30, 30, Bits) \
216 V_(NEONSize, 23, 22, Bits) \
217 V_(NEONLSSize, 11, 10, Bits) \
218 V_(NEONS, 12, 12, Bits) \
219 V_(NEONL, 21, 21, Bits) \
220 V_(NEONM, 20, 20, Bits) \
221 V_(NEONH, 11, 11, Bits) \
222 V_(ImmNEONExt, 14, 11, Bits) \
223 V_(ImmNEON5, 20, 16, Bits) \
224 V_(ImmNEON4, 14, 11, Bits) \
186 \ 225 \
187 /* Other immediates */ \ 226 /* Other immediates */ \
188 V_(ImmUncondBranch, 25, 0, SignedBits) \ 227 V_(ImmUncondBranch, 25, 0, SignedBits) \
189 V_(ImmCmpBranch, 23, 5, SignedBits) \ 228 V_(ImmCmpBranch, 23, 5, SignedBits) \
190 V_(ImmLLiteral, 23, 5, SignedBits) \ 229 V_(ImmLLiteral, 23, 5, SignedBits) \
191 V_(ImmException, 20, 5, Bits) \ 230 V_(ImmException, 20, 5, Bits) \
192 V_(ImmHint, 11, 5, Bits) \ 231 V_(ImmHint, 11, 5, Bits) \
193 V_(ImmBarrierDomain, 11, 10, Bits) \ 232 V_(ImmBarrierDomain, 11, 10, Bits) \
194 V_(ImmBarrierType, 9, 8, Bits) \ 233 V_(ImmBarrierType, 9, 8, Bits) \
195 \ 234 \
196 /* System (MRS, MSR) */ \ 235 /* System (MRS, MSR) */ \
197 V_(ImmSystemRegister, 19, 5, Bits) \ 236 V_(ImmSystemRegister, 19, 5, Bits) \
198 V_(SysO0, 19, 19, Bits) \ 237 V_(SysO0, 19, 19, Bits) \
199 V_(SysOp1, 18, 16, Bits) \ 238 V_(SysOp1, 18, 16, Bits) \
200 V_(SysOp2, 7, 5, Bits) \ 239 V_(SysOp2, 7, 5, Bits) \
201 V_(CRn, 15, 12, Bits) \ 240 V_(CRn, 15, 12, Bits) \
202 V_(CRm, 11, 8, Bits) 241 V_(CRm, 11, 8, Bits) \
242 \
243 /* NEON load/store */ \
244 V_(NEONLoad, 22, 22, Bits) \
245 \
246 /* NEON Modified Immediate fields */ \
247 V_(ImmNEONabc, 18, 16, Bits) \
248 V_(ImmNEONdefgh, 9, 5, Bits) \
249 V_(NEONModImmOp, 29, 29, Bits) \
250 V_(NEONCmode, 15, 12, Bits) \
251 \
252 /* NEON Shift Immediate fields */ \
253 V_(ImmNEONImmhImmb, 22, 16, Bits) \
254 V_(ImmNEONImmh, 22, 19, Bits) \
255 V_(ImmNEONImmb, 18, 16, Bits)
203 256
204 #define SYSTEM_REGISTER_FIELDS_LIST(V_, M_) \ 257 #define SYSTEM_REGISTER_FIELDS_LIST(V_, M_) \
205 /* NZCV */ \ 258 /* NZCV */ \
206 V_(Flags, 31, 28, Bits, uint32_t) \ 259 V_(Flags, 31, 28, Bits, uint32_t) \
207 V_(N, 31, 31, Bits, bool) \ 260 V_(N, 31, 31, Bits, bool) \
208 V_(Z, 30, 30, Bits, bool) \ 261 V_(Z, 30, 30, Bits, bool) \
209 V_(C, 29, 29, Bits, bool) \ 262 V_(C, 29, 29, Bits, bool) \
210 V_(V, 28, 28, Bits, uint32_t) \ 263 V_(V, 28, 28, Bits, uint32_t) \
211 M_(NZCV, Flags_mask) \ 264 M_(NZCV, Flags_mask) \
212 \ 265 \
(...skipping 111 matching lines...) Expand 10 before | Expand all | Expand 10 after
324 FPLessThanFlag = NFlag, 377 FPLessThanFlag = NFlag,
325 FPGreaterThanFlag = CFlag, 378 FPGreaterThanFlag = CFlag,
326 FPUnorderedFlag = CVFlag 379 FPUnorderedFlag = CVFlag
327 }; 380 };
328 381
329 enum Shift { 382 enum Shift {
330 NO_SHIFT = -1, 383 NO_SHIFT = -1,
331 LSL = 0x0, 384 LSL = 0x0,
332 LSR = 0x1, 385 LSR = 0x1,
333 ASR = 0x2, 386 ASR = 0x2,
334 ROR = 0x3 387 ROR = 0x3,
388 MSL = 0x4
335 }; 389 };
336 390
337 enum Extend { 391 enum Extend {
338 NO_EXTEND = -1, 392 NO_EXTEND = -1,
339 UXTB = 0, 393 UXTB = 0,
340 UXTH = 1, 394 UXTH = 1,
341 UXTW = 2, 395 UXTW = 2,
342 UXTX = 3, 396 UXTX = 3,
343 SXTB = 4, 397 SXTB = 4,
344 SXTH = 5, 398 SXTH = 5,
(...skipping 61 matching lines...) Expand 10 before | Expand all | Expand 10 after
406 460
407 461
408 // Generic fields. 462 // Generic fields.
409 enum GenericInstrField { 463 enum GenericInstrField {
410 SixtyFourBits = 0x80000000, 464 SixtyFourBits = 0x80000000,
411 ThirtyTwoBits = 0x00000000, 465 ThirtyTwoBits = 0x00000000,
412 FP32 = 0x00000000, 466 FP32 = 0x00000000,
413 FP64 = 0x00400000 467 FP64 = 0x00400000
414 }; 468 };
415 469
470 enum NEONFormatField {
471 NEONFormatFieldMask = 0x40C00000,
472 NEON_Q = 0x40000000,
473 NEON_8B = 0x00000000,
474 NEON_16B = NEON_8B | NEON_Q,
475 NEON_4H = 0x00400000,
476 NEON_8H = NEON_4H | NEON_Q,
477 NEON_2S = 0x00800000,
478 NEON_4S = NEON_2S | NEON_Q,
479 NEON_1D = 0x00C00000,
480 NEON_2D = 0x00C00000 | NEON_Q
481 };
482
483 enum NEONFPFormatField {
484 NEONFPFormatFieldMask = 0x40400000,
485 NEON_FP_2S = FP32,
486 NEON_FP_4S = FP32 | NEON_Q,
487 NEON_FP_2D = FP64 | NEON_Q
488 };
489
490 enum NEONLSFormatField {
491 NEONLSFormatFieldMask = 0x40000C00,
492 LS_NEON_8B = 0x00000000,
493 LS_NEON_16B = LS_NEON_8B | NEON_Q,
494 LS_NEON_4H = 0x00000400,
495 LS_NEON_8H = LS_NEON_4H | NEON_Q,
496 LS_NEON_2S = 0x00000800,
497 LS_NEON_4S = LS_NEON_2S | NEON_Q,
498 LS_NEON_1D = 0x00000C00,
499 LS_NEON_2D = LS_NEON_1D | NEON_Q
500 };
501
502 enum NEONScalarFormatField {
503 NEONScalarFormatFieldMask = 0x00C00000,
504 NEONScalar = 0x10000000,
505 NEON_B = 0x00000000,
506 NEON_H = 0x00400000,
507 NEON_S = 0x00800000,
508 NEON_D = 0x00C00000
509 };
510
416 // PC relative addressing. 511 // PC relative addressing.
417 enum PCRelAddressingOp { 512 enum PCRelAddressingOp {
418 PCRelAddressingFixed = 0x10000000, 513 PCRelAddressingFixed = 0x10000000,
419 PCRelAddressingFMask = 0x1F000000, 514 PCRelAddressingFMask = 0x1F000000,
420 PCRelAddressingMask = 0x9F000000, 515 PCRelAddressingMask = 0x9F000000,
421 ADR = PCRelAddressingFixed | 0x00000000, 516 ADR = PCRelAddressingFixed | 0x00000000,
422 ADRP = PCRelAddressingFixed | 0x80000000 517 ADRP = PCRelAddressingFixed | 0x80000000
423 }; 518 };
424 519
425 // Add/sub (immediate, shifted and extended.) 520 // Add/sub (immediate, shifted and extended.)
(...skipping 273 matching lines...) Expand 10 before | Expand all | Expand 10 after
699 LoadStoreAnyFMask = 0x0a000000, 794 LoadStoreAnyFMask = 0x0a000000,
700 LoadStoreAnyFixed = 0x08000000 795 LoadStoreAnyFixed = 0x08000000
701 }; 796 };
702 797
703 // Any load pair or store pair. 798 // Any load pair or store pair.
704 enum LoadStorePairAnyOp { 799 enum LoadStorePairAnyOp {
705 LoadStorePairAnyFMask = 0x3a000000, 800 LoadStorePairAnyFMask = 0x3a000000,
706 LoadStorePairAnyFixed = 0x28000000 801 LoadStorePairAnyFixed = 0x28000000
707 }; 802 };
708 803
709 #define LOAD_STORE_PAIR_OP_LIST(V) \ 804 #define LOAD_STORE_PAIR_OP_LIST(V) \
710 V(STP, w, 0x00000000), \ 805 V(STP, w, 0x00000000) \
711 V(LDP, w, 0x00400000), \ 806 , V(LDP, w, 0x00400000), V(LDPSW, x, 0x40400000), V(STP, x, 0x80000000), \
712 V(LDPSW, x, 0x40400000), \ 807 V(LDP, x, 0x80400000), V(STP, s, 0x04000000), V(LDP, s, 0x04400000), \
713 V(STP, x, 0x80000000), \ 808 V(STP, d, 0x44000000), V(LDP, d, 0x44400000), V(STP, q, 0x84000000), \
714 V(LDP, x, 0x80400000), \ 809 V(LDP, q, 0x84400000)
715 V(STP, s, 0x04000000), \
716 V(LDP, s, 0x04400000), \
717 V(STP, d, 0x44000000), \
718 V(LDP, d, 0x44400000)
719 810
720 // Load/store pair (post, pre and offset.) 811 // Load/store pair (post, pre and offset.)
721 enum LoadStorePairOp { 812 enum LoadStorePairOp {
722 LoadStorePairMask = 0xC4400000, 813 LoadStorePairMask = 0xC4400000,
723 LoadStorePairLBit = 1 << 22, 814 LoadStorePairLBit = 1 << 22,
724 #define LOAD_STORE_PAIR(A, B, C) \ 815 #define LOAD_STORE_PAIR(A, B, C) \
725 A##_##B = C 816 A##_##B = C
726 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR) 817 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR)
727 #undef LOAD_STORE_PAIR 818 #undef LOAD_STORE_PAIR
728 }; 819 };
(...skipping 34 matching lines...) Expand 10 before | Expand all | Expand 10 after
763 LoadLiteralFMask = 0x3B000000, 854 LoadLiteralFMask = 0x3B000000,
764 LoadLiteralMask = 0xFF000000, 855 LoadLiteralMask = 0xFF000000,
765 LDR_w_lit = LoadLiteralFixed | 0x00000000, 856 LDR_w_lit = LoadLiteralFixed | 0x00000000,
766 LDR_x_lit = LoadLiteralFixed | 0x40000000, 857 LDR_x_lit = LoadLiteralFixed | 0x40000000,
767 LDRSW_x_lit = LoadLiteralFixed | 0x80000000, 858 LDRSW_x_lit = LoadLiteralFixed | 0x80000000,
768 PRFM_lit = LoadLiteralFixed | 0xC0000000, 859 PRFM_lit = LoadLiteralFixed | 0xC0000000,
769 LDR_s_lit = LoadLiteralFixed | 0x04000000, 860 LDR_s_lit = LoadLiteralFixed | 0x04000000,
770 LDR_d_lit = LoadLiteralFixed | 0x44000000 861 LDR_d_lit = LoadLiteralFixed | 0x44000000
771 }; 862 };
772 863
773 #define LOAD_STORE_OP_LIST(V) \ 864 #define LOAD_STORE_OP_LIST(V) \
774 V(ST, RB, w, 0x00000000), \ 865 V(ST, RB, w, 0x00000000) \
775 V(ST, RH, w, 0x40000000), \ 866 , V(ST, RH, w, 0x40000000), V(ST, R, w, 0x80000000), \
776 V(ST, R, w, 0x80000000), \ 867 V(ST, R, x, 0xC0000000), V(LD, RB, w, 0x00400000), \
777 V(ST, R, x, 0xC0000000), \ 868 V(LD, RH, w, 0x40400000), V(LD, R, w, 0x80400000), \
778 V(LD, RB, w, 0x00400000), \ 869 V(LD, R, x, 0xC0400000), V(LD, RSB, x, 0x00800000), \
779 V(LD, RH, w, 0x40400000), \ 870 V(LD, RSH, x, 0x40800000), V(LD, RSW, x, 0x80800000), \
780 V(LD, R, w, 0x80400000), \ 871 V(LD, RSB, w, 0x00C00000), V(LD, RSH, w, 0x40C00000), \
781 V(LD, R, x, 0xC0400000), \ 872 V(ST, R, b, 0x04000000), V(ST, R, h, 0x44000000), \
782 V(LD, RSB, x, 0x00800000), \ 873 V(ST, R, s, 0x84000000), V(ST, R, d, 0xC4000000), \
783 V(LD, RSH, x, 0x40800000), \ 874 V(ST, R, q, 0x04800000), V(LD, R, b, 0x04400000), \
784 V(LD, RSW, x, 0x80800000), \ 875 V(LD, R, h, 0x44400000), V(LD, R, s, 0x84400000), \
785 V(LD, RSB, w, 0x00C00000), \ 876 V(LD, R, d, 0xC4400000), V(LD, R, q, 0x04C00000)
786 V(LD, RSH, w, 0x40C00000), \
787 V(ST, R, s, 0x84000000), \
788 V(ST, R, d, 0xC4000000), \
789 V(LD, R, s, 0x84400000), \
790 V(LD, R, d, 0xC4400000)
791
792 877
793 // Load/store unscaled offset. 878 // Load/store unscaled offset.
794 enum LoadStoreUnscaledOffsetOp { 879 enum LoadStoreUnscaledOffsetOp {
795 LoadStoreUnscaledOffsetFixed = 0x38000000, 880 LoadStoreUnscaledOffsetFixed = 0x38000000,
796 LoadStoreUnscaledOffsetFMask = 0x3B200C00, 881 LoadStoreUnscaledOffsetFMask = 0x3B200C00,
797 LoadStoreUnscaledOffsetMask = 0xFFE00C00, 882 LoadStoreUnscaledOffsetMask = 0xFFE00C00,
798 #define LOAD_STORE_UNSCALED(A, B, C, D) \ 883 #define LOAD_STORE_UNSCALED(A, B, C, D) \
799 A##U##B##_##C = LoadStoreUnscaledOffsetFixed | D 884 A##U##B##_##C = LoadStoreUnscaledOffsetFixed | D
800 LOAD_STORE_OP_LIST(LOAD_STORE_UNSCALED) 885 LOAD_STORE_OP_LIST(LOAD_STORE_UNSCALED)
801 #undef LOAD_STORE_UNSCALED 886 #undef LOAD_STORE_UNSCALED
802 }; 887 };
803 888
804 // Load/store (post, pre, offset and unsigned.) 889 // Load/store (post, pre, offset and unsigned.)
805 enum LoadStoreOp { 890 enum LoadStoreOp {
806 LoadStoreOpMask = 0xC4C00000, 891 LoadStoreMask = 0xC4C00000,
807 #define LOAD_STORE(A, B, C, D) \ 892 #define LOAD_STORE(A, B, C, D) A##B##_##C = D
808 A##B##_##C = D
809 LOAD_STORE_OP_LIST(LOAD_STORE), 893 LOAD_STORE_OP_LIST(LOAD_STORE),
810 #undef LOAD_STORE 894 #undef LOAD_STORE
811 PRFM = 0xC0800000 895 PRFM = 0xC0800000
812 }; 896 };
813 897
814 // Load/store post index. 898 // Load/store post index.
815 enum LoadStorePostIndex { 899 enum LoadStorePostIndex {
816 LoadStorePostIndexFixed = 0x38000400, 900 LoadStorePostIndexFixed = 0x38000400,
817 LoadStorePostIndexFMask = 0x3B200C00, 901 LoadStorePostIndexFMask = 0x3B200C00,
818 LoadStorePostIndexMask = 0xFFE00C00, 902 LoadStorePostIndexMask = 0xFFE00C00,
819 #define LOAD_STORE_POST_INDEX(A, B, C, D) \ 903 #define LOAD_STORE_POST_INDEX(A, B, C, D) \
820 A##B##_##C##_post = LoadStorePostIndexFixed | D 904 A##B##_##C##_post = LoadStorePostIndexFixed | D
(...skipping 228 matching lines...) Expand 10 before | Expand all | Expand 10 after
1049 FPImmediateFMask = 0x5F201C00, 1133 FPImmediateFMask = 0x5F201C00,
1050 FPImmediateMask = 0xFFE01C00, 1134 FPImmediateMask = 0xFFE01C00,
1051 FMOV_s_imm = FPImmediateFixed | 0x00000000, 1135 FMOV_s_imm = FPImmediateFixed | 0x00000000,
1052 FMOV_d_imm = FPImmediateFixed | FP64 | 0x00000000 1136 FMOV_d_imm = FPImmediateFixed | FP64 | 0x00000000
1053 }; 1137 };
1054 1138
1055 // Floating point data processing 1 source. 1139 // Floating point data processing 1 source.
1056 enum FPDataProcessing1SourceOp { 1140 enum FPDataProcessing1SourceOp {
1057 FPDataProcessing1SourceFixed = 0x1E204000, 1141 FPDataProcessing1SourceFixed = 0x1E204000,
1058 FPDataProcessing1SourceFMask = 0x5F207C00, 1142 FPDataProcessing1SourceFMask = 0x5F207C00,
1059 FPDataProcessing1SourceMask = 0xFFFFFC00, 1143 FPDataProcessing1SourceMask = 0xFFFFFC00,
1060 FMOV_s = FPDataProcessing1SourceFixed | 0x00000000, 1144 FMOV_s = FPDataProcessing1SourceFixed | 0x00000000,
1061 FMOV_d = FPDataProcessing1SourceFixed | FP64 | 0x00000000, 1145 FMOV_d = FPDataProcessing1SourceFixed | FP64 | 0x00000000,
1062 FMOV = FMOV_s, 1146 FMOV = FMOV_s,
1063 FABS_s = FPDataProcessing1SourceFixed | 0x00008000, 1147 FABS_s = FPDataProcessing1SourceFixed | 0x00008000,
1064 FABS_d = FPDataProcessing1SourceFixed | FP64 | 0x00008000, 1148 FABS_d = FPDataProcessing1SourceFixed | FP64 | 0x00008000,
1065 FABS = FABS_s, 1149 FABS = FABS_s,
1066 FNEG_s = FPDataProcessing1SourceFixed | 0x00010000, 1150 FNEG_s = FPDataProcessing1SourceFixed | 0x00010000,
1067 FNEG_d = FPDataProcessing1SourceFixed | FP64 | 0x00010000, 1151 FNEG_d = FPDataProcessing1SourceFixed | FP64 | 0x00010000,
1068 FNEG = FNEG_s, 1152 FNEG = FNEG_s,
1069 FSQRT_s = FPDataProcessing1SourceFixed | 0x00018000, 1153 FSQRT_s = FPDataProcessing1SourceFixed | 0x00018000,
1070 FSQRT_d = FPDataProcessing1SourceFixed | FP64 | 0x00018000, 1154 FSQRT_d = FPDataProcessing1SourceFixed | FP64 | 0x00018000,
1071 FSQRT = FSQRT_s, 1155 FSQRT = FSQRT_s,
1072 FCVT_ds = FPDataProcessing1SourceFixed | 0x00028000, 1156 FCVT_ds = FPDataProcessing1SourceFixed | 0x00028000,
1073 FCVT_sd = FPDataProcessing1SourceFixed | FP64 | 0x00020000, 1157 FCVT_sd = FPDataProcessing1SourceFixed | FP64 | 0x00020000,
1158 FCVT_hs = FPDataProcessing1SourceFixed | 0x00038000,
1159 FCVT_hd = FPDataProcessing1SourceFixed | FP64 | 0x00038000,
1160 FCVT_sh = FPDataProcessing1SourceFixed | 0x00C20000,
1161 FCVT_dh = FPDataProcessing1SourceFixed | 0x00C28000,
1074 FRINTN_s = FPDataProcessing1SourceFixed | 0x00040000, 1162 FRINTN_s = FPDataProcessing1SourceFixed | 0x00040000,
1075 FRINTN_d = FPDataProcessing1SourceFixed | FP64 | 0x00040000, 1163 FRINTN_d = FPDataProcessing1SourceFixed | FP64 | 0x00040000,
1076 FRINTN = FRINTN_s, 1164 FRINTN = FRINTN_s,
1077 FRINTP_s = FPDataProcessing1SourceFixed | 0x00048000, 1165 FRINTP_s = FPDataProcessing1SourceFixed | 0x00048000,
1078 FRINTP_d = FPDataProcessing1SourceFixed | FP64 | 0x00048000, 1166 FRINTP_d = FPDataProcessing1SourceFixed | FP64 | 0x00048000,
1079 FRINTP = FRINTP_s, 1167 FRINTP = FRINTP_s,
1080 FRINTM_s = FPDataProcessing1SourceFixed | 0x00050000, 1168 FRINTM_s = FPDataProcessing1SourceFixed | 0x00050000,
1081 FRINTM_d = FPDataProcessing1SourceFixed | FP64 | 0x00050000, 1169 FRINTM_d = FPDataProcessing1SourceFixed | FP64 | 0x00050000,
1082 FRINTM = FRINTM_s, 1170 FRINTM = FRINTM_s,
1083 FRINTZ_s = FPDataProcessing1SourceFixed | 0x00058000, 1171 FRINTZ_s = FPDataProcessing1SourceFixed | 0x00058000,
1084 FRINTZ_d = FPDataProcessing1SourceFixed | FP64 | 0x00058000, 1172 FRINTZ_d = FPDataProcessing1SourceFixed | FP64 | 0x00058000,
1085 FRINTZ = FRINTZ_s, 1173 FRINTZ = FRINTZ_s,
1086 FRINTA_s = FPDataProcessing1SourceFixed | 0x00060000, 1174 FRINTA_s = FPDataProcessing1SourceFixed | 0x00060000,
1087 FRINTA_d = FPDataProcessing1SourceFixed | FP64 | 0x00060000, 1175 FRINTA_d = FPDataProcessing1SourceFixed | FP64 | 0x00060000,
1088 FRINTA = FRINTA_s, 1176 FRINTA = FRINTA_s,
1089 FRINTX_s = FPDataProcessing1SourceFixed | 0x00070000, 1177 FRINTX_s = FPDataProcessing1SourceFixed | 0x00070000,
1090 FRINTX_d = FPDataProcessing1SourceFixed | FP64 | 0x00070000, 1178 FRINTX_d = FPDataProcessing1SourceFixed | FP64 | 0x00070000,
1091 FRINTX = FRINTX_s, 1179 FRINTX = FRINTX_s,
1092 FRINTI_s = FPDataProcessing1SourceFixed | 0x00078000, 1180 FRINTI_s = FPDataProcessing1SourceFixed | 0x00078000,
1093 FRINTI_d = FPDataProcessing1SourceFixed | FP64 | 0x00078000, 1181 FRINTI_d = FPDataProcessing1SourceFixed | FP64 | 0x00078000,
1094 FRINTI = FRINTI_s 1182 FRINTI = FRINTI_s
1095 }; 1183 };
1096 1184
1097 // Floating point data processing 2 source. 1185 // Floating point data processing 2 source.
1098 enum FPDataProcessing2SourceOp { 1186 enum FPDataProcessing2SourceOp {
1099 FPDataProcessing2SourceFixed = 0x1E200800, 1187 FPDataProcessing2SourceFixed = 0x1E200800,
1100 FPDataProcessing2SourceFMask = 0x5F200C00, 1188 FPDataProcessing2SourceFMask = 0x5F200C00,
1101 FPDataProcessing2SourceMask = 0xFFE0FC00, 1189 FPDataProcessing2SourceMask = 0xFFE0FC00,
1102 FMUL = FPDataProcessing2SourceFixed | 0x00000000, 1190 FMUL = FPDataProcessing2SourceFixed | 0x00000000,
1103 FMUL_s = FMUL, 1191 FMUL_s = FMUL,
1104 FMUL_d = FMUL | FP64, 1192 FMUL_d = FMUL | FP64,
(...skipping 35 matching lines...) Expand 10 before | Expand all | Expand 10 after
1140 FMADD_d = FPDataProcessing3SourceFixed | 0x00400000, 1228 FMADD_d = FPDataProcessing3SourceFixed | 0x00400000,
1141 FMSUB_d = FPDataProcessing3SourceFixed | 0x00408000, 1229 FMSUB_d = FPDataProcessing3SourceFixed | 0x00408000,
1142 FNMADD_d = FPDataProcessing3SourceFixed | 0x00600000, 1230 FNMADD_d = FPDataProcessing3SourceFixed | 0x00600000,
1143 FNMSUB_d = FPDataProcessing3SourceFixed | 0x00608000 1231 FNMSUB_d = FPDataProcessing3SourceFixed | 0x00608000
1144 }; 1232 };
1145 1233
1146 // Conversion between floating point and integer. 1234 // Conversion between floating point and integer.
1147 enum FPIntegerConvertOp { 1235 enum FPIntegerConvertOp {
1148 FPIntegerConvertFixed = 0x1E200000, 1236 FPIntegerConvertFixed = 0x1E200000,
1149 FPIntegerConvertFMask = 0x5F20FC00, 1237 FPIntegerConvertFMask = 0x5F20FC00,
1150 FPIntegerConvertMask = 0xFFFFFC00, 1238 FPIntegerConvertMask = 0xFFFFFC00,
1151 FCVTNS = FPIntegerConvertFixed | 0x00000000, 1239 FCVTNS = FPIntegerConvertFixed | 0x00000000,
1152 FCVTNS_ws = FCVTNS, 1240 FCVTNS_ws = FCVTNS,
1153 FCVTNS_xs = FCVTNS | SixtyFourBits, 1241 FCVTNS_xs = FCVTNS | SixtyFourBits,
1154 FCVTNS_wd = FCVTNS | FP64, 1242 FCVTNS_wd = FCVTNS | FP64,
1155 FCVTNS_xd = FCVTNS | SixtyFourBits | FP64, 1243 FCVTNS_xd = FCVTNS | SixtyFourBits | FP64,
1156 FCVTNU = FPIntegerConvertFixed | 0x00010000, 1244 FCVTNU = FPIntegerConvertFixed | 0x00010000,
1157 FCVTNU_ws = FCVTNU, 1245 FCVTNU_ws = FCVTNU,
1158 FCVTNU_xs = FCVTNU | SixtyFourBits, 1246 FCVTNU_xs = FCVTNU | SixtyFourBits,
1159 FCVTNU_wd = FCVTNU | FP64, 1247 FCVTNU_wd = FCVTNU | FP64,
1160 FCVTNU_xd = FCVTNU | SixtyFourBits | FP64, 1248 FCVTNU_xd = FCVTNU | SixtyFourBits | FP64,
1161 FCVTPS = FPIntegerConvertFixed | 0x00080000, 1249 FCVTPS = FPIntegerConvertFixed | 0x00080000,
1162 FCVTPS_ws = FCVTPS, 1250 FCVTPS_ws = FCVTPS,
1163 FCVTPS_xs = FCVTPS | SixtyFourBits, 1251 FCVTPS_xs = FCVTPS | SixtyFourBits,
1164 FCVTPS_wd = FCVTPS | FP64, 1252 FCVTPS_wd = FCVTPS | FP64,
1165 FCVTPS_xd = FCVTPS | SixtyFourBits | FP64, 1253 FCVTPS_xd = FCVTPS | SixtyFourBits | FP64,
1166 FCVTPU = FPIntegerConvertFixed | 0x00090000, 1254 FCVTPU = FPIntegerConvertFixed | 0x00090000,
1167 FCVTPU_ws = FCVTPU, 1255 FCVTPU_ws = FCVTPU,
1168 FCVTPU_xs = FCVTPU | SixtyFourBits, 1256 FCVTPU_xs = FCVTPU | SixtyFourBits,
1169 FCVTPU_wd = FCVTPU | FP64, 1257 FCVTPU_wd = FCVTPU | FP64,
1170 FCVTPU_xd = FCVTPU | SixtyFourBits | FP64, 1258 FCVTPU_xd = FCVTPU | SixtyFourBits | FP64,
1171 FCVTMS = FPIntegerConvertFixed | 0x00100000, 1259 FCVTMS = FPIntegerConvertFixed | 0x00100000,
1172 FCVTMS_ws = FCVTMS, 1260 FCVTMS_ws = FCVTMS,
1173 FCVTMS_xs = FCVTMS | SixtyFourBits, 1261 FCVTMS_xs = FCVTMS | SixtyFourBits,
1174 FCVTMS_wd = FCVTMS | FP64, 1262 FCVTMS_wd = FCVTMS | FP64,
1175 FCVTMS_xd = FCVTMS | SixtyFourBits | FP64, 1263 FCVTMS_xd = FCVTMS | SixtyFourBits | FP64,
1176 FCVTMU = FPIntegerConvertFixed | 0x00110000, 1264 FCVTMU = FPIntegerConvertFixed | 0x00110000,
1177 FCVTMU_ws = FCVTMU, 1265 FCVTMU_ws = FCVTMU,
1178 FCVTMU_xs = FCVTMU | SixtyFourBits, 1266 FCVTMU_xs = FCVTMU | SixtyFourBits,
1179 FCVTMU_wd = FCVTMU | FP64, 1267 FCVTMU_wd = FCVTMU | FP64,
1180 FCVTMU_xd = FCVTMU | SixtyFourBits | FP64, 1268 FCVTMU_xd = FCVTMU | SixtyFourBits | FP64,
1181 FCVTZS = FPIntegerConvertFixed | 0x00180000, 1269 FCVTZS = FPIntegerConvertFixed | 0x00180000,
1182 FCVTZS_ws = FCVTZS, 1270 FCVTZS_ws = FCVTZS,
1183 FCVTZS_xs = FCVTZS | SixtyFourBits, 1271 FCVTZS_xs = FCVTZS | SixtyFourBits,
1184 FCVTZS_wd = FCVTZS | FP64, 1272 FCVTZS_wd = FCVTZS | FP64,
1185 FCVTZS_xd = FCVTZS | SixtyFourBits | FP64, 1273 FCVTZS_xd = FCVTZS | SixtyFourBits | FP64,
1186 FCVTZU = FPIntegerConvertFixed | 0x00190000, 1274 FCVTZU = FPIntegerConvertFixed | 0x00190000,
1187 FCVTZU_ws = FCVTZU, 1275 FCVTZU_ws = FCVTZU,
1188 FCVTZU_xs = FCVTZU | SixtyFourBits, 1276 FCVTZU_xs = FCVTZU | SixtyFourBits,
1189 FCVTZU_wd = FCVTZU | FP64, 1277 FCVTZU_wd = FCVTZU | FP64,
1190 FCVTZU_xd = FCVTZU | SixtyFourBits | FP64, 1278 FCVTZU_xd = FCVTZU | SixtyFourBits | FP64,
1191 SCVTF = FPIntegerConvertFixed | 0x00020000, 1279 SCVTF = FPIntegerConvertFixed | 0x00020000,
1192 SCVTF_sw = SCVTF, 1280 SCVTF_sw = SCVTF,
1193 SCVTF_sx = SCVTF | SixtyFourBits, 1281 SCVTF_sx = SCVTF | SixtyFourBits,
1194 SCVTF_dw = SCVTF | FP64, 1282 SCVTF_dw = SCVTF | FP64,
1195 SCVTF_dx = SCVTF | SixtyFourBits | FP64, 1283 SCVTF_dx = SCVTF | SixtyFourBits | FP64,
1196 UCVTF = FPIntegerConvertFixed | 0x00030000, 1284 UCVTF = FPIntegerConvertFixed | 0x00030000,
1197 UCVTF_sw = UCVTF, 1285 UCVTF_sw = UCVTF,
1198 UCVTF_sx = UCVTF | SixtyFourBits, 1286 UCVTF_sx = UCVTF | SixtyFourBits,
1199 UCVTF_dw = UCVTF | FP64, 1287 UCVTF_dw = UCVTF | FP64,
1200 UCVTF_dx = UCVTF | SixtyFourBits | FP64, 1288 UCVTF_dx = UCVTF | SixtyFourBits | FP64,
1201 FCVTAS = FPIntegerConvertFixed | 0x00040000, 1289 FCVTAS = FPIntegerConvertFixed | 0x00040000,
1202 FCVTAS_ws = FCVTAS, 1290 FCVTAS_ws = FCVTAS,
1203 FCVTAS_xs = FCVTAS | SixtyFourBits, 1291 FCVTAS_xs = FCVTAS | SixtyFourBits,
1204 FCVTAS_wd = FCVTAS | FP64, 1292 FCVTAS_wd = FCVTAS | FP64,
1205 FCVTAS_xd = FCVTAS | SixtyFourBits | FP64, 1293 FCVTAS_xd = FCVTAS | SixtyFourBits | FP64,
1206 FCVTAU = FPIntegerConvertFixed | 0x00050000, 1294 FCVTAU = FPIntegerConvertFixed | 0x00050000,
1207 FCVTAU_ws = FCVTAU, 1295 FCVTAU_ws = FCVTAU,
1208 FCVTAU_xs = FCVTAU | SixtyFourBits, 1296 FCVTAU_xs = FCVTAU | SixtyFourBits,
1209 FCVTAU_wd = FCVTAU | FP64, 1297 FCVTAU_wd = FCVTAU | FP64,
1210 FCVTAU_xd = FCVTAU | SixtyFourBits | FP64, 1298 FCVTAU_xd = FCVTAU | SixtyFourBits | FP64,
1211 FMOV_ws = FPIntegerConvertFixed | 0x00060000, 1299 FMOV_ws = FPIntegerConvertFixed | 0x00060000,
1212 FMOV_sw = FPIntegerConvertFixed | 0x00070000, 1300 FMOV_sw = FPIntegerConvertFixed | 0x00070000,
1213 FMOV_xd = FMOV_ws | SixtyFourBits | FP64, 1301 FMOV_xd = FMOV_ws | SixtyFourBits | FP64,
1214 FMOV_dx = FMOV_sw | SixtyFourBits | FP64 1302 FMOV_dx = FMOV_sw | SixtyFourBits | FP64,
1303 FMOV_d1_x = FPIntegerConvertFixed | SixtyFourBits | 0x008F0000,
1304 FMOV_x_d1 = FPIntegerConvertFixed | SixtyFourBits | 0x008E0000
1215 }; 1305 };
1216 1306
1217 // Conversion between fixed point and floating point. 1307 // Conversion between fixed point and floating point.
1218 enum FPFixedPointConvertOp { 1308 enum FPFixedPointConvertOp {
1219 FPFixedPointConvertFixed = 0x1E000000, 1309 FPFixedPointConvertFixed = 0x1E000000,
1220 FPFixedPointConvertFMask = 0x5F200000, 1310 FPFixedPointConvertFMask = 0x5F200000,
1221 FPFixedPointConvertMask = 0xFFFF0000, 1311 FPFixedPointConvertMask = 0xFFFF0000,
1222 FCVTZS_fixed = FPFixedPointConvertFixed | 0x00180000, 1312 FCVTZS_fixed = FPFixedPointConvertFixed | 0x00180000,
1223 FCVTZS_ws_fixed = FCVTZS_fixed, 1313 FCVTZS_ws_fixed = FCVTZS_fixed,
1224 FCVTZS_xs_fixed = FCVTZS_fixed | SixtyFourBits, 1314 FCVTZS_xs_fixed = FCVTZS_fixed | SixtyFourBits,
1225 FCVTZS_wd_fixed = FCVTZS_fixed | FP64, 1315 FCVTZS_wd_fixed = FCVTZS_fixed | FP64,
1226 FCVTZS_xd_fixed = FCVTZS_fixed | SixtyFourBits | FP64, 1316 FCVTZS_xd_fixed = FCVTZS_fixed | SixtyFourBits | FP64,
1227 FCVTZU_fixed = FPFixedPointConvertFixed | 0x00190000, 1317 FCVTZU_fixed = FPFixedPointConvertFixed | 0x00190000,
1228 FCVTZU_ws_fixed = FCVTZU_fixed, 1318 FCVTZU_ws_fixed = FCVTZU_fixed,
1229 FCVTZU_xs_fixed = FCVTZU_fixed | SixtyFourBits, 1319 FCVTZU_xs_fixed = FCVTZU_fixed | SixtyFourBits,
1230 FCVTZU_wd_fixed = FCVTZU_fixed | FP64, 1320 FCVTZU_wd_fixed = FCVTZU_fixed | FP64,
1231 FCVTZU_xd_fixed = FCVTZU_fixed | SixtyFourBits | FP64, 1321 FCVTZU_xd_fixed = FCVTZU_fixed | SixtyFourBits | FP64,
1232 SCVTF_fixed = FPFixedPointConvertFixed | 0x00020000, 1322 SCVTF_fixed = FPFixedPointConvertFixed | 0x00020000,
1233 SCVTF_sw_fixed = SCVTF_fixed, 1323 SCVTF_sw_fixed = SCVTF_fixed,
1234 SCVTF_sx_fixed = SCVTF_fixed | SixtyFourBits, 1324 SCVTF_sx_fixed = SCVTF_fixed | SixtyFourBits,
1235 SCVTF_dw_fixed = SCVTF_fixed | FP64, 1325 SCVTF_dw_fixed = SCVTF_fixed | FP64,
1236 SCVTF_dx_fixed = SCVTF_fixed | SixtyFourBits | FP64, 1326 SCVTF_dx_fixed = SCVTF_fixed | SixtyFourBits | FP64,
1237 UCVTF_fixed = FPFixedPointConvertFixed | 0x00030000, 1327 UCVTF_fixed = FPFixedPointConvertFixed | 0x00030000,
1238 UCVTF_sw_fixed = UCVTF_fixed, 1328 UCVTF_sw_fixed = UCVTF_fixed,
1239 UCVTF_sx_fixed = UCVTF_fixed | SixtyFourBits, 1329 UCVTF_sx_fixed = UCVTF_fixed | SixtyFourBits,
1240 UCVTF_dw_fixed = UCVTF_fixed | FP64, 1330 UCVTF_dw_fixed = UCVTF_fixed | FP64,
1241 UCVTF_dx_fixed = UCVTF_fixed | SixtyFourBits | FP64 1331 UCVTF_dx_fixed = UCVTF_fixed | SixtyFourBits | FP64
1242 }; 1332 };
1243 1333
1334 // NEON instructions with two register operands.
1335 enum NEON2RegMiscOp {
1336 NEON2RegMiscFixed = 0x0E200800,
1337 NEON2RegMiscFMask = 0x9F3E0C00,
1338 NEON2RegMiscMask = 0xBF3FFC00,
1339 NEON2RegMiscUBit = 0x20000000,
1340 NEON_REV64 = NEON2RegMiscFixed | 0x00000000,
1341 NEON_REV32 = NEON2RegMiscFixed | 0x20000000,
1342 NEON_REV16 = NEON2RegMiscFixed | 0x00001000,
1343 NEON_SADDLP = NEON2RegMiscFixed | 0x00002000,
1344 NEON_UADDLP = NEON_SADDLP | NEON2RegMiscUBit,
1345 NEON_SUQADD = NEON2RegMiscFixed | 0x00003000,
1346 NEON_USQADD = NEON_SUQADD | NEON2RegMiscUBit,
1347 NEON_CLS = NEON2RegMiscFixed | 0x00004000,
1348 NEON_CLZ = NEON2RegMiscFixed | 0x20004000,
1349 NEON_CNT = NEON2RegMiscFixed | 0x00005000,
1350 NEON_RBIT_NOT = NEON2RegMiscFixed | 0x20005000,
1351 NEON_SADALP = NEON2RegMiscFixed | 0x00006000,
1352 NEON_UADALP = NEON_SADALP | NEON2RegMiscUBit,
1353 NEON_SQABS = NEON2RegMiscFixed | 0x00007000,
1354 NEON_SQNEG = NEON2RegMiscFixed | 0x20007000,
1355 NEON_CMGT_zero = NEON2RegMiscFixed | 0x00008000,
1356 NEON_CMGE_zero = NEON2RegMiscFixed | 0x20008000,
1357 NEON_CMEQ_zero = NEON2RegMiscFixed | 0x00009000,
1358 NEON_CMLE_zero = NEON2RegMiscFixed | 0x20009000,
1359 NEON_CMLT_zero = NEON2RegMiscFixed | 0x0000A000,
1360 NEON_ABS = NEON2RegMiscFixed | 0x0000B000,
1361 NEON_NEG = NEON2RegMiscFixed | 0x2000B000,
1362 NEON_XTN = NEON2RegMiscFixed | 0x00012000,
1363 NEON_SQXTUN = NEON2RegMiscFixed | 0x20012000,
1364 NEON_SHLL = NEON2RegMiscFixed | 0x20013000,
1365 NEON_SQXTN = NEON2RegMiscFixed | 0x00014000,
1366 NEON_UQXTN = NEON_SQXTN | NEON2RegMiscUBit,
1367
1368 NEON2RegMiscOpcode = 0x0001F000,
1369 NEON_RBIT_NOT_opcode = NEON_RBIT_NOT & NEON2RegMiscOpcode,
1370 NEON_NEG_opcode = NEON_NEG & NEON2RegMiscOpcode,
1371 NEON_XTN_opcode = NEON_XTN & NEON2RegMiscOpcode,
1372 NEON_UQXTN_opcode = NEON_UQXTN & NEON2RegMiscOpcode,
1373
1374 // These instructions use only one bit of the size field. The other bit is
1375 // used to distinguish between instructions.
1376 NEON2RegMiscFPMask = NEON2RegMiscMask | 0x00800000,
1377 NEON_FABS = NEON2RegMiscFixed | 0x0080F000,
1378 NEON_FNEG = NEON2RegMiscFixed | 0x2080F000,
1379 NEON_FCVTN = NEON2RegMiscFixed | 0x00016000,
1380 NEON_FCVTXN = NEON2RegMiscFixed | 0x20016000,
1381 NEON_FCVTL = NEON2RegMiscFixed | 0x00017000,
1382 NEON_FRINTN = NEON2RegMiscFixed | 0x00018000,
1383 NEON_FRINTA = NEON2RegMiscFixed | 0x20018000,
1384 NEON_FRINTP = NEON2RegMiscFixed | 0x00818000,
1385 NEON_FRINTM = NEON2RegMiscFixed | 0x00019000,
1386 NEON_FRINTX = NEON2RegMiscFixed | 0x20019000,
1387 NEON_FRINTZ = NEON2RegMiscFixed | 0x00819000,
1388 NEON_FRINTI = NEON2RegMiscFixed | 0x20819000,
1389 NEON_FCVTNS = NEON2RegMiscFixed | 0x0001A000,
1390 NEON_FCVTNU = NEON_FCVTNS | NEON2RegMiscUBit,
1391 NEON_FCVTPS = NEON2RegMiscFixed | 0x0081A000,
1392 NEON_FCVTPU = NEON_FCVTPS | NEON2RegMiscUBit,
1393 NEON_FCVTMS = NEON2RegMiscFixed | 0x0001B000,
1394 NEON_FCVTMU = NEON_FCVTMS | NEON2RegMiscUBit,
1395 NEON_FCVTZS = NEON2RegMiscFixed | 0x0081B000,
1396 NEON_FCVTZU = NEON_FCVTZS | NEON2RegMiscUBit,
1397 NEON_FCVTAS = NEON2RegMiscFixed | 0x0001C000,
1398 NEON_FCVTAU = NEON_FCVTAS | NEON2RegMiscUBit,
1399 NEON_FSQRT = NEON2RegMiscFixed | 0x2081F000,
1400 NEON_SCVTF = NEON2RegMiscFixed | 0x0001D000,
1401 NEON_UCVTF = NEON_SCVTF | NEON2RegMiscUBit,
1402 NEON_URSQRTE = NEON2RegMiscFixed | 0x2081C000,
1403 NEON_URECPE = NEON2RegMiscFixed | 0x0081C000,
1404 NEON_FRSQRTE = NEON2RegMiscFixed | 0x2081D000,
1405 NEON_FRECPE = NEON2RegMiscFixed | 0x0081D000,
1406 NEON_FCMGT_zero = NEON2RegMiscFixed | 0x0080C000,
1407 NEON_FCMGE_zero = NEON2RegMiscFixed | 0x2080C000,
1408 NEON_FCMEQ_zero = NEON2RegMiscFixed | 0x0080D000,
1409 NEON_FCMLE_zero = NEON2RegMiscFixed | 0x2080D000,
1410 NEON_FCMLT_zero = NEON2RegMiscFixed | 0x0080E000,
1411
1412 NEON_FCVTL_opcode = NEON_FCVTL & NEON2RegMiscOpcode,
1413 NEON_FCVTN_opcode = NEON_FCVTN & NEON2RegMiscOpcode
1414 };
1415
1416 // NEON instructions with three same-type operands.
1417 enum NEON3SameOp {
1418 NEON3SameFixed = 0x0E200400,
1419 NEON3SameFMask = 0x9F200400,
1420 NEON3SameMask = 0xBF20FC00,
1421 NEON3SameUBit = 0x20000000,
1422 NEON_ADD = NEON3SameFixed | 0x00008000,
1423 NEON_ADDP = NEON3SameFixed | 0x0000B800,
1424 NEON_SHADD = NEON3SameFixed | 0x00000000,
1425 NEON_SHSUB = NEON3SameFixed | 0x00002000,
1426 NEON_SRHADD = NEON3SameFixed | 0x00001000,
1427 NEON_CMEQ = NEON3SameFixed | NEON3SameUBit | 0x00008800,
1428 NEON_CMGE = NEON3SameFixed | 0x00003800,
1429 NEON_CMGT = NEON3SameFixed | 0x00003000,
1430 NEON_CMHI = NEON3SameFixed | NEON3SameUBit | NEON_CMGT,
1431 NEON_CMHS = NEON3SameFixed | NEON3SameUBit | NEON_CMGE,
1432 NEON_CMTST = NEON3SameFixed | 0x00008800,
1433 NEON_MLA = NEON3SameFixed | 0x00009000,
1434 NEON_MLS = NEON3SameFixed | 0x20009000,
1435 NEON_MUL = NEON3SameFixed | 0x00009800,
1436 NEON_PMUL = NEON3SameFixed | 0x20009800,
1437 NEON_SRSHL = NEON3SameFixed | 0x00005000,
1438 NEON_SQSHL = NEON3SameFixed | 0x00004800,
1439 NEON_SQRSHL = NEON3SameFixed | 0x00005800,
1440 NEON_SSHL = NEON3SameFixed | 0x00004000,
1441 NEON_SMAX = NEON3SameFixed | 0x00006000,
1442 NEON_SMAXP = NEON3SameFixed | 0x0000A000,
1443 NEON_SMIN = NEON3SameFixed | 0x00006800,
1444 NEON_SMINP = NEON3SameFixed | 0x0000A800,
1445 NEON_SABD = NEON3SameFixed | 0x00007000,
1446 NEON_SABA = NEON3SameFixed | 0x00007800,
1447 NEON_UABD = NEON3SameFixed | NEON3SameUBit | NEON_SABD,
1448 NEON_UABA = NEON3SameFixed | NEON3SameUBit | NEON_SABA,
1449 NEON_SQADD = NEON3SameFixed | 0x00000800,
1450 NEON_SQSUB = NEON3SameFixed | 0x00002800,
1451 NEON_SUB = NEON3SameFixed | NEON3SameUBit | 0x00008000,
1452 NEON_UHADD = NEON3SameFixed | NEON3SameUBit | NEON_SHADD,
1453 NEON_UHSUB = NEON3SameFixed | NEON3SameUBit | NEON_SHSUB,
1454 NEON_URHADD = NEON3SameFixed | NEON3SameUBit | NEON_SRHADD,
1455 NEON_UMAX = NEON3SameFixed | NEON3SameUBit | NEON_SMAX,
1456 NEON_UMAXP = NEON3SameFixed | NEON3SameUBit | NEON_SMAXP,
1457 NEON_UMIN = NEON3SameFixed | NEON3SameUBit | NEON_SMIN,
1458 NEON_UMINP = NEON3SameFixed | NEON3SameUBit | NEON_SMINP,
1459 NEON_URSHL = NEON3SameFixed | NEON3SameUBit | NEON_SRSHL,
1460 NEON_UQADD = NEON3SameFixed | NEON3SameUBit | NEON_SQADD,
1461 NEON_UQRSHL = NEON3SameFixed | NEON3SameUBit | NEON_SQRSHL,
1462 NEON_UQSHL = NEON3SameFixed | NEON3SameUBit | NEON_SQSHL,
1463 NEON_UQSUB = NEON3SameFixed | NEON3SameUBit | NEON_SQSUB,
1464 NEON_USHL = NEON3SameFixed | NEON3SameUBit | NEON_SSHL,
1465 NEON_SQDMULH = NEON3SameFixed | 0x0000B000,
1466 NEON_SQRDMULH = NEON3SameFixed | 0x2000B000,
1467
1468 // NEON floating point instructions with three same-type operands.
1469 NEON3SameFPFixed = NEON3SameFixed | 0x0000C000,
1470 NEON3SameFPFMask = NEON3SameFMask | 0x0000C000,
1471 NEON3SameFPMask = NEON3SameMask | 0x00800000,
1472 NEON_FADD = NEON3SameFixed | 0x0000D000,
1473 NEON_FSUB = NEON3SameFixed | 0x0080D000,
1474 NEON_FMUL = NEON3SameFixed | 0x2000D800,
1475 NEON_FDIV = NEON3SameFixed | 0x2000F800,
1476 NEON_FMAX = NEON3SameFixed | 0x0000F000,
1477 NEON_FMAXNM = NEON3SameFixed | 0x0000C000,
1478 NEON_FMAXP = NEON3SameFixed | 0x2000F000,
1479 NEON_FMAXNMP = NEON3SameFixed | 0x2000C000,
1480 NEON_FMIN = NEON3SameFixed | 0x0080F000,
1481 NEON_FMINNM = NEON3SameFixed | 0x0080C000,
1482 NEON_FMINP = NEON3SameFixed | 0x2080F000,
1483 NEON_FMINNMP = NEON3SameFixed | 0x2080C000,
1484 NEON_FMLA = NEON3SameFixed | 0x0000C800,
1485 NEON_FMLS = NEON3SameFixed | 0x0080C800,
1486 NEON_FMULX = NEON3SameFixed | 0x0000D800,
1487 NEON_FRECPS = NEON3SameFixed | 0x0000F800,
1488 NEON_FRSQRTS = NEON3SameFixed | 0x0080F800,
1489 NEON_FABD = NEON3SameFixed | 0x2080D000,
1490 NEON_FADDP = NEON3SameFixed | 0x2000D000,
1491 NEON_FCMEQ = NEON3SameFixed | 0x0000E000,
1492 NEON_FCMGE = NEON3SameFixed | 0x2000E000,
1493 NEON_FCMGT = NEON3SameFixed | 0x2080E000,
1494 NEON_FACGE = NEON3SameFixed | 0x2000E800,
1495 NEON_FACGT = NEON3SameFixed | 0x2080E800,
1496
1497 // NEON logical instructions with three same-type operands.
1498 NEON3SameLogicalFixed = NEON3SameFixed | 0x00001800,
1499 NEON3SameLogicalFMask = NEON3SameFMask | 0x0000F800,
1500 NEON3SameLogicalMask = 0xBFE0FC00,
1501 NEON3SameLogicalFormatMask = NEON_Q,
1502 NEON_AND = NEON3SameLogicalFixed | 0x00000000,
1503 NEON_ORR = NEON3SameLogicalFixed | 0x00A00000,
1504 NEON_ORN = NEON3SameLogicalFixed | 0x00C00000,
1505 NEON_EOR = NEON3SameLogicalFixed | 0x20000000,
1506 NEON_BIC = NEON3SameLogicalFixed | 0x00400000,
1507 NEON_BIF = NEON3SameLogicalFixed | 0x20C00000,
1508 NEON_BIT = NEON3SameLogicalFixed | 0x20800000,
1509 NEON_BSL = NEON3SameLogicalFixed | 0x20400000
1510 };
1511
1512 // NEON instructions with three different-type operands.
1513 enum NEON3DifferentOp {
1514 NEON3DifferentFixed = 0x0E200000,
1515 NEON3DifferentFMask = 0x9F200C00,
1516 NEON3DifferentMask = 0xFF20FC00,
1517 NEON_ADDHN = NEON3DifferentFixed | 0x00004000,
1518 NEON_ADDHN2 = NEON_ADDHN | NEON_Q,
1519 NEON_PMULL = NEON3DifferentFixed | 0x0000E000,
1520 NEON_PMULL2 = NEON_PMULL | NEON_Q,
1521 NEON_RADDHN = NEON3DifferentFixed | 0x20004000,
1522 NEON_RADDHN2 = NEON_RADDHN | NEON_Q,
1523 NEON_RSUBHN = NEON3DifferentFixed | 0x20006000,
1524 NEON_RSUBHN2 = NEON_RSUBHN | NEON_Q,
1525 NEON_SABAL = NEON3DifferentFixed | 0x00005000,
1526 NEON_SABAL2 = NEON_SABAL | NEON_Q,
1527 NEON_SABDL = NEON3DifferentFixed | 0x00007000,
1528 NEON_SABDL2 = NEON_SABDL | NEON_Q,
1529 NEON_SADDL = NEON3DifferentFixed | 0x00000000,
1530 NEON_SADDL2 = NEON_SADDL | NEON_Q,
1531 NEON_SADDW = NEON3DifferentFixed | 0x00001000,
1532 NEON_SADDW2 = NEON_SADDW | NEON_Q,
1533 NEON_SMLAL = NEON3DifferentFixed | 0x00008000,
1534 NEON_SMLAL2 = NEON_SMLAL | NEON_Q,
1535 NEON_SMLSL = NEON3DifferentFixed | 0x0000A000,
1536 NEON_SMLSL2 = NEON_SMLSL | NEON_Q,
1537 NEON_SMULL = NEON3DifferentFixed | 0x0000C000,
1538 NEON_SMULL2 = NEON_SMULL | NEON_Q,
1539 NEON_SSUBL = NEON3DifferentFixed | 0x00002000,
1540 NEON_SSUBL2 = NEON_SSUBL | NEON_Q,
1541 NEON_SSUBW = NEON3DifferentFixed | 0x00003000,
1542 NEON_SSUBW2 = NEON_SSUBW | NEON_Q,
1543 NEON_SQDMLAL = NEON3DifferentFixed | 0x00009000,
1544 NEON_SQDMLAL2 = NEON_SQDMLAL | NEON_Q,
1545 NEON_SQDMLSL = NEON3DifferentFixed | 0x0000B000,
1546 NEON_SQDMLSL2 = NEON_SQDMLSL | NEON_Q,
1547 NEON_SQDMULL = NEON3DifferentFixed | 0x0000D000,
1548 NEON_SQDMULL2 = NEON_SQDMULL | NEON_Q,
1549 NEON_SUBHN = NEON3DifferentFixed | 0x00006000,
1550 NEON_SUBHN2 = NEON_SUBHN | NEON_Q,
1551 NEON_UABAL = NEON_SABAL | NEON3SameUBit,
1552 NEON_UABAL2 = NEON_UABAL | NEON_Q,
1553 NEON_UABDL = NEON_SABDL | NEON3SameUBit,
1554 NEON_UABDL2 = NEON_UABDL | NEON_Q,
1555 NEON_UADDL = NEON_SADDL | NEON3SameUBit,
1556 NEON_UADDL2 = NEON_UADDL | NEON_Q,
1557 NEON_UADDW = NEON_SADDW | NEON3SameUBit,
1558 NEON_UADDW2 = NEON_UADDW | NEON_Q,
1559 NEON_UMLAL = NEON_SMLAL | NEON3SameUBit,
1560 NEON_UMLAL2 = NEON_UMLAL | NEON_Q,
1561 NEON_UMLSL = NEON_SMLSL | NEON3SameUBit,
1562 NEON_UMLSL2 = NEON_UMLSL | NEON_Q,
1563 NEON_UMULL = NEON_SMULL | NEON3SameUBit,
1564 NEON_UMULL2 = NEON_UMULL | NEON_Q,
1565 NEON_USUBL = NEON_SSUBL | NEON3SameUBit,
1566 NEON_USUBL2 = NEON_USUBL | NEON_Q,
1567 NEON_USUBW = NEON_SSUBW | NEON3SameUBit,
1568 NEON_USUBW2 = NEON_USUBW | NEON_Q
1569 };
1570
1571 // NEON instructions operating across vectors.
1572 enum NEONAcrossLanesOp {
1573 NEONAcrossLanesFixed = 0x0E300800,
1574 NEONAcrossLanesFMask = 0x9F3E0C00,
1575 NEONAcrossLanesMask = 0xBF3FFC00,
1576 NEON_ADDV = NEONAcrossLanesFixed | 0x0001B000,
1577 NEON_SADDLV = NEONAcrossLanesFixed | 0x00003000,
1578 NEON_UADDLV = NEONAcrossLanesFixed | 0x20003000,
1579 NEON_SMAXV = NEONAcrossLanesFixed | 0x0000A000,
1580 NEON_SMINV = NEONAcrossLanesFixed | 0x0001A000,
1581 NEON_UMAXV = NEONAcrossLanesFixed | 0x2000A000,
1582 NEON_UMINV = NEONAcrossLanesFixed | 0x2001A000,
1583
1584 // NEON floating point across instructions.
1585 NEONAcrossLanesFPFixed = NEONAcrossLanesFixed | 0x0000C000,
1586 NEONAcrossLanesFPFMask = NEONAcrossLanesFMask | 0x0000C000,
1587 NEONAcrossLanesFPMask = NEONAcrossLanesMask | 0x00800000,
1588
1589 NEON_FMAXV = NEONAcrossLanesFPFixed | 0x2000F000,
1590 NEON_FMINV = NEONAcrossLanesFPFixed | 0x2080F000,
1591 NEON_FMAXNMV = NEONAcrossLanesFPFixed | 0x2000C000,
1592 NEON_FMINNMV = NEONAcrossLanesFPFixed | 0x2080C000
1593 };
1594
1595 // NEON instructions with indexed element operand.
1596 enum NEONByIndexedElementOp {
1597 NEONByIndexedElementFixed = 0x0F000000,
1598 NEONByIndexedElementFMask = 0x9F000400,
1599 NEONByIndexedElementMask = 0xBF00F400,
1600 NEON_MUL_byelement = NEONByIndexedElementFixed | 0x00008000,
1601 NEON_MLA_byelement = NEONByIndexedElementFixed | 0x20000000,
1602 NEON_MLS_byelement = NEONByIndexedElementFixed | 0x20004000,
1603 NEON_SMULL_byelement = NEONByIndexedElementFixed | 0x0000A000,
1604 NEON_SMLAL_byelement = NEONByIndexedElementFixed | 0x00002000,
1605 NEON_SMLSL_byelement = NEONByIndexedElementFixed | 0x00006000,
1606 NEON_UMULL_byelement = NEONByIndexedElementFixed | 0x2000A000,
1607 NEON_UMLAL_byelement = NEONByIndexedElementFixed | 0x20002000,
1608 NEON_UMLSL_byelement = NEONByIndexedElementFixed | 0x20006000,
1609 NEON_SQDMULL_byelement = NEONByIndexedElementFixed | 0x0000B000,
1610 NEON_SQDMLAL_byelement = NEONByIndexedElementFixed | 0x00003000,
1611 NEON_SQDMLSL_byelement = NEONByIndexedElementFixed | 0x00007000,
1612 NEON_SQDMULH_byelement = NEONByIndexedElementFixed | 0x0000C000,
1613 NEON_SQRDMULH_byelement = NEONByIndexedElementFixed | 0x0000D000,
1614
1615 // Floating point instructions.
1616 NEONByIndexedElementFPFixed = NEONByIndexedElementFixed | 0x00800000,
1617 NEONByIndexedElementFPMask = NEONByIndexedElementMask | 0x00800000,
1618 NEON_FMLA_byelement = NEONByIndexedElementFPFixed | 0x00001000,
1619 NEON_FMLS_byelement = NEONByIndexedElementFPFixed | 0x00005000,
1620 NEON_FMUL_byelement = NEONByIndexedElementFPFixed | 0x00009000,
1621 NEON_FMULX_byelement = NEONByIndexedElementFPFixed | 0x20009000
1622 };
1623
1624 // NEON modified immediate.
1625 enum NEONModifiedImmediateOp {
1626 NEONModifiedImmediateFixed = 0x0F000400,
1627 NEONModifiedImmediateFMask = 0x9FF80400,
1628 NEONModifiedImmediateOpBit = 0x20000000,
1629 NEONModifiedImmediate_MOVI = NEONModifiedImmediateFixed | 0x00000000,
1630 NEONModifiedImmediate_MVNI = NEONModifiedImmediateFixed | 0x20000000,
1631 NEONModifiedImmediate_ORR = NEONModifiedImmediateFixed | 0x00001000,
1632 NEONModifiedImmediate_BIC = NEONModifiedImmediateFixed | 0x20001000
1633 };
1634
1635 // NEON extract.
1636 enum NEONExtractOp {
1637 NEONExtractFixed = 0x2E000000,
1638 NEONExtractFMask = 0xBF208400,
1639 NEONExtractMask = 0xBFE08400,
1640 NEON_EXT = NEONExtractFixed | 0x00000000
1641 };
1642
1643 enum NEONLoadStoreMultiOp {
1644 NEONLoadStoreMultiL = 0x00400000,
1645 NEONLoadStoreMulti1_1v = 0x00007000,
1646 NEONLoadStoreMulti1_2v = 0x0000A000,
1647 NEONLoadStoreMulti1_3v = 0x00006000,
1648 NEONLoadStoreMulti1_4v = 0x00002000,
1649 NEONLoadStoreMulti2 = 0x00008000,
1650 NEONLoadStoreMulti3 = 0x00004000,
1651 NEONLoadStoreMulti4 = 0x00000000
1652 };
1653
1654 // NEON load/store multiple structures.
1655 enum NEONLoadStoreMultiStructOp {
1656 NEONLoadStoreMultiStructFixed = 0x0C000000,
1657 NEONLoadStoreMultiStructFMask = 0xBFBF0000,
1658 NEONLoadStoreMultiStructMask = 0xBFFFF000,
1659 NEONLoadStoreMultiStructStore = NEONLoadStoreMultiStructFixed,
1660 NEONLoadStoreMultiStructLoad =
1661 NEONLoadStoreMultiStructFixed | NEONLoadStoreMultiL,
1662 NEON_LD1_1v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_1v,
1663 NEON_LD1_2v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_2v,
1664 NEON_LD1_3v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_3v,
1665 NEON_LD1_4v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_4v,
1666 NEON_LD2 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti2,
1667 NEON_LD3 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti3,
1668 NEON_LD4 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti4,
1669 NEON_ST1_1v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_1v,
1670 NEON_ST1_2v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_2v,
1671 NEON_ST1_3v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_3v,
1672 NEON_ST1_4v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_4v,
1673 NEON_ST2 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti2,
1674 NEON_ST3 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti3,
1675 NEON_ST4 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti4
1676 };
1677
1678 // NEON load/store multiple structures with post-index addressing.
1679 enum NEONLoadStoreMultiStructPostIndexOp {
1680 NEONLoadStoreMultiStructPostIndexFixed = 0x0C800000,
1681 NEONLoadStoreMultiStructPostIndexFMask = 0xBFA00000,
1682 NEONLoadStoreMultiStructPostIndexMask = 0xBFE0F000,
1683 NEONLoadStoreMultiStructPostIndex = 0x00800000,
1684 NEON_LD1_1v_post = NEON_LD1_1v | NEONLoadStoreMultiStructPostIndex,
1685 NEON_LD1_2v_post = NEON_LD1_2v | NEONLoadStoreMultiStructPostIndex,
1686 NEON_LD1_3v_post = NEON_LD1_3v | NEONLoadStoreMultiStructPostIndex,
1687 NEON_LD1_4v_post = NEON_LD1_4v | NEONLoadStoreMultiStructPostIndex,
1688 NEON_LD2_post = NEON_LD2 | NEONLoadStoreMultiStructPostIndex,
1689 NEON_LD3_post = NEON_LD3 | NEONLoadStoreMultiStructPostIndex,
1690 NEON_LD4_post = NEON_LD4 | NEONLoadStoreMultiStructPostIndex,
1691 NEON_ST1_1v_post = NEON_ST1_1v | NEONLoadStoreMultiStructPostIndex,
1692 NEON_ST1_2v_post = NEON_ST1_2v | NEONLoadStoreMultiStructPostIndex,
1693 NEON_ST1_3v_post = NEON_ST1_3v | NEONLoadStoreMultiStructPostIndex,
1694 NEON_ST1_4v_post = NEON_ST1_4v | NEONLoadStoreMultiStructPostIndex,
1695 NEON_ST2_post = NEON_ST2 | NEONLoadStoreMultiStructPostIndex,
1696 NEON_ST3_post = NEON_ST3 | NEONLoadStoreMultiStructPostIndex,
1697 NEON_ST4_post = NEON_ST4 | NEONLoadStoreMultiStructPostIndex
1698 };
1699
1700 enum NEONLoadStoreSingleOp {
1701 NEONLoadStoreSingle1 = 0x00000000,
1702 NEONLoadStoreSingle2 = 0x00200000,
1703 NEONLoadStoreSingle3 = 0x00002000,
1704 NEONLoadStoreSingle4 = 0x00202000,
1705 NEONLoadStoreSingleL = 0x00400000,
1706 NEONLoadStoreSingle_b = 0x00000000,
1707 NEONLoadStoreSingle_h = 0x00004000,
1708 NEONLoadStoreSingle_s = 0x00008000,
1709 NEONLoadStoreSingle_d = 0x00008400,
1710 NEONLoadStoreSingleAllLanes = 0x0000C000,
1711 NEONLoadStoreSingleLenMask = 0x00202000
1712 };
1713
1714 // NEON load/store single structure.
1715 enum NEONLoadStoreSingleStructOp {
1716 NEONLoadStoreSingleStructFixed = 0x0D000000,
1717 NEONLoadStoreSingleStructFMask = 0xBF9F0000,
1718 NEONLoadStoreSingleStructMask = 0xBFFFE000,
1719 NEONLoadStoreSingleStructStore = NEONLoadStoreSingleStructFixed,
1720 NEONLoadStoreSingleStructLoad =
1721 NEONLoadStoreSingleStructFixed | NEONLoadStoreSingleL,
1722 NEONLoadStoreSingleStructLoad1 =
1723 NEONLoadStoreSingle1 | NEONLoadStoreSingleStructLoad,
1724 NEONLoadStoreSingleStructLoad2 =
1725 NEONLoadStoreSingle2 | NEONLoadStoreSingleStructLoad,
1726 NEONLoadStoreSingleStructLoad3 =
1727 NEONLoadStoreSingle3 | NEONLoadStoreSingleStructLoad,
1728 NEONLoadStoreSingleStructLoad4 =
1729 NEONLoadStoreSingle4 | NEONLoadStoreSingleStructLoad,
1730 NEONLoadStoreSingleStructStore1 =
1731 NEONLoadStoreSingle1 | NEONLoadStoreSingleStructFixed,
1732 NEONLoadStoreSingleStructStore2 =
1733 NEONLoadStoreSingle2 | NEONLoadStoreSingleStructFixed,
1734 NEONLoadStoreSingleStructStore3 =
1735 NEONLoadStoreSingle3 | NEONLoadStoreSingleStructFixed,
1736 NEONLoadStoreSingleStructStore4 =
1737 NEONLoadStoreSingle4 | NEONLoadStoreSingleStructFixed,
1738 NEON_LD1_b = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_b,
1739 NEON_LD1_h = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_h,
1740 NEON_LD1_s = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_s,
1741 NEON_LD1_d = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_d,
1742 NEON_LD1R = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingleAllLanes,
1743 NEON_ST1_b = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_b,
1744 NEON_ST1_h = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_h,
1745 NEON_ST1_s = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_s,
1746 NEON_ST1_d = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_d,
1747
1748 NEON_LD2_b = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_b,
1749 NEON_LD2_h = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_h,
1750 NEON_LD2_s = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_s,
1751 NEON_LD2_d = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_d,
1752 NEON_LD2R = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingleAllLanes,
1753 NEON_ST2_b = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_b,
1754 NEON_ST2_h = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_h,
1755 NEON_ST2_s = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_s,
1756 NEON_ST2_d = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_d,
1757
1758 NEON_LD3_b = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_b,
1759 NEON_LD3_h = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_h,
1760 NEON_LD3_s = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_s,
1761 NEON_LD3_d = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_d,
1762 NEON_LD3R = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingleAllLanes,
1763 NEON_ST3_b = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_b,
1764 NEON_ST3_h = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_h,
1765 NEON_ST3_s = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_s,
1766 NEON_ST3_d = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_d,
1767
1768 NEON_LD4_b = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_b,
1769 NEON_LD4_h = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_h,
1770 NEON_LD4_s = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_s,
1771 NEON_LD4_d = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_d,
1772 NEON_LD4R = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingleAllLanes,
1773 NEON_ST4_b = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_b,
1774 NEON_ST4_h = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_h,
1775 NEON_ST4_s = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_s,
1776 NEON_ST4_d = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_d
1777 };
1778
1779 // NEON load/store single structure with post-index addressing.
1780 enum NEONLoadStoreSingleStructPostIndexOp {
1781 NEONLoadStoreSingleStructPostIndexFixed = 0x0D800000,
1782 NEONLoadStoreSingleStructPostIndexFMask = 0xBF800000,
1783 NEONLoadStoreSingleStructPostIndexMask = 0xBFE0E000,
1784 NEONLoadStoreSingleStructPostIndex = 0x00800000,
1785 NEON_LD1_b_post = NEON_LD1_b | NEONLoadStoreSingleStructPostIndex,
1786 NEON_LD1_h_post = NEON_LD1_h | NEONLoadStoreSingleStructPostIndex,
1787 NEON_LD1_s_post = NEON_LD1_s | NEONLoadStoreSingleStructPostIndex,
1788 NEON_LD1_d_post = NEON_LD1_d | NEONLoadStoreSingleStructPostIndex,
1789 NEON_LD1R_post = NEON_LD1R | NEONLoadStoreSingleStructPostIndex,
1790 NEON_ST1_b_post = NEON_ST1_b | NEONLoadStoreSingleStructPostIndex,
1791 NEON_ST1_h_post = NEON_ST1_h | NEONLoadStoreSingleStructPostIndex,
1792 NEON_ST1_s_post = NEON_ST1_s | NEONLoadStoreSingleStructPostIndex,
1793 NEON_ST1_d_post = NEON_ST1_d | NEONLoadStoreSingleStructPostIndex,
1794
1795 NEON_LD2_b_post = NEON_LD2_b | NEONLoadStoreSingleStructPostIndex,
1796 NEON_LD2_h_post = NEON_LD2_h | NEONLoadStoreSingleStructPostIndex,
1797 NEON_LD2_s_post = NEON_LD2_s | NEONLoadStoreSingleStructPostIndex,
1798 NEON_LD2_d_post = NEON_LD2_d | NEONLoadStoreSingleStructPostIndex,
1799 NEON_LD2R_post = NEON_LD2R | NEONLoadStoreSingleStructPostIndex,
1800 NEON_ST2_b_post = NEON_ST2_b | NEONLoadStoreSingleStructPostIndex,
1801 NEON_ST2_h_post = NEON_ST2_h | NEONLoadStoreSingleStructPostIndex,
1802 NEON_ST2_s_post = NEON_ST2_s | NEONLoadStoreSingleStructPostIndex,
1803 NEON_ST2_d_post = NEON_ST2_d | NEONLoadStoreSingleStructPostIndex,
1804
1805 NEON_LD3_b_post = NEON_LD3_b | NEONLoadStoreSingleStructPostIndex,
1806 NEON_LD3_h_post = NEON_LD3_h | NEONLoadStoreSingleStructPostIndex,
1807 NEON_LD3_s_post = NEON_LD3_s | NEONLoadStoreSingleStructPostIndex,
1808 NEON_LD3_d_post = NEON_LD3_d | NEONLoadStoreSingleStructPostIndex,
1809 NEON_LD3R_post = NEON_LD3R | NEONLoadStoreSingleStructPostIndex,
1810 NEON_ST3_b_post = NEON_ST3_b | NEONLoadStoreSingleStructPostIndex,
1811 NEON_ST3_h_post = NEON_ST3_h | NEONLoadStoreSingleStructPostIndex,
1812 NEON_ST3_s_post = NEON_ST3_s | NEONLoadStoreSingleStructPostIndex,
1813 NEON_ST3_d_post = NEON_ST3_d | NEONLoadStoreSingleStructPostIndex,
1814
1815 NEON_LD4_b_post = NEON_LD4_b | NEONLoadStoreSingleStructPostIndex,
1816 NEON_LD4_h_post = NEON_LD4_h | NEONLoadStoreSingleStructPostIndex,
1817 NEON_LD4_s_post = NEON_LD4_s | NEONLoadStoreSingleStructPostIndex,
1818 NEON_LD4_d_post = NEON_LD4_d | NEONLoadStoreSingleStructPostIndex,
1819 NEON_LD4R_post = NEON_LD4R | NEONLoadStoreSingleStructPostIndex,
1820 NEON_ST4_b_post = NEON_ST4_b | NEONLoadStoreSingleStructPostIndex,
1821 NEON_ST4_h_post = NEON_ST4_h | NEONLoadStoreSingleStructPostIndex,
1822 NEON_ST4_s_post = NEON_ST4_s | NEONLoadStoreSingleStructPostIndex,
1823 NEON_ST4_d_post = NEON_ST4_d | NEONLoadStoreSingleStructPostIndex
1824 };
1825
1826 // NEON register copy.
1827 enum NEONCopyOp {
1828 NEONCopyFixed = 0x0E000400,
1829 NEONCopyFMask = 0x9FE08400,
1830 NEONCopyMask = 0x3FE08400,
1831 NEONCopyInsElementMask = NEONCopyMask | 0x40000000,
1832 NEONCopyInsGeneralMask = NEONCopyMask | 0x40007800,
1833 NEONCopyDupElementMask = NEONCopyMask | 0x20007800,
1834 NEONCopyDupGeneralMask = NEONCopyDupElementMask,
1835 NEONCopyUmovMask = NEONCopyMask | 0x20007800,
1836 NEONCopySmovMask = NEONCopyMask | 0x20007800,
1837 NEON_INS_ELEMENT = NEONCopyFixed | 0x60000000,
1838 NEON_INS_GENERAL = NEONCopyFixed | 0x40001800,
1839 NEON_DUP_ELEMENT = NEONCopyFixed | 0x00000000,
1840 NEON_DUP_GENERAL = NEONCopyFixed | 0x00000800,
1841 NEON_SMOV = NEONCopyFixed | 0x00002800,
1842 NEON_UMOV = NEONCopyFixed | 0x00003800
1843 };
1844
1845 // NEON scalar instructions with indexed element operand.
1846 enum NEONScalarByIndexedElementOp {
1847 NEONScalarByIndexedElementFixed = 0x5F000000,
1848 NEONScalarByIndexedElementFMask = 0xDF000400,
1849 NEONScalarByIndexedElementMask = 0xFF00F400,
1850 NEON_SQDMLAL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMLAL_byelement,
1851 NEON_SQDMLSL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMLSL_byelement,
1852 NEON_SQDMULL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMULL_byelement,
1853 NEON_SQDMULH_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMULH_byelement,
1854 NEON_SQRDMULH_byelement_scalar =
1855 NEON_Q | NEONScalar | NEON_SQRDMULH_byelement,
1856
1857 // Floating point instructions.
1858 NEONScalarByIndexedElementFPFixed =
1859 NEONScalarByIndexedElementFixed | 0x00800000,
1860 NEONScalarByIndexedElementFPMask =
1861 NEONScalarByIndexedElementMask | 0x00800000,
1862 NEON_FMLA_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLA_byelement,
1863 NEON_FMLS_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLS_byelement,
1864 NEON_FMUL_byelement_scalar = NEON_Q | NEONScalar | NEON_FMUL_byelement,
1865 NEON_FMULX_byelement_scalar = NEON_Q | NEONScalar | NEON_FMULX_byelement
1866 };
1867
1868 // NEON shift immediate.
1869 enum NEONShiftImmediateOp {
1870 NEONShiftImmediateFixed = 0x0F000400,
1871 NEONShiftImmediateFMask = 0x9F800400,
1872 NEONShiftImmediateMask = 0xBF80FC00,
1873 NEONShiftImmediateUBit = 0x20000000,
1874 NEON_SHL = NEONShiftImmediateFixed | 0x00005000,
1875 NEON_SSHLL = NEONShiftImmediateFixed | 0x0000A000,
1876 NEON_USHLL = NEONShiftImmediateFixed | 0x2000A000,
1877 NEON_SLI = NEONShiftImmediateFixed | 0x20005000,
1878 NEON_SRI = NEONShiftImmediateFixed | 0x20004000,
1879 NEON_SHRN = NEONShiftImmediateFixed | 0x00008000,
1880 NEON_RSHRN = NEONShiftImmediateFixed | 0x00008800,
1881 NEON_UQSHRN = NEONShiftImmediateFixed | 0x20009000,
1882 NEON_UQRSHRN = NEONShiftImmediateFixed | 0x20009800,
1883 NEON_SQSHRN = NEONShiftImmediateFixed | 0x00009000,
1884 NEON_SQRSHRN = NEONShiftImmediateFixed | 0x00009800,
1885 NEON_SQSHRUN = NEONShiftImmediateFixed | 0x20008000,
1886 NEON_SQRSHRUN = NEONShiftImmediateFixed | 0x20008800,
1887 NEON_SSHR = NEONShiftImmediateFixed | 0x00000000,
1888 NEON_SRSHR = NEONShiftImmediateFixed | 0x00002000,
1889 NEON_USHR = NEONShiftImmediateFixed | 0x20000000,
1890 NEON_URSHR = NEONShiftImmediateFixed | 0x20002000,
1891 NEON_SSRA = NEONShiftImmediateFixed | 0x00001000,
1892 NEON_SRSRA = NEONShiftImmediateFixed | 0x00003000,
1893 NEON_USRA = NEONShiftImmediateFixed | 0x20001000,
1894 NEON_URSRA = NEONShiftImmediateFixed | 0x20003000,
1895 NEON_SQSHLU = NEONShiftImmediateFixed | 0x20006000,
1896 NEON_SCVTF_imm = NEONShiftImmediateFixed | 0x0000E000,
1897 NEON_UCVTF_imm = NEONShiftImmediateFixed | 0x2000E000,
1898 NEON_FCVTZS_imm = NEONShiftImmediateFixed | 0x0000F800,
1899 NEON_FCVTZU_imm = NEONShiftImmediateFixed | 0x2000F800,
1900 NEON_SQSHL_imm = NEONShiftImmediateFixed | 0x00007000,
1901 NEON_UQSHL_imm = NEONShiftImmediateFixed | 0x20007000
1902 };
1903
1904 // NEON scalar register copy.
1905 enum NEONScalarCopyOp {
1906 NEONScalarCopyFixed = 0x5E000400,
1907 NEONScalarCopyFMask = 0xDFE08400,
1908 NEONScalarCopyMask = 0xFFE0FC00,
1909 NEON_DUP_ELEMENT_scalar = NEON_Q | NEONScalar | NEON_DUP_ELEMENT
1910 };
1911
1912 // NEON scalar pairwise instructions.
1913 enum NEONScalarPairwiseOp {
1914 NEONScalarPairwiseFixed = 0x5E300800,
1915 NEONScalarPairwiseFMask = 0xDF3E0C00,
1916 NEONScalarPairwiseMask = 0xFFB1F800,
1917 NEON_ADDP_scalar = NEONScalarPairwiseFixed | 0x0081B000,
1918 NEON_FMAXNMP_scalar = NEONScalarPairwiseFixed | 0x2000C000,
1919 NEON_FMINNMP_scalar = NEONScalarPairwiseFixed | 0x2080C000,
1920 NEON_FADDP_scalar = NEONScalarPairwiseFixed | 0x2000D000,
1921 NEON_FMAXP_scalar = NEONScalarPairwiseFixed | 0x2000F000,
1922 NEON_FMINP_scalar = NEONScalarPairwiseFixed | 0x2080F000
1923 };
1924
1925 // NEON scalar shift immediate.
1926 enum NEONScalarShiftImmediateOp {
1927 NEONScalarShiftImmediateFixed = 0x5F000400,
1928 NEONScalarShiftImmediateFMask = 0xDF800400,
1929 NEONScalarShiftImmediateMask = 0xFF80FC00,
1930 NEON_SHL_scalar = NEON_Q | NEONScalar | NEON_SHL,
1931 NEON_SLI_scalar = NEON_Q | NEONScalar | NEON_SLI,
1932 NEON_SRI_scalar = NEON_Q | NEONScalar | NEON_SRI,
1933 NEON_SSHR_scalar = NEON_Q | NEONScalar | NEON_SSHR,
1934 NEON_USHR_scalar = NEON_Q | NEONScalar | NEON_USHR,
1935 NEON_SRSHR_scalar = NEON_Q | NEONScalar | NEON_SRSHR,
1936 NEON_URSHR_scalar = NEON_Q | NEONScalar | NEON_URSHR,
1937 NEON_SSRA_scalar = NEON_Q | NEONScalar | NEON_SSRA,
1938 NEON_USRA_scalar = NEON_Q | NEONScalar | NEON_USRA,
1939 NEON_SRSRA_scalar = NEON_Q | NEONScalar | NEON_SRSRA,
1940 NEON_URSRA_scalar = NEON_Q | NEONScalar | NEON_URSRA,
1941 NEON_UQSHRN_scalar = NEON_Q | NEONScalar | NEON_UQSHRN,
1942 NEON_UQRSHRN_scalar = NEON_Q | NEONScalar | NEON_UQRSHRN,
1943 NEON_SQSHRN_scalar = NEON_Q | NEONScalar | NEON_SQSHRN,
1944 NEON_SQRSHRN_scalar = NEON_Q | NEONScalar | NEON_SQRSHRN,
1945 NEON_SQSHRUN_scalar = NEON_Q | NEONScalar | NEON_SQSHRUN,
1946 NEON_SQRSHRUN_scalar = NEON_Q | NEONScalar | NEON_SQRSHRUN,
1947 NEON_SQSHLU_scalar = NEON_Q | NEONScalar | NEON_SQSHLU,
1948 NEON_SQSHL_imm_scalar = NEON_Q | NEONScalar | NEON_SQSHL_imm,
1949 NEON_UQSHL_imm_scalar = NEON_Q | NEONScalar | NEON_UQSHL_imm,
1950 NEON_SCVTF_imm_scalar = NEON_Q | NEONScalar | NEON_SCVTF_imm,
1951 NEON_UCVTF_imm_scalar = NEON_Q | NEONScalar | NEON_UCVTF_imm,
1952 NEON_FCVTZS_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZS_imm,
1953 NEON_FCVTZU_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZU_imm
1954 };
1955
1956 // NEON table.
1957 enum NEONTableOp {
1958 NEONTableFixed = 0x0E000000,
1959 NEONTableFMask = 0xBF208C00,
1960 NEONTableExt = 0x00001000,
1961 NEONTableMask = 0xBF20FC00,
1962 NEON_TBL_1v = NEONTableFixed | 0x00000000,
1963 NEON_TBL_2v = NEONTableFixed | 0x00002000,
1964 NEON_TBL_3v = NEONTableFixed | 0x00004000,
1965 NEON_TBL_4v = NEONTableFixed | 0x00006000,
1966 NEON_TBX_1v = NEON_TBL_1v | NEONTableExt,
1967 NEON_TBX_2v = NEON_TBL_2v | NEONTableExt,
1968 NEON_TBX_3v = NEON_TBL_3v | NEONTableExt,
1969 NEON_TBX_4v = NEON_TBL_4v | NEONTableExt
1970 };
1971
1972 // NEON perm.
1973 enum NEONPermOp {
1974 NEONPermFixed = 0x0E000800,
1975 NEONPermFMask = 0xBF208C00,
1976 NEONPermMask = 0x3F20FC00,
1977 NEON_UZP1 = NEONPermFixed | 0x00001000,
1978 NEON_TRN1 = NEONPermFixed | 0x00002000,
1979 NEON_ZIP1 = NEONPermFixed | 0x00003000,
1980 NEON_UZP2 = NEONPermFixed | 0x00005000,
1981 NEON_TRN2 = NEONPermFixed | 0x00006000,
1982 NEON_ZIP2 = NEONPermFixed | 0x00007000
1983 };
1984
1985 // NEON scalar instructions with two register operands.
1986 enum NEONScalar2RegMiscOp {
1987 NEONScalar2RegMiscFixed = 0x5E200800,
1988 NEONScalar2RegMiscFMask = 0xDF3E0C00,
1989 NEONScalar2RegMiscMask = NEON_Q | NEONScalar | NEON2RegMiscMask,
1990 NEON_CMGT_zero_scalar = NEON_Q | NEONScalar | NEON_CMGT_zero,
1991 NEON_CMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_CMEQ_zero,
1992 NEON_CMLT_zero_scalar = NEON_Q | NEONScalar | NEON_CMLT_zero,
1993 NEON_CMGE_zero_scalar = NEON_Q | NEONScalar | NEON_CMGE_zero,
1994 NEON_CMLE_zero_scalar = NEON_Q | NEONScalar | NEON_CMLE_zero,
1995 NEON_ABS_scalar = NEON_Q | NEONScalar | NEON_ABS,
1996 NEON_SQABS_scalar = NEON_Q | NEONScalar | NEON_SQABS,
1997 NEON_NEG_scalar = NEON_Q | NEONScalar | NEON_NEG,
1998 NEON_SQNEG_scalar = NEON_Q | NEONScalar | NEON_SQNEG,
1999 NEON_SQXTN_scalar = NEON_Q | NEONScalar | NEON_SQXTN,
2000 NEON_UQXTN_scalar = NEON_Q | NEONScalar | NEON_UQXTN,
2001 NEON_SQXTUN_scalar = NEON_Q | NEONScalar | NEON_SQXTUN,
2002 NEON_SUQADD_scalar = NEON_Q | NEONScalar | NEON_SUQADD,
2003 NEON_USQADD_scalar = NEON_Q | NEONScalar | NEON_USQADD,
2004
2005 NEONScalar2RegMiscOpcode = NEON2RegMiscOpcode,
2006 NEON_NEG_scalar_opcode = NEON_NEG_scalar & NEONScalar2RegMiscOpcode,
2007
2008 NEONScalar2RegMiscFPMask = NEONScalar2RegMiscMask | 0x00800000,
2009 NEON_FRSQRTE_scalar = NEON_Q | NEONScalar | NEON_FRSQRTE,
2010 NEON_FRECPE_scalar = NEON_Q | NEONScalar | NEON_FRECPE,
2011 NEON_SCVTF_scalar = NEON_Q | NEONScalar | NEON_SCVTF,
2012 NEON_UCVTF_scalar = NEON_Q | NEONScalar | NEON_UCVTF,
2013 NEON_FCMGT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGT_zero,
2014 NEON_FCMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_FCMEQ_zero,
2015 NEON_FCMLT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLT_zero,
2016 NEON_FCMGE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGE_zero,
2017 NEON_FCMLE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLE_zero,
2018 NEON_FRECPX_scalar = NEONScalar2RegMiscFixed | 0x0081F000,
2019 NEON_FCVTNS_scalar = NEON_Q | NEONScalar | NEON_FCVTNS,
2020 NEON_FCVTNU_scalar = NEON_Q | NEONScalar | NEON_FCVTNU,
2021 NEON_FCVTPS_scalar = NEON_Q | NEONScalar | NEON_FCVTPS,
2022 NEON_FCVTPU_scalar = NEON_Q | NEONScalar | NEON_FCVTPU,
2023 NEON_FCVTMS_scalar = NEON_Q | NEONScalar | NEON_FCVTMS,
2024 NEON_FCVTMU_scalar = NEON_Q | NEONScalar | NEON_FCVTMU,
2025 NEON_FCVTZS_scalar = NEON_Q | NEONScalar | NEON_FCVTZS,
2026 NEON_FCVTZU_scalar = NEON_Q | NEONScalar | NEON_FCVTZU,
2027 NEON_FCVTAS_scalar = NEON_Q | NEONScalar | NEON_FCVTAS,
2028 NEON_FCVTAU_scalar = NEON_Q | NEONScalar | NEON_FCVTAU,
2029 NEON_FCVTXN_scalar = NEON_Q | NEONScalar | NEON_FCVTXN
2030 };
2031
2032 // NEON scalar instructions with three same-type operands.
2033 enum NEONScalar3SameOp {
2034 NEONScalar3SameFixed = 0x5E200400,
2035 NEONScalar3SameFMask = 0xDF200400,
2036 NEONScalar3SameMask = 0xFF20FC00,
2037 NEON_ADD_scalar = NEON_Q | NEONScalar | NEON_ADD,
2038 NEON_CMEQ_scalar = NEON_Q | NEONScalar | NEON_CMEQ,
2039 NEON_CMGE_scalar = NEON_Q | NEONScalar | NEON_CMGE,
2040 NEON_CMGT_scalar = NEON_Q | NEONScalar | NEON_CMGT,
2041 NEON_CMHI_scalar = NEON_Q | NEONScalar | NEON_CMHI,
2042 NEON_CMHS_scalar = NEON_Q | NEONScalar | NEON_CMHS,
2043 NEON_CMTST_scalar = NEON_Q | NEONScalar | NEON_CMTST,
2044 NEON_SUB_scalar = NEON_Q | NEONScalar | NEON_SUB,
2045 NEON_UQADD_scalar = NEON_Q | NEONScalar | NEON_UQADD,
2046 NEON_SQADD_scalar = NEON_Q | NEONScalar | NEON_SQADD,
2047 NEON_UQSUB_scalar = NEON_Q | NEONScalar | NEON_UQSUB,
2048 NEON_SQSUB_scalar = NEON_Q | NEONScalar | NEON_SQSUB,
2049 NEON_USHL_scalar = NEON_Q | NEONScalar | NEON_USHL,
2050 NEON_SSHL_scalar = NEON_Q | NEONScalar | NEON_SSHL,
2051 NEON_UQSHL_scalar = NEON_Q | NEONScalar | NEON_UQSHL,
2052 NEON_SQSHL_scalar = NEON_Q | NEONScalar | NEON_SQSHL,
2053 NEON_URSHL_scalar = NEON_Q | NEONScalar | NEON_URSHL,
2054 NEON_SRSHL_scalar = NEON_Q | NEONScalar | NEON_SRSHL,
2055 NEON_UQRSHL_scalar = NEON_Q | NEONScalar | NEON_UQRSHL,
2056 NEON_SQRSHL_scalar = NEON_Q | NEONScalar | NEON_SQRSHL,
2057 NEON_SQDMULH_scalar = NEON_Q | NEONScalar | NEON_SQDMULH,
2058 NEON_SQRDMULH_scalar = NEON_Q | NEONScalar | NEON_SQRDMULH,
2059
2060 // NEON floating point scalar instructions with three same-type operands.
2061 NEONScalar3SameFPFixed = NEONScalar3SameFixed | 0x0000C000,
2062 NEONScalar3SameFPFMask = NEONScalar3SameFMask | 0x0000C000,
2063 NEONScalar3SameFPMask = NEONScalar3SameMask | 0x00800000,
2064 NEON_FACGE_scalar = NEON_Q | NEONScalar | NEON_FACGE,
2065 NEON_FACGT_scalar = NEON_Q | NEONScalar | NEON_FACGT,
2066 NEON_FCMEQ_scalar = NEON_Q | NEONScalar | NEON_FCMEQ,
2067 NEON_FCMGE_scalar = NEON_Q | NEONScalar | NEON_FCMGE,
2068 NEON_FCMGT_scalar = NEON_Q | NEONScalar | NEON_FCMGT,
2069 NEON_FMULX_scalar = NEON_Q | NEONScalar | NEON_FMULX,
2070 NEON_FRECPS_scalar = NEON_Q | NEONScalar | NEON_FRECPS,
2071 NEON_FRSQRTS_scalar = NEON_Q | NEONScalar | NEON_FRSQRTS,
2072 NEON_FABD_scalar = NEON_Q | NEONScalar | NEON_FABD
2073 };
2074
2075 // NEON scalar instructions with three different-type operands.
2076 enum NEONScalar3DiffOp {
2077 NEONScalar3DiffFixed = 0x5E200000,
2078 NEONScalar3DiffFMask = 0xDF200C00,
2079 NEONScalar3DiffMask = NEON_Q | NEONScalar | NEON3DifferentMask,
2080 NEON_SQDMLAL_scalar = NEON_Q | NEONScalar | NEON_SQDMLAL,
2081 NEON_SQDMLSL_scalar = NEON_Q | NEONScalar | NEON_SQDMLSL,
2082 NEON_SQDMULL_scalar = NEON_Q | NEONScalar | NEON_SQDMULL
2083 };
2084
1244 // Unimplemented and unallocated instructions. These are defined to make fixed 2085 // Unimplemented and unallocated instructions. These are defined to make fixed
1245 // bit assertion easier. 2086 // bit assertion easier.
1246 enum UnimplementedOp { 2087 enum UnimplementedOp {
1247 UnimplementedFixed = 0x00000000, 2088 UnimplementedFixed = 0x00000000,
1248 UnimplementedFMask = 0x00000000 2089 UnimplementedFMask = 0x00000000
1249 }; 2090 };
1250 2091
1251 enum UnallocatedOp { 2092 enum UnallocatedOp {
1252 UnallocatedFixed = 0x00000000, 2093 UnallocatedFixed = 0x00000000,
1253 UnallocatedFMask = 0x00000000 2094 UnallocatedFMask = 0x00000000
1254 }; 2095 };
1255 2096
1256 } // namespace internal 2097 } // namespace internal
1257 } // namespace v8 2098 } // namespace v8
1258 2099
1259 #endif // V8_ARM64_CONSTANTS_ARM64_H_ 2100 #endif // V8_ARM64_CONSTANTS_ARM64_H_
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