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Issue 2619943003: [SubZero] Fix code generation issues occurred in Cross-test and PNaCL smoke-tests (Closed)
Patch Set: Addressed review comments Created 3 years, 11 months ago
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1 ; This file tests support for the select instruction with vector valued inputs. 1 ; This file tests support for the select instruction with vector valued inputs.
2 2
3 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \ 3 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
4 ; RUN: | FileCheck %s 4 ; RUN: | FileCheck %s
5 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \ 5 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
6 ; RUN: | FileCheck %s 6 ; RUN: | FileCheck %s
7 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 -mattr=sse4.1 \ 7 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 -mattr=sse4.1 \
8 ; RUN: | FileCheck --check-prefix=SSE41 %s 8 ; RUN: | FileCheck --check-prefix=SSE41 %s
9 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -mattr=sse4.1 \ 9 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -mattr=sse4.1 \
10 ; RUN: | FileCheck --check-prefix=SSE41 %s 10 ; RUN: | FileCheck --check-prefix=SSE41 %s
(...skipping 11 matching lines...) Expand all
22 ret <16 x i8> %res 22 ret <16 x i8> %res
23 ; CHECK-LABEL: test_select_v16i8 23 ; CHECK-LABEL: test_select_v16i8
24 ; CHECK: pand 24 ; CHECK: pand
25 ; CHECK: pandn 25 ; CHECK: pandn
26 ; CHECK: por 26 ; CHECK: por
27 27
28 ; SSE41-LABEL: test_select_v16i8 28 ; SSE41-LABEL: test_select_v16i8
29 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} 29 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
30 30
31 ; MIPS32-LABEL: test_select_v16i8 31 ; MIPS32-LABEL: test_select_v16i8
32 ; MIPS32: addiu [[T0:.*]],sp,-20 32 ; MIPS32: addiu [[T0:.*]],sp,-32
33 ; MIPS32: sw [[T1:.*]], 33 ; MIPS32: sw [[T1:.*]],
34 ; MIPS32: sw [[T2:.*]], 34 ; MIPS32: sw [[T2:.*]],
35 ; MIPS32: sw [[T3:.*]], 35 ; MIPS32: sw [[T3:.*]],
36 ; MIPS32: sw [[T4:.*]], 36 ; MIPS32: sw [[T4:.*]],
37 ; MIPS32: sw [[T5:.*]], 37 ; MIPS32: sw [[T5:.*]],
38 ; MIPS32: lw [[T6:.*]], 38 ; MIPS32: lw [[T6:.*]],
39 ; MIPS32: lw [[T7:.*]], 39 ; MIPS32: lw [[T7:.*]],
40 ; MIPS32: lw [[T8:.*]], 40 ; MIPS32: lw [[T8:.*]],
41 ; MIPS32: lw [[T9:.*]], 41 ; MIPS32: lw [[T9:.*]],
42 ; MIPS32: lw [[T10:.*]], 42 ; MIPS32: lw [[T10:.*]],
(...skipping 48 matching lines...) Expand 10 before | Expand all | Expand 10 after
91 ; MIPS32: sll [[T1]],[[T1]],0x10 91 ; MIPS32: sll [[T1]],[[T1]],0x10
92 ; MIPS32: lui [[T14]],0xff00 92 ; MIPS32: lui [[T14]],0xff00
93 ; MIPS32: ori [[T14]],[[T14]],0xffff 93 ; MIPS32: ori [[T14]],[[T14]],0xffff
94 ; MIPS32: and [[T2]],[[T2]],[[T14]] 94 ; MIPS32: and [[T2]],[[T2]],[[T14]]
95 ; MIPS32: or [[T1]],[[T1]],[[T2]] 95 ; MIPS32: or [[T1]],[[T1]],[[T2]]
96 ; MIPS32: srl [[T16:.*]],a0,0x18 96 ; MIPS32: srl [[T16:.*]],a0,0x18
97 ; MIPS32: andi [[T16]],[[T16]],0x1 97 ; MIPS32: andi [[T16]],[[T16]],0x1
98 ; MIPS32: srl [[T6]],[[T6]],0x18 98 ; MIPS32: srl [[T6]],[[T6]],0x18
99 ; MIPS32: srl [[T10]],[[T10]],0x18 99 ; MIPS32: srl [[T10]],[[T10]],0x18
100 ; MIPS32: movn [[T10]],[[T6]],[[T16]] 100 ; MIPS32: movn [[T10]],[[T6]],[[T16]]
101 ; MIPS32: srl [[T10]],[[T10]],0x18 101 ; MIPS32: sll [[T10]],[[T10]],0x18
102 ; MIPS32: sll [[T1]],[[T1]],0x8 102 ; MIPS32: sll [[T1]],[[T1]],0x8
103 ; MIPS32: srl [[T1]],[[T1]],0x8 103 ; MIPS32: srl [[T1]],[[T1]],0x8
104 ; MIPS32: or [[T10]],[[T10]],[[T1]] 104 ; MIPS32: or [[T10]],[[T10]],[[T1]]
105 ; MIPS32: move [[T6]],a1 105 ; MIPS32: move [[T6]],a1
106 ; MIPS32: andi [[T6]],[[T6]],0xff 106 ; MIPS32: andi [[T6]],[[T6]],0xff
107 ; MIPS32: andi [[T6]],[[T6]],0x1 107 ; MIPS32: andi [[T6]],[[T6]],0x1
108 ; MIPS32: move [[T16]],[[T7]] 108 ; MIPS32: move [[T16]],[[T7]]
109 ; MIPS32: andi [[T16]],[[T16]],0xff 109 ; MIPS32: andi [[T16]],[[T16]],0xff
110 ; MIPS32: move [[T14]],[[T11]] 110 ; MIPS32: move [[T14]],[[T11]]
111 ; MIPS32: andi [[T14]],[[T14]],0xff 111 ; MIPS32: andi [[T14]],[[T14]],0xff
(...skipping 34 matching lines...) Expand 10 before | Expand all | Expand 10 after
146 ; MIPS32: sll [[T14]],[[T14]],0x10 146 ; MIPS32: sll [[T14]],[[T14]],0x10
147 ; MIPS32: lui [[T6]],0xff00 147 ; MIPS32: lui [[T6]],0xff00
148 ; MIPS32: ori [[T6]],[[T6]],0xffff 148 ; MIPS32: ori [[T6]],[[T6]],0xffff
149 ; MIPS32: and [[T15]],[[T15]],[[T6]] 149 ; MIPS32: and [[T15]],[[T15]],[[T6]]
150 ; MIPS32: or [[T14]],[[T14]],[[T15]] 150 ; MIPS32: or [[T14]],[[T14]],[[T15]]
151 ; MIPS32: srl [[T17:.*]],a1,0x18 151 ; MIPS32: srl [[T17:.*]],a1,0x18
152 ; MIPS32: andi [[T17]],[[T17]],0x1 152 ; MIPS32: andi [[T17]],[[T17]],0x1
153 ; MIPS32: srl [[T7]],[[T7]],0x18 153 ; MIPS32: srl [[T7]],[[T7]],0x18
154 ; MIPS32: srl [[T11]],[[T11]],0x18 154 ; MIPS32: srl [[T11]],[[T11]],0x18
155 ; MIPS32: movn [[T11]],[[T7]],[[T17]] 155 ; MIPS32: movn [[T11]],[[T7]],[[T17]]
156 ; MIPS32: srl [[T11]],[[T11]],0x18 156 ; MIPS32: sll [[T11]],[[T11]],0x18
157 ; MIPS32: sll [[T14]],[[T14]],0x8 157 ; MIPS32: sll [[T14]],[[T14]],0x8
158 ; MIPS32: srl [[T14]],[[T14]],0x8 158 ; MIPS32: srl [[T14]],[[T14]],0x8
159 ; MIPS32: or [[T11]],[[T11]],[[T14]] 159 ; MIPS32: or [[T11]],[[T11]],[[T14]]
160 ; MIPS32: move [[T6]],a2 160 ; MIPS32: move [[T6]],a2
161 ; MIPS32: andi [[T6]],[[T6]],0xff 161 ; MIPS32: andi [[T6]],[[T6]],0xff
162 ; MIPS32: andi [[T6]],[[T6]],0x1 162 ; MIPS32: andi [[T6]],[[T6]],0x1
163 ; MIPS32: move [[T7]],[[T8]] 163 ; MIPS32: move [[T7]],[[T8]]
164 ; MIPS32: andi [[T7]],[[T7]],0xff 164 ; MIPS32: andi [[T7]],[[T7]],0xff
165 ; MIPS32: move [[T16]],[[T12]] 165 ; MIPS32: move [[T16]],[[T12]]
166 ; MIPS32: andi [[T16]],[[T16]],0xff 166 ; MIPS32: andi [[T16]],[[T16]],0xff
(...skipping 34 matching lines...) Expand 10 before | Expand all | Expand 10 after
201 ; MIPS32: sll [[T16]],[[T16]],0x10 201 ; MIPS32: sll [[T16]],[[T16]],0x10
202 ; MIPS32: lui [[T6]],0xff00 202 ; MIPS32: lui [[T6]],0xff00
203 ; MIPS32: ori [[T6]],[[T6]],0xffff 203 ; MIPS32: ori [[T6]],[[T6]],0xffff
204 ; MIPS32: and [[T17]],[[T17]],[[T6]] 204 ; MIPS32: and [[T17]],[[T17]],[[T6]]
205 ; MIPS32: or [[T16]],[[T16]],[[T17]] 205 ; MIPS32: or [[T16]],[[T16]],[[T17]]
206 ; MIPS32: srl [[T18:.*]],a2,0x18 206 ; MIPS32: srl [[T18:.*]],a2,0x18
207 ; MIPS32: andi [[T18]],[[T18]],0x1 207 ; MIPS32: andi [[T18]],[[T18]],0x1
208 ; MIPS32: srl [[T8]],[[T8]],0x18 208 ; MIPS32: srl [[T8]],[[T8]],0x18
209 ; MIPS32: srl [[T12]],[[T12]],0x18 209 ; MIPS32: srl [[T12]],[[T12]],0x18
210 ; MIPS32: movn [[T12]],[[T8]],[[T18]] 210 ; MIPS32: movn [[T12]],[[T8]],[[T18]]
211 ; MIPS32: srl [[T12]],[[T12]],0x18 211 ; MIPS32: sll [[T12]],[[T12]],0x18
212 ; MIPS32: sll [[T16]],[[T16]],0x8 212 ; MIPS32: sll [[T16]],[[T16]],0x8
213 ; MIPS32: srl [[T16]],[[T16]],0x8 213 ; MIPS32: srl [[T16]],[[T16]],0x8
214 ; MIPS32: or [[T12]],[[T12]],[[T16]] 214 ; MIPS32: or [[T12]],[[T12]],[[T16]]
215 ; MIPS32: move [[T6]],a3 215 ; MIPS32: move [[T6]],a3
216 ; MIPS32: andi [[T6]],[[T6]],0xff 216 ; MIPS32: andi [[T6]],[[T6]],0xff
217 ; MIPS32: andi [[T6]],[[T6]],0x1 217 ; MIPS32: andi [[T6]],[[T6]],0x1
218 ; MIPS32: move [[T7]],[[T9]] 218 ; MIPS32: move [[T7]],[[T9]]
219 ; MIPS32: andi [[T7]],[[T7]],0xff 219 ; MIPS32: andi [[T7]],[[T7]],0xff
220 ; MIPS32: move [[T16]],[[T13]] 220 ; MIPS32: move [[T16]],[[T13]]
221 ; MIPS32: andi [[T16]],[[T16]],0xff 221 ; MIPS32: andi [[T16]],[[T16]],0xff
(...skipping 34 matching lines...) Expand 10 before | Expand all | Expand 10 after
256 ; MIPS32: sll [[T16]],[[T16]],0x10 256 ; MIPS32: sll [[T16]],[[T16]],0x10
257 ; MIPS32: lui [[T6]],0xff00 257 ; MIPS32: lui [[T6]],0xff00
258 ; MIPS32: ori [[T6]],[[T6]],0xffff 258 ; MIPS32: ori [[T6]],[[T6]],0xffff
259 ; MIPS32: and [[T17]],[[T17]],[[T6]] 259 ; MIPS32: and [[T17]],[[T17]],[[T6]]
260 ; MIPS32: or [[T16]],[[T16]],[[T17]] 260 ; MIPS32: or [[T16]],[[T16]],[[T17]]
261 ; MIPS32: srl [[T19:.*]],a3,0x18 261 ; MIPS32: srl [[T19:.*]],a3,0x18
262 ; MIPS32: andi [[T19]],[[T19]],0x1 262 ; MIPS32: andi [[T19]],[[T19]],0x1
263 ; MIPS32: srl [[T9]],[[T9]],0x18 263 ; MIPS32: srl [[T9]],[[T9]],0x18
264 ; MIPS32: srl [[T13]],[[T13]],0x18 264 ; MIPS32: srl [[T13]],[[T13]],0x18
265 ; MIPS32: movn [[T13]],[[T9]],[[T19]] 265 ; MIPS32: movn [[T13]],[[T9]],[[T19]]
266 ; MIPS32: srl [[T13]],[[T13]],0x18 266 ; MIPS32: sll [[T13]],[[T13]],0x18
267 ; MIPS32: sll [[T16]],[[T16]],0x8 267 ; MIPS32: sll [[T16]],[[T16]],0x8
268 ; MIPS32: srl [[T16]],[[T16]],0x8 268 ; MIPS32: srl [[T16]],[[T16]],0x8
269 ; MIPS32: or [[T13]],[[T13]],[[T16]] 269 ; MIPS32: or [[T13]],[[T13]],[[T16]]
270 ; MIPS32: move v0,[[T10]] 270 ; MIPS32: move v0,[[T10]]
271 ; MIPS32: move v1,[[T11]] 271 ; MIPS32: move v1,[[T11]]
272 ; MIPS32: move a0,[[T12]] 272 ; MIPS32: move a0,[[T12]]
273 ; MIPS32: move a1,[[T13]] 273 ; MIPS32: move a1,[[T13]]
274 ; MIPS32: lw [[T5]], 274 ; MIPS32: lw [[T5]],
275 ; MIPS32: lw [[T4]], 275 ; MIPS32: lw [[T4]],
276 ; MIPS32: lw [[T3]], 276 ; MIPS32: lw [[T3]],
277 ; MIPS32: lw [[T2]], 277 ; MIPS32: lw [[T2]],
278 ; MIPS32: lw [[T1]], 278 ; MIPS32: lw [[T1]],
279 ; MIPS32: addiu [[T0]],sp,20 279 ; MIPS32: addiu [[T0]],sp,32
280 } 280 }
281 281
282 define internal <16 x i1> @test_select_v16i1(<16 x i1> %cond, <16 x i1> %arg1, 282 define internal <16 x i1> @test_select_v16i1(<16 x i1> %cond, <16 x i1> %arg1,
283 <16 x i1> %arg2) { 283 <16 x i1> %arg2) {
284 entry: 284 entry:
285 %res = select <16 x i1> %cond, <16 x i1> %arg1, <16 x i1> %arg2 285 %res = select <16 x i1> %cond, <16 x i1> %arg1, <16 x i1> %arg2
286 ret <16 x i1> %res 286 ret <16 x i1> %res
287 ; CHECK-LABEL: test_select_v16i1 287 ; CHECK-LABEL: test_select_v16i1
288 ; CHECK: pand 288 ; CHECK: pand
289 ; CHECK: pandn 289 ; CHECK: pandn
290 ; CHECK: por 290 ; CHECK: por
291 291
292 ; SSE41-LABEL: test_select_v16i1 292 ; SSE41-LABEL: test_select_v16i1
293 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} 293 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
294 294
295 ; MIPS32-LABEL: test_select_v16i1 295 ; MIPS32-LABEL: test_select_v16i1
296 ; MIPS32: addiu [[T0:.*]],sp,-20 296 ; MIPS32: addiu [[T0:.*]],sp,-32
297 ; MIPS32: sw [[T1:.*]], 297 ; MIPS32: sw [[T1:.*]],
298 ; MIPS32: sw [[T2:.*]], 298 ; MIPS32: sw [[T2:.*]],
299 ; MIPS32: sw [[T3:.*]], 299 ; MIPS32: sw [[T3:.*]],
300 ; MIPS32: sw [[T4:.*]], 300 ; MIPS32: sw [[T4:.*]],
301 ; MIPS32: sw [[T5:.*]], 301 ; MIPS32: sw [[T5:.*]],
302 ; MIPS32: lw [[T6:.*]], 302 ; MIPS32: lw [[T6:.*]],
303 ; MIPS32: lw [[T7:.*]], 303 ; MIPS32: lw [[T7:.*]],
304 ; MIPS32: lw [[T8:.*]], 304 ; MIPS32: lw [[T8:.*]],
305 ; MIPS32: lw [[T9:.*]], 305 ; MIPS32: lw [[T9:.*]],
306 ; MIPS32: lw [[T10:.*]], 306 ; MIPS32: lw [[T10:.*]],
(...skipping 56 matching lines...) Expand 10 before | Expand all | Expand 10 after
363 ; MIPS32: ori [[T14]],[[T14]],0xffff 363 ; MIPS32: ori [[T14]],[[T14]],0xffff
364 ; MIPS32: and [[T2]],[[T2]],[[T14]] 364 ; MIPS32: and [[T2]],[[T2]],[[T14]]
365 ; MIPS32: or [[T1]],[[T1]],[[T2]] 365 ; MIPS32: or [[T1]],[[T1]],[[T2]]
366 ; MIPS32: srl [[T16:.*]],a0,0x18 366 ; MIPS32: srl [[T16:.*]],a0,0x18
367 ; MIPS32: andi [[T16]],[[T16]],0x1 367 ; MIPS32: andi [[T16]],[[T16]],0x1
368 ; MIPS32: srl [[T6]],[[T6]],0x18 368 ; MIPS32: srl [[T6]],[[T6]],0x18
369 ; MIPS32: andi [[T6]],[[T6]],0x1 369 ; MIPS32: andi [[T6]],[[T6]],0x1
370 ; MIPS32: srl [[T10]],[[T10]],0x18 370 ; MIPS32: srl [[T10]],[[T10]],0x18
371 ; MIPS32: andi [[T10]],[[T10]],0x1 371 ; MIPS32: andi [[T10]],[[T10]],0x1
372 ; MIPS32: movn [[T10]],[[T6]],[[T16]] 372 ; MIPS32: movn [[T10]],[[T6]],[[T16]]
373 ; MIPS32: srl [[T10]],[[T10]],0x18 373 ; MIPS32: sll [[T10]],[[T10]],0x18
374 ; MIPS32: sll [[T1]],[[T1]],0x8 374 ; MIPS32: sll [[T1]],[[T1]],0x8
375 ; MIPS32: srl [[T1]],[[T1]],0x8 375 ; MIPS32: srl [[T1]],[[T1]],0x8
376 ; MIPS32: or [[T10]],[[T10]],[[T1]] 376 ; MIPS32: or [[T10]],[[T10]],[[T1]]
377 ; MIPS32: move [[T6]],a1 377 ; MIPS32: move [[T6]],a1
378 ; MIPS32: andi [[T6]],[[T6]],0xff 378 ; MIPS32: andi [[T6]],[[T6]],0xff
379 ; MIPS32: andi [[T6]],[[T6]],0x1 379 ; MIPS32: andi [[T6]],[[T6]],0x1
380 ; MIPS32: move [[T16]],[[T7]] 380 ; MIPS32: move [[T16]],[[T7]]
381 ; MIPS32: andi [[T16]],[[T16]],0xff 381 ; MIPS32: andi [[T16]],[[T16]],0xff
382 ; MIPS32: andi [[T16]],[[T16]],0x1 382 ; MIPS32: andi [[T16]],[[T16]],0x1
383 ; MIPS32: move [[T14]],[[T11]] 383 ; MIPS32: move [[T14]],[[T11]]
(...skipping 42 matching lines...) Expand 10 before | Expand all | Expand 10 after
426 ; MIPS32: ori [[T6]],[[T6]],0xffff 426 ; MIPS32: ori [[T6]],[[T6]],0xffff
427 ; MIPS32: and [[T15]],[[T15]],[[T6]] 427 ; MIPS32: and [[T15]],[[T15]],[[T6]]
428 ; MIPS32: or [[T14]],[[T14]],[[T15]] 428 ; MIPS32: or [[T14]],[[T14]],[[T15]]
429 ; MIPS32: srl [[T17:.*]],a1,0x18 429 ; MIPS32: srl [[T17:.*]],a1,0x18
430 ; MIPS32: andi [[T17]],[[T17]],0x1 430 ; MIPS32: andi [[T17]],[[T17]],0x1
431 ; MIPS32: srl [[T7]],[[T7]],0x18 431 ; MIPS32: srl [[T7]],[[T7]],0x18
432 ; MIPS32: andi [[T7]],[[T7]],0x1 432 ; MIPS32: andi [[T7]],[[T7]],0x1
433 ; MIPS32: srl [[T11]],[[T11]],0x18 433 ; MIPS32: srl [[T11]],[[T11]],0x18
434 ; MIPS32: andi [[T11]],[[T11]],0x1 434 ; MIPS32: andi [[T11]],[[T11]],0x1
435 ; MIPS32: movn [[T11]],[[T7]],[[T17]] 435 ; MIPS32: movn [[T11]],[[T7]],[[T17]]
436 ; MIPS32: srl [[T11]],[[T11]],0x18 436 ; MIPS32: sll [[T11]],[[T11]],0x18
437 ; MIPS32: sll [[T14]],[[T14]],0x8 437 ; MIPS32: sll [[T14]],[[T14]],0x8
438 ; MIPS32: srl [[T14]],[[T14]],0x8 438 ; MIPS32: srl [[T14]],[[T14]],0x8
439 ; MIPS32: or [[T11]],[[T11]],[[T14]] 439 ; MIPS32: or [[T11]],[[T11]],[[T14]]
440 ; MIPS32: move [[T6]],a2 440 ; MIPS32: move [[T6]],a2
441 ; MIPS32: andi [[T6]],[[T6]],0xff 441 ; MIPS32: andi [[T6]],[[T6]],0xff
442 ; MIPS32: andi [[T6]],[[T6]],0x1 442 ; MIPS32: andi [[T6]],[[T6]],0x1
443 ; MIPS32: move [[T7]],[[T8]] 443 ; MIPS32: move [[T7]],[[T8]]
444 ; MIPS32: andi [[T7]],[[T7]],0xff 444 ; MIPS32: andi [[T7]],[[T7]],0xff
445 ; MIPS32: andi [[T7]],[[T7]],0x1 445 ; MIPS32: andi [[T7]],[[T7]],0x1
446 ; MIPS32: move [[T16]],[[T12]] 446 ; MIPS32: move [[T16]],[[T12]]
(...skipping 42 matching lines...) Expand 10 before | Expand all | Expand 10 after
489 ; MIPS32: ori [[T6]],[[T6]],0xffff 489 ; MIPS32: ori [[T6]],[[T6]],0xffff
490 ; MIPS32: and [[T17]],[[T17]],[[T6]] 490 ; MIPS32: and [[T17]],[[T17]],[[T6]]
491 ; MIPS32: or [[T16]],[[T16]],[[T17]] 491 ; MIPS32: or [[T16]],[[T16]],[[T17]]
492 ; MIPS32: srl [[T18:.*]],a2,0x18 492 ; MIPS32: srl [[T18:.*]],a2,0x18
493 ; MIPS32: andi [[T18]],[[T18]],0x1 493 ; MIPS32: andi [[T18]],[[T18]],0x1
494 ; MIPS32: srl [[T8]],[[T8]],0x18 494 ; MIPS32: srl [[T8]],[[T8]],0x18
495 ; MIPS32: andi [[T8]],[[T8]],0x1 495 ; MIPS32: andi [[T8]],[[T8]],0x1
496 ; MIPS32: srl [[T12]],[[T12]],0x18 496 ; MIPS32: srl [[T12]],[[T12]],0x18
497 ; MIPS32: andi [[T12]],[[T12]],0x1 497 ; MIPS32: andi [[T12]],[[T12]],0x1
498 ; MIPS32: movn [[T12]],[[T8]],[[T18]] 498 ; MIPS32: movn [[T12]],[[T8]],[[T18]]
499 ; MIPS32: srl [[T12]],[[T12]],0x18 499 ; MIPS32: sll [[T12]],[[T12]],0x18
500 ; MIPS32: sll [[T16]],[[T16]],0x8 500 ; MIPS32: sll [[T16]],[[T16]],0x8
501 ; MIPS32: srl [[T16]],[[T16]],0x8 501 ; MIPS32: srl [[T16]],[[T16]],0x8
502 ; MIPS32: or [[T12]],[[T12]],[[T16]] 502 ; MIPS32: or [[T12]],[[T12]],[[T16]]
503 ; MIPS32: move [[T6]],a3 503 ; MIPS32: move [[T6]],a3
504 ; MIPS32: andi [[T6]],[[T6]],0xff 504 ; MIPS32: andi [[T6]],[[T6]],0xff
505 ; MIPS32: andi [[T6]],[[T6]],0x1 505 ; MIPS32: andi [[T6]],[[T6]],0x1
506 ; MIPS32: move [[T7]],[[T9]] 506 ; MIPS32: move [[T7]],[[T9]]
507 ; MIPS32: andi [[T7]],[[T7]],0xff 507 ; MIPS32: andi [[T7]],[[T7]],0xff
508 ; MIPS32: andi [[T7]],[[T7]],0x1 508 ; MIPS32: andi [[T7]],[[T7]],0x1
509 ; MIPS32: move [[T16]],[[T13]] 509 ; MIPS32: move [[T16]],[[T13]]
(...skipping 42 matching lines...) Expand 10 before | Expand all | Expand 10 after
552 ; MIPS32: ori [[T6]],[[T6]],0xffff 552 ; MIPS32: ori [[T6]],[[T6]],0xffff
553 ; MIPS32: and [[T17]],[[T17]],[[T6]] 553 ; MIPS32: and [[T17]],[[T17]],[[T6]]
554 ; MIPS32: or [[T16]],[[T16]],[[T17]] 554 ; MIPS32: or [[T16]],[[T16]],[[T17]]
555 ; MIPS32: srl [[T19:.*]],a3,0x18 555 ; MIPS32: srl [[T19:.*]],a3,0x18
556 ; MIPS32: andi [[T19]],[[T19]],0x1 556 ; MIPS32: andi [[T19]],[[T19]],0x1
557 ; MIPS32: srl [[T9]],[[T9]],0x18 557 ; MIPS32: srl [[T9]],[[T9]],0x18
558 ; MIPS32: andi [[T9]],[[T9]],0x1 558 ; MIPS32: andi [[T9]],[[T9]],0x1
559 ; MIPS32: srl [[T13]],[[T13]],0x18 559 ; MIPS32: srl [[T13]],[[T13]],0x18
560 ; MIPS32: andi [[T13]],[[T13]],0x1 560 ; MIPS32: andi [[T13]],[[T13]],0x1
561 ; MIPS32: movn [[T13]],[[T9]],[[T19]] 561 ; MIPS32: movn [[T13]],[[T9]],[[T19]]
562 ; MIPS32: srl [[T13]],[[T13]],0x18 562 ; MIPS32: sll [[T13]],[[T13]],0x18
563 ; MIPS32: sll [[T16]],[[T16]],0x8 563 ; MIPS32: sll [[T16]],[[T16]],0x8
564 ; MIPS32: srl [[T16]],[[T16]],0x8 564 ; MIPS32: srl [[T16]],[[T16]],0x8
565 ; MIPS32: or [[T13]],[[T13]],[[T16]] 565 ; MIPS32: or [[T13]],[[T13]],[[T16]]
566 ; MIPS32: move v0,[[T10]] 566 ; MIPS32: move v0,[[T10]]
567 ; MIPS32: move v1,[[T11]] 567 ; MIPS32: move v1,[[T11]]
568 ; MIPS32: move a0,[[T12]] 568 ; MIPS32: move a0,[[T12]]
569 ; MIPS32: move a1,[[T13]] 569 ; MIPS32: move a1,[[T13]]
570 ; MIPS32: lw [[T5]], 570 ; MIPS32: lw [[T5]],
571 ; MIPS32: lw [[T4]], 571 ; MIPS32: lw [[T4]],
572 ; MIPS32: lw [[T3]], 572 ; MIPS32: lw [[T3]],
573 ; MIPS32: lw [[T2]], 573 ; MIPS32: lw [[T2]],
574 ; MIPS32: lw [[T1]], 574 ; MIPS32: lw [[T1]],
575 ; MIPS32: addiu [[T0]],sp,20 575 ; MIPS32: addiu [[T0]],sp,32
576 } 576 }
577 577
578 define internal <8 x i16> @test_select_v8i16(<8 x i1> %cond, <8 x i16> %arg1, 578 define internal <8 x i16> @test_select_v8i16(<8 x i1> %cond, <8 x i16> %arg1,
579 <8 x i16> %arg2) { 579 <8 x i16> %arg2) {
580 entry: 580 entry:
581 %res = select <8 x i1> %cond, <8 x i16> %arg1, <8 x i16> %arg2 581 %res = select <8 x i1> %cond, <8 x i16> %arg1, <8 x i16> %arg2
582 ret <8 x i16> %res 582 ret <8 x i16> %res
583 ; CHECK-LABEL: test_select_v8i16 583 ; CHECK-LABEL: test_select_v8i16
584 ; CHECK: pand 584 ; CHECK: pand
585 ; CHECK: pandn 585 ; CHECK: pandn
586 ; CHECK: por 586 ; CHECK: por
587 587
588 ; SSE41-LABEL: test_select_v8i16 588 ; SSE41-LABEL: test_select_v8i16
589 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} 589 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
590 590
591 ; MIPS32-LABEL: test_select_v8i16 591 ; MIPS32-LABEL: test_select_v8i16
592 ; MIPS32: addiu [[T0:.*]],sp,-20 592 ; MIPS32: addiu [[T0:.*]],sp,-32
593 ; MIPS32: sw [[T1:.*]], 593 ; MIPS32: sw [[T1:.*]],
594 ; MIPS32: sw [[T2:.*]], 594 ; MIPS32: sw [[T2:.*]],
595 ; MIPS32: sw [[T3:.*]], 595 ; MIPS32: sw [[T3:.*]],
596 ; MIPS32: sw [[T4:.*]], 596 ; MIPS32: sw [[T4:.*]],
597 ; MIPS32: sw [[T5:.*]], 597 ; MIPS32: sw [[T5:.*]],
598 ; MIPS32: lw [[T6:.*]], 598 ; MIPS32: lw [[T6:.*]],
599 ; MIPS32: lw [[T7:.*]], 599 ; MIPS32: lw [[T7:.*]],
600 ; MIPS32: lw [[T8:.*]], 600 ; MIPS32: lw [[T8:.*]],
601 ; MIPS32: lw [[T9:.*]], 601 ; MIPS32: lw [[T9:.*]],
602 ; MIPS32: lw [[T10:.*]], 602 ; MIPS32: lw [[T10:.*]],
(...skipping 90 matching lines...) Expand 10 before | Expand all | Expand 10 after
693 ; MIPS32: or [[T13]],[[T13]],[[T16]] 693 ; MIPS32: or [[T13]],[[T13]],[[T16]]
694 ; MIPS32: move v0,[[T10]] 694 ; MIPS32: move v0,[[T10]]
695 ; MIPS32: move v1,[[T11]] 695 ; MIPS32: move v1,[[T11]]
696 ; MIPS32: move a0,[[T12]] 696 ; MIPS32: move a0,[[T12]]
697 ; MIPS32: move a1,[[T13]] 697 ; MIPS32: move a1,[[T13]]
698 ; MIPS32: lw [[T5]], 698 ; MIPS32: lw [[T5]],
699 ; MIPS32: lw [[T4]], 699 ; MIPS32: lw [[T4]],
700 ; MIPS32: lw [[T3]], 700 ; MIPS32: lw [[T3]],
701 ; MIPS32: lw [[T2]], 701 ; MIPS32: lw [[T2]],
702 ; MIPS32: lw [[T1]], 702 ; MIPS32: lw [[T1]],
703 ; MIPS32: addiu [[T0]],sp,20 703 ; MIPS32: addiu [[T0]],sp,32
704 } 704 }
705 705
706 define internal <8 x i1> @test_select_v8i1(<8 x i1> %cond, <8 x i1> %arg1, 706 define internal <8 x i1> @test_select_v8i1(<8 x i1> %cond, <8 x i1> %arg1,
707 <8 x i1> %arg2) { 707 <8 x i1> %arg2) {
708 entry: 708 entry:
709 %res = select <8 x i1> %cond, <8 x i1> %arg1, <8 x i1> %arg2 709 %res = select <8 x i1> %cond, <8 x i1> %arg1, <8 x i1> %arg2
710 ret <8 x i1> %res 710 ret <8 x i1> %res
711 ; CHECK-LABEL: test_select_v8i1 711 ; CHECK-LABEL: test_select_v8i1
712 ; CHECK: pand 712 ; CHECK: pand
713 ; CHECK: pandn 713 ; CHECK: pandn
714 ; CHECK: por 714 ; CHECK: por
715 715
716 ; SSE41-LABEL: test_select_v8i1 716 ; SSE41-LABEL: test_select_v8i1
717 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} 717 ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
718 718
719 ; MIPS32-LABEL: test_select_v8i1 719 ; MIPS32-LABEL: test_select_v8i1
720 ; MIPS32: addiu [[T0:.*]],sp,-20 720 ; MIPS32: addiu [[T0:.*]],sp,-32
721 ; MIPS32: sw [[T1:.*]], 721 ; MIPS32: sw [[T1:.*]],
722 ; MIPS32: sw [[T2:.*]], 722 ; MIPS32: sw [[T2:.*]],
723 ; MIPS32: sw [[T3:.*]], 723 ; MIPS32: sw [[T3:.*]],
724 ; MIPS32: sw [[T4:.*]], 724 ; MIPS32: sw [[T4:.*]],
725 ; MIPS32: sw [[T5:.*]], 725 ; MIPS32: sw [[T5:.*]],
726 ; MIPS32: lw [[T6:.*]], 726 ; MIPS32: lw [[T6:.*]],
727 ; MIPS32: lw [[T7:.*]], 727 ; MIPS32: lw [[T7:.*]],
728 ; MIPS32: lw [[T8:.*]], 728 ; MIPS32: lw [[T8:.*]],
729 ; MIPS32: lw [[T9:.*]], 729 ; MIPS32: lw [[T9:.*]],
730 ; MIPS32: lw [[T10:.*]], 730 ; MIPS32: lw [[T10:.*]],
(...skipping 106 matching lines...) Expand 10 before | Expand all | Expand 10 after
837 ; MIPS32: or [[T13]],[[T13]],[[T16]] 837 ; MIPS32: or [[T13]],[[T13]],[[T16]]
838 ; MIPS32: move v0,[[T10]] 838 ; MIPS32: move v0,[[T10]]
839 ; MIPS32: move v1,[[T11]] 839 ; MIPS32: move v1,[[T11]]
840 ; MIPS32: move a0,[[T12]] 840 ; MIPS32: move a0,[[T12]]
841 ; MIPS32: move a1,[[T13]] 841 ; MIPS32: move a1,[[T13]]
842 ; MIPS32: lw [[T5]], 842 ; MIPS32: lw [[T5]],
843 ; MIPS32: lw [[T4]], 843 ; MIPS32: lw [[T4]],
844 ; MIPS32: lw [[T3]], 844 ; MIPS32: lw [[T3]],
845 ; MIPS32: lw [[T2]], 845 ; MIPS32: lw [[T2]],
846 ; MIPS32: lw [[T1]], 846 ; MIPS32: lw [[T1]],
847 ; MIPS32: addiu [[T0]],sp,20 847 ; MIPS32: addiu [[T0]],sp,32
848 } 848 }
849 849
850 define internal <4 x i32> @test_select_v4i32(<4 x i1> %cond, <4 x i32> %arg1, 850 define internal <4 x i32> @test_select_v4i32(<4 x i1> %cond, <4 x i32> %arg1,
851 <4 x i32> %arg2) { 851 <4 x i32> %arg2) {
852 entry: 852 entry:
853 %res = select <4 x i1> %cond, <4 x i32> %arg1, <4 x i32> %arg2 853 %res = select <4 x i1> %cond, <4 x i32> %arg1, <4 x i32> %arg2
854 ret <4 x i32> %res 854 ret <4 x i32> %res
855 ; CHECK-LABEL: test_select_v4i32 855 ; CHECK-LABEL: test_select_v4i32
856 ; CHECK: pand 856 ; CHECK: pand
857 ; CHECK: pandn 857 ; CHECK: pandn
(...skipping 116 matching lines...) Expand 10 before | Expand all | Expand 10 after
974 ; MIPS32: movn [[T6]],[[T2]],[[T10]] 974 ; MIPS32: movn [[T6]],[[T2]],[[T10]]
975 ; MIPS32: andi [[T11:.*]],a3,0x1 975 ; MIPS32: andi [[T11:.*]],a3,0x1
976 ; MIPS32: andi [[T3]],[[T3]],0x1 976 ; MIPS32: andi [[T3]],[[T3]],0x1
977 ; MIPS32: andi [[T7]],[[T7]],0x1 977 ; MIPS32: andi [[T7]],[[T7]],0x1
978 ; MIPS32: movn [[T7]],[[T3]],[[T11]] 978 ; MIPS32: movn [[T7]],[[T3]],[[T11]]
979 ; MIPS32: move v0,[[T4]] 979 ; MIPS32: move v0,[[T4]]
980 ; MIPS32: move v1,[[T5]] 980 ; MIPS32: move v1,[[T5]]
981 ; MIPS32: move a0,[[T6]] 981 ; MIPS32: move a0,[[T6]]
982 ; MIPS32: move a1,[[T7]] 982 ; MIPS32: move a1,[[T7]]
983 } 983 }
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