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Issue 2619943003: [SubZero] Fix code generation issues occurred in Cross-test and PNaCL smoke-tests (Closed)
Patch Set: Addressed review comments Created 3 years, 11 months ago
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1 ; This file checks support for comparing vector values with the icmp 1 ; This file checks support for comparing vector values with the icmp
2 ; instruction. 2 ; instruction.
3 3
4 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 | FileCheck %s 4 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 | FileCheck %s
5 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 | FileCheck %s 5 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 | FileCheck %s
6 6
7 ; RUN: %if --need=target_MIPS32 --need=allow_dump \ 7 ; RUN: %if --need=target_MIPS32 --need=allow_dump \
8 ; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\ 8 ; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\
9 ; RUN: -i %s --args -O2 \ 9 ; RUN: -i %s --args -O2 \
10 ; RUN: | %if --need=target_MIPS32 --need=allow_dump \ 10 ; RUN: | %if --need=target_MIPS32 --need=allow_dump \
(...skipping 2740 matching lines...) Expand 10 before | Expand all | Expand 10 after
2751 ; MIPS32: lui [[T9]],0xff00 2751 ; MIPS32: lui [[T9]],0xff00
2752 ; MIPS32: ori [[T9]],[[T9]],0xffff 2752 ; MIPS32: ori [[T9]],[[T9]],0xffff
2753 ; MIPS32: and [[T4]],[[T4]],[[T9]] 2753 ; MIPS32: and [[T4]],[[T4]],[[T9]]
2754 ; MIPS32: or [[T8]],[[T8]],[[T4]] 2754 ; MIPS32: or [[T8]],[[T8]],[[T4]]
2755 ; MIPS32: srl [[T10:.*]],a0,0x18 2755 ; MIPS32: srl [[T10:.*]],a0,0x18
2756 ; MIPS32: srl [[T0]],[[T0]],0x18 2756 ; MIPS32: srl [[T0]],[[T0]],0x18
2757 ; MIPS32: sll [[T10]],[[T10]],0x18 2757 ; MIPS32: sll [[T10]],[[T10]],0x18
2758 ; MIPS32: sll [[T0]],[[T0]],0x18 2758 ; MIPS32: sll [[T0]],[[T0]],0x18
2759 ; MIPS32: xor [[T10]],[[T10]],[[T0]] 2759 ; MIPS32: xor [[T10]],[[T10]],[[T0]]
2760 ; MIPS32: sltiu [[T10]],[[T10]],1 2760 ; MIPS32: sltiu [[T10]],[[T10]],1
2761 ; MIPS32: srl [[T10]],[[T10]],0x18 2761 ; MIPS32: sll [[T10]],[[T10]],0x18
2762 ; MIPS32: sll [[T8]],[[T8]],0x8 2762 ; MIPS32: sll [[T8]],[[T8]],0x8
2763 ; MIPS32: srl [[T8]],[[T8]],0x8 2763 ; MIPS32: srl [[T8]],[[T8]],0x8
2764 ; MIPS32: or [[T10]],[[T10]],[[T8]] 2764 ; MIPS32: or [[T10]],[[T10]],[[T8]]
2765 ; MIPS32: move [[T0]],a1 2765 ; MIPS32: move [[T0]],a1
2766 ; MIPS32: andi [[T0]],[[T0]],0xff 2766 ; MIPS32: andi [[T0]],[[T0]],0xff
2767 ; MIPS32: move [[T4]],[[T1]] 2767 ; MIPS32: move [[T4]],[[T1]]
2768 ; MIPS32: andi [[T4]],[[T4]],0xff 2768 ; MIPS32: andi [[T4]],[[T4]],0xff
2769 ; MIPS32: sll [[T0]],[[T0]],0x18 2769 ; MIPS32: sll [[T0]],[[T0]],0x18
2770 ; MIPS32: sll [[T4]],[[T4]],0x18 2770 ; MIPS32: sll [[T4]],[[T4]],0x18
2771 ; MIPS32: xor [[T0]],[[T0]],[[T4]] 2771 ; MIPS32: xor [[T0]],[[T0]],[[T4]]
(...skipping 33 matching lines...) Expand 10 before | Expand all | Expand 10 after
2805 ; MIPS32: lui [[T5]],0xff00 2805 ; MIPS32: lui [[T5]],0xff00
2806 ; MIPS32: ori [[T5]],[[T5]],0xffff 2806 ; MIPS32: ori [[T5]],[[T5]],0xffff
2807 ; MIPS32: and [[T4]],[[T4]],[[T5]] 2807 ; MIPS32: and [[T4]],[[T4]],[[T5]]
2808 ; MIPS32: or [[T0]],[[T0]],[[T4]] 2808 ; MIPS32: or [[T0]],[[T0]],[[T4]]
2809 ; MIPS32: srl [[T11:.*]],a1,0x18 2809 ; MIPS32: srl [[T11:.*]],a1,0x18
2810 ; MIPS32: srl [[T1]],[[T1]],0x18 2810 ; MIPS32: srl [[T1]],[[T1]],0x18
2811 ; MIPS32: sll [[T11]],[[T11]],0x18 2811 ; MIPS32: sll [[T11]],[[T11]],0x18
2812 ; MIPS32: sll [[T1]],[[T1]],0x18 2812 ; MIPS32: sll [[T1]],[[T1]],0x18
2813 ; MIPS32: xor [[T11]],[[T11]],[[T1]] 2813 ; MIPS32: xor [[T11]],[[T11]],[[T1]]
2814 ; MIPS32: sltiu [[T11]],[[T11]],1 2814 ; MIPS32: sltiu [[T11]],[[T11]],1
2815 ; MIPS32: srl [[T11]],[[T11]],0x18 2815 ; MIPS32: sll [[T11]],[[T11]],0x18
2816 ; MIPS32: sll [[T0]],[[T0]],0x8 2816 ; MIPS32: sll [[T0]],[[T0]],0x8
2817 ; MIPS32: srl [[T0]],[[T0]],0x8 2817 ; MIPS32: srl [[T0]],[[T0]],0x8
2818 ; MIPS32: or [[T11]],[[T11]],[[T0]] 2818 ; MIPS32: or [[T11]],[[T11]],[[T0]]
2819 ; MIPS32: move [[T0]],a2 2819 ; MIPS32: move [[T0]],a2
2820 ; MIPS32: andi [[T0]],[[T0]],0xff 2820 ; MIPS32: andi [[T0]],[[T0]],0xff
2821 ; MIPS32: move [[T1]],[[T2]] 2821 ; MIPS32: move [[T1]],[[T2]]
2822 ; MIPS32: andi [[T1]],[[T1]],0xff 2822 ; MIPS32: andi [[T1]],[[T1]],0xff
2823 ; MIPS32: sll [[T0]],[[T0]],0x18 2823 ; MIPS32: sll [[T0]],[[T0]],0x18
2824 ; MIPS32: sll [[T1]],[[T1]],0x18 2824 ; MIPS32: sll [[T1]],[[T1]],0x18
2825 ; MIPS32: xor [[T0]],[[T0]],[[T1]] 2825 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
(...skipping 33 matching lines...) Expand 10 before | Expand all | Expand 10 after
2859 ; MIPS32: lui [[T4]],0xff00 2859 ; MIPS32: lui [[T4]],0xff00
2860 ; MIPS32: ori [[T4]],[[T4]],0xffff 2860 ; MIPS32: ori [[T4]],[[T4]],0xffff
2861 ; MIPS32: and [[T1]],[[T1]],[[T4]] 2861 ; MIPS32: and [[T1]],[[T1]],[[T4]]
2862 ; MIPS32: or [[T0]],[[T0]],[[T1]] 2862 ; MIPS32: or [[T0]],[[T0]],[[T1]]
2863 ; MIPS32: srl [[T12:.*]],a2,0x18 2863 ; MIPS32: srl [[T12:.*]],a2,0x18
2864 ; MIPS32: srl [[T2]],[[T2]],0x18 2864 ; MIPS32: srl [[T2]],[[T2]],0x18
2865 ; MIPS32: sll [[T12]],[[T12]],0x18 2865 ; MIPS32: sll [[T12]],[[T12]],0x18
2866 ; MIPS32: sll [[T2]],[[T2]],0x18 2866 ; MIPS32: sll [[T2]],[[T2]],0x18
2867 ; MIPS32: xor [[T12]],[[T12]],[[T2]] 2867 ; MIPS32: xor [[T12]],[[T12]],[[T2]]
2868 ; MIPS32: sltiu [[T12]],[[T12]],1 2868 ; MIPS32: sltiu [[T12]],[[T12]],1
2869 ; MIPS32: srl [[T12]],[[T12]],0x18 2869 ; MIPS32: sll [[T12]],[[T12]],0x18
2870 ; MIPS32: sll [[T0]],[[T0]],0x8 2870 ; MIPS32: sll [[T0]],[[T0]],0x8
2871 ; MIPS32: srl [[T0]],[[T0]],0x8 2871 ; MIPS32: srl [[T0]],[[T0]],0x8
2872 ; MIPS32: or [[T12]],[[T12]],[[T0]] 2872 ; MIPS32: or [[T12]],[[T12]],[[T0]]
2873 ; MIPS32: move [[T0]],a3 2873 ; MIPS32: move [[T0]],a3
2874 ; MIPS32: andi [[T0]],[[T0]],0xff 2874 ; MIPS32: andi [[T0]],[[T0]],0xff
2875 ; MIPS32: move [[T1]],[[T3]] 2875 ; MIPS32: move [[T1]],[[T3]]
2876 ; MIPS32: andi [[T1]],[[T1]],0xff 2876 ; MIPS32: andi [[T1]],[[T1]],0xff
2877 ; MIPS32: sll [[T0]],[[T0]],0x18 2877 ; MIPS32: sll [[T0]],[[T0]],0x18
2878 ; MIPS32: sll [[T1]],[[T1]],0x18 2878 ; MIPS32: sll [[T1]],[[T1]],0x18
2879 ; MIPS32: xor [[T0]],[[T0]],[[T1]] 2879 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
(...skipping 33 matching lines...) Expand 10 before | Expand all | Expand 10 after
2913 ; MIPS32: lui [[T2]],0xff00 2913 ; MIPS32: lui [[T2]],0xff00
2914 ; MIPS32: ori [[T2]],[[T2]],0xffff 2914 ; MIPS32: ori [[T2]],[[T2]],0xffff
2915 ; MIPS32: and [[T1]],[[T1]],[[T2]] 2915 ; MIPS32: and [[T1]],[[T1]],[[T2]]
2916 ; MIPS32: or [[T0]],[[T0]],[[T1]] 2916 ; MIPS32: or [[T0]],[[T0]],[[T1]]
2917 ; MIPS32: srl [[T13:.*]],a3,0x18 2917 ; MIPS32: srl [[T13:.*]],a3,0x18
2918 ; MIPS32: srl [[T3]],[[T3]],0x18 2918 ; MIPS32: srl [[T3]],[[T3]],0x18
2919 ; MIPS32: sll [[T13]],[[T13]],0x18 2919 ; MIPS32: sll [[T13]],[[T13]],0x18
2920 ; MIPS32: sll [[T3]],[[T3]],0x18 2920 ; MIPS32: sll [[T3]],[[T3]],0x18
2921 ; MIPS32: xor [[T13]],[[T13]],[[T3]] 2921 ; MIPS32: xor [[T13]],[[T13]],[[T3]]
2922 ; MIPS32: sltiu [[T13]],[[T13]],1 2922 ; MIPS32: sltiu [[T13]],[[T13]],1
2923 ; MIPS32: srl [[T13]],[[T13]],0x18 2923 ; MIPS32: sll [[T13]],[[T13]],0x18
2924 ; MIPS32: sll [[T0]],[[T0]],0x8 2924 ; MIPS32: sll [[T0]],[[T0]],0x8
2925 ; MIPS32: srl [[T0]],[[T0]],0x8 2925 ; MIPS32: srl [[T0]],[[T0]],0x8
2926 ; MIPS32: or [[T13]],[[T13]],[[T0]] 2926 ; MIPS32: or [[T13]],[[T13]],[[T0]]
2927 ; MIPS32: move v0,[[T10]] 2927 ; MIPS32: move v0,[[T10]]
2928 ; MIPS32: move v1,[[T11]] 2928 ; MIPS32: move v1,[[T11]]
2929 ; MIPS32: move a0,[[T12]] 2929 ; MIPS32: move a0,[[T12]]
2930 ; MIPS32: move a1,[[T13]] 2930 ; MIPS32: move a1,[[T13]]
2931 } 2931 }
2932 2932
2933 define internal <16 x i1> @test_icmp_v16i8_ne(<16 x i8> %a, <16 x i8> %b) { 2933 define internal <16 x i1> @test_icmp_v16i8_ne(<16 x i8> %a, <16 x i8> %b) {
(...skipping 56 matching lines...) Expand 10 before | Expand all | Expand 10 after
2990 ; MIPS32: lui [[T9]],0xff00 2990 ; MIPS32: lui [[T9]],0xff00
2991 ; MIPS32: ori [[T9]],[[T9]],0xffff 2991 ; MIPS32: ori [[T9]],[[T9]],0xffff
2992 ; MIPS32: and [[T4]],[[T4]],[[T9]] 2992 ; MIPS32: and [[T4]],[[T4]],[[T9]]
2993 ; MIPS32: or [[T8]],[[T8]],[[T4]] 2993 ; MIPS32: or [[T8]],[[T8]],[[T4]]
2994 ; MIPS32: srl [[T10:.*]],a0,0x18 2994 ; MIPS32: srl [[T10:.*]],a0,0x18
2995 ; MIPS32: srl [[T0]],[[T0]],0x18 2995 ; MIPS32: srl [[T0]],[[T0]],0x18
2996 ; MIPS32: sll [[T10]],[[T10]],0x18 2996 ; MIPS32: sll [[T10]],[[T10]],0x18
2997 ; MIPS32: sll [[T0]],[[T0]],0x18 2997 ; MIPS32: sll [[T0]],[[T0]],0x18
2998 ; MIPS32: xor [[T10]],[[T10]],[[T0]] 2998 ; MIPS32: xor [[T10]],[[T10]],[[T0]]
2999 ; MIPS32: sltu [[T10]],zero,[[T10]] 2999 ; MIPS32: sltu [[T10]],zero,[[T10]]
3000 ; MIPS32: srl [[T10]],[[T10]],0x18 3000 ; MIPS32: sll [[T10]],[[T10]],0x18
3001 ; MIPS32: sll [[T8]],[[T8]],0x8 3001 ; MIPS32: sll [[T8]],[[T8]],0x8
3002 ; MIPS32: srl [[T8]],[[T8]],0x8 3002 ; MIPS32: srl [[T8]],[[T8]],0x8
3003 ; MIPS32: or [[T10]],[[T10]],[[T8]] 3003 ; MIPS32: or [[T10]],[[T10]],[[T8]]
3004 ; MIPS32: move [[T0]],a1 3004 ; MIPS32: move [[T0]],a1
3005 ; MIPS32: andi [[T0]],[[T0]],0xff 3005 ; MIPS32: andi [[T0]],[[T0]],0xff
3006 ; MIPS32: move [[T4]],[[T1]] 3006 ; MIPS32: move [[T4]],[[T1]]
3007 ; MIPS32: andi [[T4]],[[T4]],0xff 3007 ; MIPS32: andi [[T4]],[[T4]],0xff
3008 ; MIPS32: sll [[T0]],[[T0]],0x18 3008 ; MIPS32: sll [[T0]],[[T0]],0x18
3009 ; MIPS32: sll [[T4]],[[T4]],0x18 3009 ; MIPS32: sll [[T4]],[[T4]],0x18
3010 ; MIPS32: xor [[T0]],[[T0]],[[T4]] 3010 ; MIPS32: xor [[T0]],[[T0]],[[T4]]
(...skipping 33 matching lines...) Expand 10 before | Expand all | Expand 10 after
3044 ; MIPS32: lui [[T5]],0xff00 3044 ; MIPS32: lui [[T5]],0xff00
3045 ; MIPS32: ori [[T5]],[[T5]],0xffff 3045 ; MIPS32: ori [[T5]],[[T5]],0xffff
3046 ; MIPS32: and [[T4]],[[T4]],[[T5]] 3046 ; MIPS32: and [[T4]],[[T4]],[[T5]]
3047 ; MIPS32: or [[T0]],[[T0]],[[T4]] 3047 ; MIPS32: or [[T0]],[[T0]],[[T4]]
3048 ; MIPS32: srl [[T11:.*]],a1,0x18 3048 ; MIPS32: srl [[T11:.*]],a1,0x18
3049 ; MIPS32: srl [[T1]],[[T1]],0x18 3049 ; MIPS32: srl [[T1]],[[T1]],0x18
3050 ; MIPS32: sll [[T11]],[[T11]],0x18 3050 ; MIPS32: sll [[T11]],[[T11]],0x18
3051 ; MIPS32: sll [[T1]],[[T1]],0x18 3051 ; MIPS32: sll [[T1]],[[T1]],0x18
3052 ; MIPS32: xor [[T11]],[[T11]],[[T1]] 3052 ; MIPS32: xor [[T11]],[[T11]],[[T1]]
3053 ; MIPS32: sltu [[T11]],zero,[[T11]] 3053 ; MIPS32: sltu [[T11]],zero,[[T11]]
3054 ; MIPS32: srl [[T11]],[[T11]],0x18 3054 ; MIPS32: sll [[T11]],[[T11]],0x18
3055 ; MIPS32: sll [[T0]],[[T0]],0x8 3055 ; MIPS32: sll [[T0]],[[T0]],0x8
3056 ; MIPS32: srl [[T0]],[[T0]],0x8 3056 ; MIPS32: srl [[T0]],[[T0]],0x8
3057 ; MIPS32: or [[T11]],[[T11]],[[T0]] 3057 ; MIPS32: or [[T11]],[[T11]],[[T0]]
3058 ; MIPS32: move [[T0]],a2 3058 ; MIPS32: move [[T0]],a2
3059 ; MIPS32: andi [[T0]],[[T0]],0xff 3059 ; MIPS32: andi [[T0]],[[T0]],0xff
3060 ; MIPS32: move [[T1]],[[T2]] 3060 ; MIPS32: move [[T1]],[[T2]]
3061 ; MIPS32: andi [[T1]],[[T1]],0xff 3061 ; MIPS32: andi [[T1]],[[T1]],0xff
3062 ; MIPS32: sll [[T0]],[[T0]],0x18 3062 ; MIPS32: sll [[T0]],[[T0]],0x18
3063 ; MIPS32: sll [[T1]],[[T1]],0x18 3063 ; MIPS32: sll [[T1]],[[T1]],0x18
3064 ; MIPS32: xor [[T0]],[[T0]],[[T1]] 3064 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
(...skipping 33 matching lines...) Expand 10 before | Expand all | Expand 10 after
3098 ; MIPS32: lui [[T4]],0xff00 3098 ; MIPS32: lui [[T4]],0xff00
3099 ; MIPS32: ori [[T4]],[[T4]],0xffff 3099 ; MIPS32: ori [[T4]],[[T4]],0xffff
3100 ; MIPS32: and [[T1]],[[T1]],[[T4]] 3100 ; MIPS32: and [[T1]],[[T1]],[[T4]]
3101 ; MIPS32: or [[T0]],[[T0]],[[T1]] 3101 ; MIPS32: or [[T0]],[[T0]],[[T1]]
3102 ; MIPS32: srl [[T12:.*]],a2,0x18 3102 ; MIPS32: srl [[T12:.*]],a2,0x18
3103 ; MIPS32: srl [[T2]],[[T2]],0x18 3103 ; MIPS32: srl [[T2]],[[T2]],0x18
3104 ; MIPS32: sll [[T12]],[[T12]],0x18 3104 ; MIPS32: sll [[T12]],[[T12]],0x18
3105 ; MIPS32: sll [[T2]],[[T2]],0x18 3105 ; MIPS32: sll [[T2]],[[T2]],0x18
3106 ; MIPS32: xor [[T12]],[[T12]],[[T2]] 3106 ; MIPS32: xor [[T12]],[[T12]],[[T2]]
3107 ; MIPS32: sltu [[T12]],zero,[[T12]] 3107 ; MIPS32: sltu [[T12]],zero,[[T12]]
3108 ; MIPS32: srl [[T12]],[[T12]],0x18 3108 ; MIPS32: sll [[T12]],[[T12]],0x18
3109 ; MIPS32: sll [[T0]],[[T0]],0x8 3109 ; MIPS32: sll [[T0]],[[T0]],0x8
3110 ; MIPS32: srl [[T0]],[[T0]],0x8 3110 ; MIPS32: srl [[T0]],[[T0]],0x8
3111 ; MIPS32: or [[T12]],[[T12]],[[T0]] 3111 ; MIPS32: or [[T12]],[[T12]],[[T0]]
3112 ; MIPS32: move [[T0]],a3 3112 ; MIPS32: move [[T0]],a3
3113 ; MIPS32: andi [[T0]],[[T0]],0xff 3113 ; MIPS32: andi [[T0]],[[T0]],0xff
3114 ; MIPS32: move [[T1]],[[T3]] 3114 ; MIPS32: move [[T1]],[[T3]]
3115 ; MIPS32: andi [[T1]],[[T1]],0xff 3115 ; MIPS32: andi [[T1]],[[T1]],0xff
3116 ; MIPS32: sll [[T0]],[[T0]],0x18 3116 ; MIPS32: sll [[T0]],[[T0]],0x18
3117 ; MIPS32: sll [[T1]],[[T1]],0x18 3117 ; MIPS32: sll [[T1]],[[T1]],0x18
3118 ; MIPS32: xor [[T0]],[[T0]],[[T1]] 3118 ; MIPS32: xor [[T0]],[[T0]],[[T1]]
(...skipping 33 matching lines...) Expand 10 before | Expand all | Expand 10 after
3152 ; MIPS32: lui [[T2]],0xff00 3152 ; MIPS32: lui [[T2]],0xff00
3153 ; MIPS32: ori [[T2]],[[T2]],0xffff 3153 ; MIPS32: ori [[T2]],[[T2]],0xffff
3154 ; MIPS32: and [[T1]],[[T1]],[[T2]] 3154 ; MIPS32: and [[T1]],[[T1]],[[T2]]
3155 ; MIPS32: or [[T0]],[[T0]],[[T1]] 3155 ; MIPS32: or [[T0]],[[T0]],[[T1]]
3156 ; MIPS32: srl [[T13:.*]],a3,0x18 3156 ; MIPS32: srl [[T13:.*]],a3,0x18
3157 ; MIPS32: srl [[T3]],[[T3]],0x18 3157 ; MIPS32: srl [[T3]],[[T3]],0x18
3158 ; MIPS32: sll [[T13]],[[T13]],0x18 3158 ; MIPS32: sll [[T13]],[[T13]],0x18
3159 ; MIPS32: sll [[T3]],[[T3]],0x18 3159 ; MIPS32: sll [[T3]],[[T3]],0x18
3160 ; MIPS32: xor [[T13]],[[T13]],[[T3]] 3160 ; MIPS32: xor [[T13]],[[T13]],[[T3]]
3161 ; MIPS32: sltu [[T13]],zero,[[T13]] 3161 ; MIPS32: sltu [[T13]],zero,[[T13]]
3162 ; MIPS32: srl [[T13]],[[T13]],0x18 3162 ; MIPS32: sll [[T13]],[[T13]],0x18
3163 ; MIPS32: sll [[T0]],[[T0]],0x8 3163 ; MIPS32: sll [[T0]],[[T0]],0x8
3164 ; MIPS32: srl [[T0]],[[T0]],0x8 3164 ; MIPS32: srl [[T0]],[[T0]],0x8
3165 ; MIPS32: or [[T13]],[[T13]],[[T0]] 3165 ; MIPS32: or [[T13]],[[T13]],[[T0]]
3166 ; MIPS32: move v0,[[T10]] 3166 ; MIPS32: move v0,[[T10]]
3167 ; MIPS32: move v1,[[T11]] 3167 ; MIPS32: move v1,[[T11]]
3168 ; MIPS32: move a0,[[T12]] 3168 ; MIPS32: move a0,[[T12]]
3169 ; MIPS32: move a1,[[T13]] 3169 ; MIPS32: move a1,[[T13]]
3170 } 3170 }
3171 3171
3172 define internal <16 x i1> @test_icmp_v16i8_sgt(<16 x i8> %a, <16 x i8> %b) { 3172 define internal <16 x i1> @test_icmp_v16i8_sgt(<16 x i8> %a, <16 x i8> %b) {
(...skipping 51 matching lines...) Expand 10 before | Expand all | Expand 10 after
3224 ; MIPS32: sll [[T9]],[[T9]],0x10 3224 ; MIPS32: sll [[T9]],[[T9]],0x10
3225 ; MIPS32: lui [[T4]],0xff00 3225 ; MIPS32: lui [[T4]],0xff00
3226 ; MIPS32: ori [[T4]],[[T4]],0xffff 3226 ; MIPS32: ori [[T4]],[[T4]],0xffff
3227 ; MIPS32: and [[T8]],[[T8]],[[T4]] 3227 ; MIPS32: and [[T8]],[[T8]],[[T4]]
3228 ; MIPS32: or [[T9]],[[T9]],[[T8]] 3228 ; MIPS32: or [[T9]],[[T9]],[[T8]]
3229 ; MIPS32: srl [[T10:.*]],a0,0x18 3229 ; MIPS32: srl [[T10:.*]],a0,0x18
3230 ; MIPS32: srl [[T0]],[[T0]],0x18 3230 ; MIPS32: srl [[T0]],[[T0]],0x18
3231 ; MIPS32: sll [[T10]],[[T10]],0x18 3231 ; MIPS32: sll [[T10]],[[T10]],0x18
3232 ; MIPS32: sll [[T0]],[[T0]],0x18 3232 ; MIPS32: sll [[T0]],[[T0]],0x18
3233 ; MIPS32: slt [[T0]],[[T0]],[[T10]] 3233 ; MIPS32: slt [[T0]],[[T0]],[[T10]]
3234 ; MIPS32: srl [[T0]],[[T0]],0x18 3234 ; MIPS32: sll [[T0]],[[T0]],0x18
3235 ; MIPS32: sll [[T9]],[[T9]],0x8 3235 ; MIPS32: sll [[T9]],[[T9]],0x8
3236 ; MIPS32: srl [[T9]],[[T9]],0x8 3236 ; MIPS32: srl [[T9]],[[T9]],0x8
3237 ; MIPS32: or v0,[[T0]],[[T9]] 3237 ; MIPS32: or v0,[[T0]],[[T9]]
3238 ; MIPS32: move [[T10]],a1 3238 ; MIPS32: move [[T10]],a1
3239 ; MIPS32: andi [[T10]],[[T10]],0xff 3239 ; MIPS32: andi [[T10]],[[T10]],0xff
3240 ; MIPS32: move [[T4]],[[T1]] 3240 ; MIPS32: move [[T4]],[[T1]]
3241 ; MIPS32: andi [[T4]],[[T4]],0xff 3241 ; MIPS32: andi [[T4]],[[T4]],0xff
3242 ; MIPS32: sll [[T10]],[[T10]],0x18 3242 ; MIPS32: sll [[T10]],[[T10]],0x18
3243 ; MIPS32: sll [[T4]],[[T4]],0x18 3243 ; MIPS32: sll [[T4]],[[T4]],0x18
3244 ; MIPS32: slt [[T4]],[[T4]],[[T10]] 3244 ; MIPS32: slt [[T4]],[[T4]],[[T10]]
(...skipping 29 matching lines...) Expand all
3274 ; MIPS32: sll [[T4]],[[T4]],0x10 3274 ; MIPS32: sll [[T4]],[[T4]],0x10
3275 ; MIPS32: lui [[T10]],0xff00 3275 ; MIPS32: lui [[T10]],0xff00
3276 ; MIPS32: ori [[T10]],[[T10]],0xffff 3276 ; MIPS32: ori [[T10]],[[T10]],0xffff
3277 ; MIPS32: and [[T5]],[[T5]],[[T10]] 3277 ; MIPS32: and [[T5]],[[T5]],[[T10]]
3278 ; MIPS32: or [[T4]],[[T4]],[[T5]] 3278 ; MIPS32: or [[T4]],[[T4]],[[T5]]
3279 ; MIPS32: srl [[T11:.*]],a1,0x18 3279 ; MIPS32: srl [[T11:.*]],a1,0x18
3280 ; MIPS32: srl [[T1]],[[T1]],0x18 3280 ; MIPS32: srl [[T1]],[[T1]],0x18
3281 ; MIPS32: sll [[T11]],[[T11]],0x18 3281 ; MIPS32: sll [[T11]],[[T11]],0x18
3282 ; MIPS32: sll [[T1]],[[T1]],0x18 3282 ; MIPS32: sll [[T1]],[[T1]],0x18
3283 ; MIPS32: slt [[T1]],[[T1]],[[T11]] 3283 ; MIPS32: slt [[T1]],[[T1]],[[T11]]
3284 ; MIPS32: srl [[T1]],[[T1]],0x18 3284 ; MIPS32: sll [[T1]],[[T1]],0x18
3285 ; MIPS32: sll [[T4]],[[T4]],0x8 3285 ; MIPS32: sll [[T4]],[[T4]],0x8
3286 ; MIPS32: srl [[T4]],[[T4]],0x8 3286 ; MIPS32: srl [[T4]],[[T4]],0x8
3287 ; MIPS32: or v1,[[T1]],[[T4]] 3287 ; MIPS32: or v1,[[T1]],[[T4]]
3288 ; MIPS32: move [[T10]],a2 3288 ; MIPS32: move [[T10]],a2
3289 ; MIPS32: andi [[T10]],[[T10]],0xff 3289 ; MIPS32: andi [[T10]],[[T10]],0xff
3290 ; MIPS32: move [[T11]],[[T2]] 3290 ; MIPS32: move [[T11]],[[T2]]
3291 ; MIPS32: andi [[T11]],[[T11]],0xff 3291 ; MIPS32: andi [[T11]],[[T11]],0xff
3292 ; MIPS32: sll [[T10]],[[T10]],0x18 3292 ; MIPS32: sll [[T10]],[[T10]],0x18
3293 ; MIPS32: sll [[T11]],[[T11]],0x18 3293 ; MIPS32: sll [[T11]],[[T11]],0x18
3294 ; MIPS32: slt [[T11]],[[T11]],[[T10]] 3294 ; MIPS32: slt [[T11]],[[T11]],[[T10]]
(...skipping 29 matching lines...) Expand all
3324 ; MIPS32: sll [[T11]],[[T11]],0x10 3324 ; MIPS32: sll [[T11]],[[T11]],0x10
3325 ; MIPS32: lui [[T10]],0xff00 3325 ; MIPS32: lui [[T10]],0xff00
3326 ; MIPS32: ori [[T10]],[[T10]],0xffff 3326 ; MIPS32: ori [[T10]],[[T10]],0xffff
3327 ; MIPS32: and [[T4]],[[T4]],[[T10]] 3327 ; MIPS32: and [[T4]],[[T4]],[[T10]]
3328 ; MIPS32: or [[T11]],[[T11]],[[T4]] 3328 ; MIPS32: or [[T11]],[[T11]],[[T4]]
3329 ; MIPS32: srl [[T12:.*]],a2,0x18 3329 ; MIPS32: srl [[T12:.*]],a2,0x18
3330 ; MIPS32: srl [[T2]],[[T2]],0x18 3330 ; MIPS32: srl [[T2]],[[T2]],0x18
3331 ; MIPS32: sll [[T12]],[[T12]],0x18 3331 ; MIPS32: sll [[T12]],[[T12]],0x18
3332 ; MIPS32: sll [[T2]],[[T2]],0x18 3332 ; MIPS32: sll [[T2]],[[T2]],0x18
3333 ; MIPS32: slt [[T2]],[[T2]],[[T12]] 3333 ; MIPS32: slt [[T2]],[[T2]],[[T12]]
3334 ; MIPS32: srl [[T2]],[[T2]],0x18 3334 ; MIPS32: sll [[T2]],[[T2]],0x18
3335 ; MIPS32: sll [[T11]],[[T11]],0x8 3335 ; MIPS32: sll [[T11]],[[T11]],0x8
3336 ; MIPS32: srl [[T11]],[[T11]],0x8 3336 ; MIPS32: srl [[T11]],[[T11]],0x8
3337 ; MIPS32: or [[T2]],[[T2]],[[T11]] 3337 ; MIPS32: or [[T2]],[[T2]],[[T11]]
3338 ; MIPS32: move [[T10]],a3 3338 ; MIPS32: move [[T10]],a3
3339 ; MIPS32: andi [[T10]],[[T10]],0xff 3339 ; MIPS32: andi [[T10]],[[T10]],0xff
3340 ; MIPS32: move [[T11]],[[T3]] 3340 ; MIPS32: move [[T11]],[[T3]]
3341 ; MIPS32: andi [[T11]],[[T11]],0xff 3341 ; MIPS32: andi [[T11]],[[T11]],0xff
3342 ; MIPS32: sll [[T10]],[[T10]],0x18 3342 ; MIPS32: sll [[T10]],[[T10]],0x18
3343 ; MIPS32: sll [[T11]],[[T11]],0x18 3343 ; MIPS32: sll [[T11]],[[T11]],0x18
3344 ; MIPS32: slt [[T11]],[[T11]],[[T10]] 3344 ; MIPS32: slt [[T11]],[[T11]],[[T10]]
(...skipping 29 matching lines...) Expand all
3374 ; MIPS32: sll [[T11]],[[T11]],0x10 3374 ; MIPS32: sll [[T11]],[[T11]],0x10
3375 ; MIPS32: lui [[T10]],0xff00 3375 ; MIPS32: lui [[T10]],0xff00
3376 ; MIPS32: ori [[T10]],[[T10]],0xffff 3376 ; MIPS32: ori [[T10]],[[T10]],0xffff
3377 ; MIPS32: and [[T12]],[[T12]],[[T10]] 3377 ; MIPS32: and [[T12]],[[T12]],[[T10]]
3378 ; MIPS32: or [[T11]],[[T11]],[[T12]] 3378 ; MIPS32: or [[T11]],[[T11]],[[T12]]
3379 ; MIPS32: srl [[T13:.*]],a3,0x18 3379 ; MIPS32: srl [[T13:.*]],a3,0x18
3380 ; MIPS32: srl [[T3]],[[T3]],0x18 3380 ; MIPS32: srl [[T3]],[[T3]],0x18
3381 ; MIPS32: sll [[T13]],[[T13]],0x18 3381 ; MIPS32: sll [[T13]],[[T13]],0x18
3382 ; MIPS32: sll [[T3]],[[T3]],0x18 3382 ; MIPS32: sll [[T3]],[[T3]],0x18
3383 ; MIPS32: slt [[T3]],[[T3]],[[T13]] 3383 ; MIPS32: slt [[T3]],[[T3]],[[T13]]
3384 ; MIPS32: srl [[T3]],[[T3]],0x18 3384 ; MIPS32: sll [[T3]],[[T3]],0x18
3385 ; MIPS32: sll [[T11]],[[T11]],0x8 3385 ; MIPS32: sll [[T11]],[[T11]],0x8
3386 ; MIPS32: srl [[T11]],[[T11]],0x8 3386 ; MIPS32: srl [[T11]],[[T11]],0x8
3387 ; MIPS32: or [[T3]],[[T3]],[[T11]] 3387 ; MIPS32: or [[T3]],[[T3]],[[T11]]
3388 ; MIPS32: move a0,[[T2]] 3388 ; MIPS32: move a0,[[T2]]
3389 ; MIPS32: move a1,[[T3]] 3389 ; MIPS32: move a1,[[T3]]
3390 } 3390 }
3391 3391
3392 define internal <16 x i1> @test_icmp_v16i8_sle(<16 x i8> %a, <16 x i8> %b) { 3392 define internal <16 x i1> @test_icmp_v16i8_sle(<16 x i8> %a, <16 x i8> %b) {
3393 entry: 3393 entry:
3394 %res = icmp sle <16 x i8> %a, %b 3394 %res = icmp sle <16 x i8> %a, %b
(...skipping 54 matching lines...) Expand 10 before | Expand all | Expand 10 after
3449 ; MIPS32: lui [[T4]],0xff00 3449 ; MIPS32: lui [[T4]],0xff00
3450 ; MIPS32: ori [[T4]],[[T4]],0xffff 3450 ; MIPS32: ori [[T4]],[[T4]],0xffff
3451 ; MIPS32: and [[T8]],[[T8]],[[T4]] 3451 ; MIPS32: and [[T8]],[[T8]],[[T4]]
3452 ; MIPS32: or [[T9]],[[T9]],[[T8]] 3452 ; MIPS32: or [[T9]],[[T9]],[[T8]]
3453 ; MIPS32: srl [[T10:.*]],a0,0x18 3453 ; MIPS32: srl [[T10:.*]],a0,0x18
3454 ; MIPS32: srl [[T0]],[[T0]],0x18 3454 ; MIPS32: srl [[T0]],[[T0]],0x18
3455 ; MIPS32: sll [[T10]],[[T10]],0x18 3455 ; MIPS32: sll [[T10]],[[T10]],0x18
3456 ; MIPS32: sll [[T0]],[[T0]],0x18 3456 ; MIPS32: sll [[T0]],[[T0]],0x18
3457 ; MIPS32: slt [[T0]],[[T0]],[[T10]] 3457 ; MIPS32: slt [[T0]],[[T0]],[[T10]]
3458 ; MIPS32: xori [[T0]],[[T0]],0x1 3458 ; MIPS32: xori [[T0]],[[T0]],0x1
3459 ; MIPS32: srl [[T0]],[[T0]],0x18 3459 ; MIPS32: sll [[T0]],[[T0]],0x18
3460 ; MIPS32: sll [[T9]],[[T9]],0x8 3460 ; MIPS32: sll [[T9]],[[T9]],0x8
3461 ; MIPS32: srl [[T9]],[[T9]],0x8 3461 ; MIPS32: srl [[T9]],[[T9]],0x8
3462 ; MIPS32: or v0,[[T0]],[[T9]] 3462 ; MIPS32: or v0,[[T0]],[[T9]]
3463 ; MIPS32: move [[T10]],a1 3463 ; MIPS32: move [[T10]],a1
3464 ; MIPS32: andi [[T10]],[[T10]],0xff 3464 ; MIPS32: andi [[T10]],[[T10]],0xff
3465 ; MIPS32: move [[T4]],[[T1]] 3465 ; MIPS32: move [[T4]],[[T1]]
3466 ; MIPS32: andi [[T4]],[[T4]],0xff 3466 ; MIPS32: andi [[T4]],[[T4]],0xff
3467 ; MIPS32: sll [[T10]],[[T10]],0x18 3467 ; MIPS32: sll [[T10]],[[T10]],0x18
3468 ; MIPS32: sll [[T4]],[[T4]],0x18 3468 ; MIPS32: sll [[T4]],[[T4]],0x18
3469 ; MIPS32: slt [[T4]],[[T4]],[[T10]] 3469 ; MIPS32: slt [[T4]],[[T4]],[[T10]]
(...skipping 33 matching lines...) Expand 10 before | Expand all | Expand 10 after
3503 ; MIPS32: lui [[T10]],0xff00 3503 ; MIPS32: lui [[T10]],0xff00
3504 ; MIPS32: ori [[T10]],[[T10]],0xffff 3504 ; MIPS32: ori [[T10]],[[T10]],0xffff
3505 ; MIPS32: and [[T5]],[[T5]],[[T10]] 3505 ; MIPS32: and [[T5]],[[T5]],[[T10]]
3506 ; MIPS32: or [[T4]],[[T4]],[[T5]] 3506 ; MIPS32: or [[T4]],[[T4]],[[T5]]
3507 ; MIPS32: srl [[T11:.*]],a1,0x18 3507 ; MIPS32: srl [[T11:.*]],a1,0x18
3508 ; MIPS32: srl [[T1]],[[T1]],0x18 3508 ; MIPS32: srl [[T1]],[[T1]],0x18
3509 ; MIPS32: sll [[T11]],[[T11]],0x18 3509 ; MIPS32: sll [[T11]],[[T11]],0x18
3510 ; MIPS32: sll [[T1]],[[T1]],0x18 3510 ; MIPS32: sll [[T1]],[[T1]],0x18
3511 ; MIPS32: slt [[T1]],[[T1]],[[T11]] 3511 ; MIPS32: slt [[T1]],[[T1]],[[T11]]
3512 ; MIPS32: xori [[T1]],[[T1]],0x1 3512 ; MIPS32: xori [[T1]],[[T1]],0x1
3513 ; MIPS32: srl [[T1]],[[T1]],0x18 3513 ; MIPS32: sll [[T1]],[[T1]],0x18
3514 ; MIPS32: sll [[T4]],[[T4]],0x8 3514 ; MIPS32: sll [[T4]],[[T4]],0x8
3515 ; MIPS32: srl [[T4]],[[T4]],0x8 3515 ; MIPS32: srl [[T4]],[[T4]],0x8
3516 ; MIPS32: or v1,[[T1]],[[T4]] 3516 ; MIPS32: or v1,[[T1]],[[T4]]
3517 ; MIPS32: move [[T10]],a2 3517 ; MIPS32: move [[T10]],a2
3518 ; MIPS32: andi [[T10]],[[T10]],0xff 3518 ; MIPS32: andi [[T10]],[[T10]],0xff
3519 ; MIPS32: move [[T11]],[[T2]] 3519 ; MIPS32: move [[T11]],[[T2]]
3520 ; MIPS32: andi [[T11]],[[T11]],0xff 3520 ; MIPS32: andi [[T11]],[[T11]],0xff
3521 ; MIPS32: sll [[T10]],[[T10]],0x18 3521 ; MIPS32: sll [[T10]],[[T10]],0x18
3522 ; MIPS32: sll [[T11]],[[T11]],0x18 3522 ; MIPS32: sll [[T11]],[[T11]],0x18
3523 ; MIPS32: slt [[T11]],[[T11]],[[T10]] 3523 ; MIPS32: slt [[T11]],[[T11]],[[T10]]
(...skipping 33 matching lines...) Expand 10 before | Expand all | Expand 10 after
3557 ; MIPS32: lui [[T10]],0xff00 3557 ; MIPS32: lui [[T10]],0xff00
3558 ; MIPS32: ori [[T10]],[[T10]],0xffff 3558 ; MIPS32: ori [[T10]],[[T10]],0xffff
3559 ; MIPS32: and [[T4]],[[T4]],[[T10]] 3559 ; MIPS32: and [[T4]],[[T4]],[[T10]]
3560 ; MIPS32: or [[T11]],[[T11]],[[T4]] 3560 ; MIPS32: or [[T11]],[[T11]],[[T4]]
3561 ; MIPS32: srl [[T12:.*]],a2,0x18 3561 ; MIPS32: srl [[T12:.*]],a2,0x18
3562 ; MIPS32: srl [[T2]],[[T2]],0x18 3562 ; MIPS32: srl [[T2]],[[T2]],0x18
3563 ; MIPS32: sll [[T12]],[[T12]],0x18 3563 ; MIPS32: sll [[T12]],[[T12]],0x18
3564 ; MIPS32: sll [[T2]],[[T2]],0x18 3564 ; MIPS32: sll [[T2]],[[T2]],0x18
3565 ; MIPS32: slt [[T2]],[[T2]],[[T12]] 3565 ; MIPS32: slt [[T2]],[[T2]],[[T12]]
3566 ; MIPS32: xori [[T2]],[[T2]],0x1 3566 ; MIPS32: xori [[T2]],[[T2]],0x1
3567 ; MIPS32: srl [[T2]],[[T2]],0x18 3567 ; MIPS32: sll [[T2]],[[T2]],0x18
3568 ; MIPS32: sll [[T11]],[[T11]],0x8 3568 ; MIPS32: sll [[T11]],[[T11]],0x8
3569 ; MIPS32: srl [[T11]],[[T11]],0x8 3569 ; MIPS32: srl [[T11]],[[T11]],0x8
3570 ; MIPS32: or [[T2]],[[T2]],[[T11]] 3570 ; MIPS32: or [[T2]],[[T2]],[[T11]]
3571 ; MIPS32: move [[T10]],a3 3571 ; MIPS32: move [[T10]],a3
3572 ; MIPS32: andi [[T10]],[[T10]],0xff 3572 ; MIPS32: andi [[T10]],[[T10]],0xff
3573 ; MIPS32: move [[T11]],[[T3]] 3573 ; MIPS32: move [[T11]],[[T3]]
3574 ; MIPS32: andi [[T11]],[[T11]],0xff 3574 ; MIPS32: andi [[T11]],[[T11]],0xff
3575 ; MIPS32: sll [[T10]],[[T10]],0x18 3575 ; MIPS32: sll [[T10]],[[T10]],0x18
3576 ; MIPS32: sll [[T11]],[[T11]],0x18 3576 ; MIPS32: sll [[T11]],[[T11]],0x18
3577 ; MIPS32: slt [[T11]],[[T11]],[[T10]] 3577 ; MIPS32: slt [[T11]],[[T11]],[[T10]]
(...skipping 33 matching lines...) Expand 10 before | Expand all | Expand 10 after
3611 ; MIPS32: lui [[T10]],0xff00 3611 ; MIPS32: lui [[T10]],0xff00
3612 ; MIPS32: ori [[T10]],[[T10]],0xffff 3612 ; MIPS32: ori [[T10]],[[T10]],0xffff
3613 ; MIPS32: and [[T12]],[[T12]],[[T10]] 3613 ; MIPS32: and [[T12]],[[T12]],[[T10]]
3614 ; MIPS32: or [[T11]],[[T11]],[[T12]] 3614 ; MIPS32: or [[T11]],[[T11]],[[T12]]
3615 ; MIPS32: srl [[T13:.*]],a3,0x18 3615 ; MIPS32: srl [[T13:.*]],a3,0x18
3616 ; MIPS32: srl [[T3]],[[T3]],0x18 3616 ; MIPS32: srl [[T3]],[[T3]],0x18
3617 ; MIPS32: sll [[T13]],[[T13]],0x18 3617 ; MIPS32: sll [[T13]],[[T13]],0x18
3618 ; MIPS32: sll [[T3]],[[T3]],0x18 3618 ; MIPS32: sll [[T3]],[[T3]],0x18
3619 ; MIPS32: slt [[T3]],[[T3]],[[T13]] 3619 ; MIPS32: slt [[T3]],[[T3]],[[T13]]
3620 ; MIPS32: xori [[T3]],[[T3]],0x1 3620 ; MIPS32: xori [[T3]],[[T3]],0x1
3621 ; MIPS32: srl [[T3]],[[T3]],0x18 3621 ; MIPS32: sll [[T3]],[[T3]],0x18
3622 ; MIPS32: sll [[T11]],[[T11]],0x8 3622 ; MIPS32: sll [[T11]],[[T11]],0x8
3623 ; MIPS32: srl [[T11]],[[T11]],0x8 3623 ; MIPS32: srl [[T11]],[[T11]],0x8
3624 ; MIPS32: or [[T3]],[[T3]],[[T11]] 3624 ; MIPS32: or [[T3]],[[T3]],[[T11]]
3625 ; MIPS32: move a0,[[T2]] 3625 ; MIPS32: move a0,[[T2]]
3626 ; MIPS32: move a1,[[T3]] 3626 ; MIPS32: move a1,[[T3]]
3627 } 3627 }
3628 3628
3629 define internal <16 x i1> @test_icmp_v16i8_slt(<16 x i8> %a, <16 x i8> %b) { 3629 define internal <16 x i1> @test_icmp_v16i8_slt(<16 x i8> %a, <16 x i8> %b) {
3630 entry: 3630 entry:
3631 %res = icmp slt <16 x i8> %a, %b 3631 %res = icmp slt <16 x i8> %a, %b
(...skipping 49 matching lines...) Expand 10 before | Expand all | Expand 10 after
3681 ; MIPS32: sll [[T8]],[[T8]],0x10 3681 ; MIPS32: sll [[T8]],[[T8]],0x10
3682 ; MIPS32: lui [[T9]],0xff00 3682 ; MIPS32: lui [[T9]],0xff00
3683 ; MIPS32: ori [[T9]],[[T9]],0xffff 3683 ; MIPS32: ori [[T9]],[[T9]],0xffff
3684 ; MIPS32: and [[T4]],[[T4]],[[T9]] 3684 ; MIPS32: and [[T4]],[[T4]],[[T9]]
3685 ; MIPS32: or [[T8]],[[T8]],[[T4]] 3685 ; MIPS32: or [[T8]],[[T8]],[[T4]]
3686 ; MIPS32: srl [[T10:.*]],a0,0x18 3686 ; MIPS32: srl [[T10:.*]],a0,0x18
3687 ; MIPS32: srl [[T0]],[[T0]],0x18 3687 ; MIPS32: srl [[T0]],[[T0]],0x18
3688 ; MIPS32: sll [[T10]],[[T10]],0x18 3688 ; MIPS32: sll [[T10]],[[T10]],0x18
3689 ; MIPS32: sll [[T0]],[[T0]],0x18 3689 ; MIPS32: sll [[T0]],[[T0]],0x18
3690 ; MIPS32: slt [[T10]],[[T10]],[[T0]] 3690 ; MIPS32: slt [[T10]],[[T10]],[[T0]]
3691 ; MIPS32: srl [[T10]],[[T10]],0x18 3691 ; MIPS32: sll [[T10]],[[T10]],0x18
3692 ; MIPS32: sll [[T8]],[[T8]],0x8 3692 ; MIPS32: sll [[T8]],[[T8]],0x8
3693 ; MIPS32: srl [[T8]],[[T8]],0x8 3693 ; MIPS32: srl [[T8]],[[T8]],0x8
3694 ; MIPS32: or [[T10]],[[T10]],[[T8]] 3694 ; MIPS32: or [[T10]],[[T10]],[[T8]]
3695 ; MIPS32: move [[T0]],a1 3695 ; MIPS32: move [[T0]],a1
3696 ; MIPS32: andi [[T0]],[[T0]],0xff 3696 ; MIPS32: andi [[T0]],[[T0]],0xff
3697 ; MIPS32: move [[T4]],[[T1]] 3697 ; MIPS32: move [[T4]],[[T1]]
3698 ; MIPS32: andi [[T4]],[[T4]],0xff 3698 ; MIPS32: andi [[T4]],[[T4]],0xff
3699 ; MIPS32: sll [[T0]],[[T0]],0x18 3699 ; MIPS32: sll [[T0]],[[T0]],0x18
3700 ; MIPS32: sll [[T4]],[[T4]],0x18 3700 ; MIPS32: sll [[T4]],[[T4]],0x18
3701 ; MIPS32: slt [[T0]],[[T0]],[[T4]] 3701 ; MIPS32: slt [[T0]],[[T0]],[[T4]]
(...skipping 29 matching lines...) Expand all
3731 ; MIPS32: sll [[T0]],[[T0]],0x10 3731 ; MIPS32: sll [[T0]],[[T0]],0x10
3732 ; MIPS32: lui [[T5]],0xff00 3732 ; MIPS32: lui [[T5]],0xff00
3733 ; MIPS32: ori [[T5]],[[T5]],0xffff 3733 ; MIPS32: ori [[T5]],[[T5]],0xffff
3734 ; MIPS32: and [[T4]],[[T4]],[[T5]] 3734 ; MIPS32: and [[T4]],[[T4]],[[T5]]
3735 ; MIPS32: or [[T0]],[[T0]],[[T4]] 3735 ; MIPS32: or [[T0]],[[T0]],[[T4]]
3736 ; MIPS32: srl [[T11:.*]],a1,0x18 3736 ; MIPS32: srl [[T11:.*]],a1,0x18
3737 ; MIPS32: srl [[T1]],[[T1]],0x18 3737 ; MIPS32: srl [[T1]],[[T1]],0x18
3738 ; MIPS32: sll [[T11]],[[T11]],0x18 3738 ; MIPS32: sll [[T11]],[[T11]],0x18
3739 ; MIPS32: sll [[T1]],[[T1]],0x18 3739 ; MIPS32: sll [[T1]],[[T1]],0x18
3740 ; MIPS32: slt [[T11]],[[T11]],[[T1]] 3740 ; MIPS32: slt [[T11]],[[T11]],[[T1]]
3741 ; MIPS32: srl [[T11]],[[T11]],0x18 3741 ; MIPS32: sll [[T11]],[[T11]],0x18
3742 ; MIPS32: sll [[T0]],[[T0]],0x8 3742 ; MIPS32: sll [[T0]],[[T0]],0x8
3743 ; MIPS32: srl [[T0]],[[T0]],0x8 3743 ; MIPS32: srl [[T0]],[[T0]],0x8
3744 ; MIPS32: or [[T11]],[[T11]],[[T0]] 3744 ; MIPS32: or [[T11]],[[T11]],[[T0]]
3745 ; MIPS32: move [[T0]],a2 3745 ; MIPS32: move [[T0]],a2
3746 ; MIPS32: andi [[T0]],[[T0]],0xff 3746 ; MIPS32: andi [[T0]],[[T0]],0xff
3747 ; MIPS32: move [[T1]],[[T2]] 3747 ; MIPS32: move [[T1]],[[T2]]
3748 ; MIPS32: andi [[T1]],[[T1]],0xff 3748 ; MIPS32: andi [[T1]],[[T1]],0xff
3749 ; MIPS32: sll [[T0]],[[T0]],0x18 3749 ; MIPS32: sll [[T0]],[[T0]],0x18
3750 ; MIPS32: sll [[T1]],[[T1]],0x18 3750 ; MIPS32: sll [[T1]],[[T1]],0x18
3751 ; MIPS32: slt [[T0]],[[T0]],[[T1]] 3751 ; MIPS32: slt [[T0]],[[T0]],[[T1]]
(...skipping 29 matching lines...) Expand all
3781 ; MIPS32: sll [[T0]],[[T0]],0x10 3781 ; MIPS32: sll [[T0]],[[T0]],0x10
3782 ; MIPS32: lui [[T4]],0xff00 3782 ; MIPS32: lui [[T4]],0xff00
3783 ; MIPS32: ori [[T4]],[[T4]],0xffff 3783 ; MIPS32: ori [[T4]],[[T4]],0xffff
3784 ; MIPS32: and [[T1]],[[T1]],[[T4]] 3784 ; MIPS32: and [[T1]],[[T1]],[[T4]]
3785 ; MIPS32: or [[T0]],[[T0]],[[T1]] 3785 ; MIPS32: or [[T0]],[[T0]],[[T1]]
3786 ; MIPS32: srl [[T12:.*]],a2,0x18 3786 ; MIPS32: srl [[T12:.*]],a2,0x18
3787 ; MIPS32: srl [[T2]],[[T2]],0x18 3787 ; MIPS32: srl [[T2]],[[T2]],0x18
3788 ; MIPS32: sll [[T12]],[[T12]],0x18 3788 ; MIPS32: sll [[T12]],[[T12]],0x18
3789 ; MIPS32: sll [[T2]],[[T2]],0x18 3789 ; MIPS32: sll [[T2]],[[T2]],0x18
3790 ; MIPS32: slt [[T12]],[[T12]],[[T2]] 3790 ; MIPS32: slt [[T12]],[[T12]],[[T2]]
3791 ; MIPS32: srl [[T12]],[[T12]],0x18 3791 ; MIPS32: sll [[T12]],[[T12]],0x18
3792 ; MIPS32: sll [[T0]],[[T0]],0x8 3792 ; MIPS32: sll [[T0]],[[T0]],0x8
3793 ; MIPS32: srl [[T0]],[[T0]],0x8 3793 ; MIPS32: srl [[T0]],[[T0]],0x8
3794 ; MIPS32: or [[T12]],[[T12]],[[T0]] 3794 ; MIPS32: or [[T12]],[[T12]],[[T0]]
3795 ; MIPS32: move [[T0]],a3 3795 ; MIPS32: move [[T0]],a3
3796 ; MIPS32: andi [[T0]],[[T0]],0xff 3796 ; MIPS32: andi [[T0]],[[T0]],0xff
3797 ; MIPS32: move [[T1]],[[T3]] 3797 ; MIPS32: move [[T1]],[[T3]]
3798 ; MIPS32: andi [[T1]],[[T1]],0xff 3798 ; MIPS32: andi [[T1]],[[T1]],0xff
3799 ; MIPS32: sll [[T0]],[[T0]],0x18 3799 ; MIPS32: sll [[T0]],[[T0]],0x18
3800 ; MIPS32: sll [[T1]],[[T1]],0x18 3800 ; MIPS32: sll [[T1]],[[T1]],0x18
3801 ; MIPS32: slt [[T0]],[[T0]],[[T1]] 3801 ; MIPS32: slt [[T0]],[[T0]],[[T1]]
(...skipping 29 matching lines...) Expand all
3831 ; MIPS32: sll [[T0]],[[T0]],0x10 3831 ; MIPS32: sll [[T0]],[[T0]],0x10
3832 ; MIPS32: lui [[T2]],0xff00 3832 ; MIPS32: lui [[T2]],0xff00
3833 ; MIPS32: ori [[T2]],[[T2]],0xffff 3833 ; MIPS32: ori [[T2]],[[T2]],0xffff
3834 ; MIPS32: and [[T1]],[[T1]],[[T2]] 3834 ; MIPS32: and [[T1]],[[T1]],[[T2]]
3835 ; MIPS32: or [[T0]],[[T0]],[[T1]] 3835 ; MIPS32: or [[T0]],[[T0]],[[T1]]
3836 ; MIPS32: srl [[T13:.*]],a3,0x18 3836 ; MIPS32: srl [[T13:.*]],a3,0x18
3837 ; MIPS32: srl [[T3]],[[T3]],0x18 3837 ; MIPS32: srl [[T3]],[[T3]],0x18
3838 ; MIPS32: sll [[T13]],[[T13]],0x18 3838 ; MIPS32: sll [[T13]],[[T13]],0x18
3839 ; MIPS32: sll [[T3]],[[T3]],0x18 3839 ; MIPS32: sll [[T3]],[[T3]],0x18
3840 ; MIPS32: slt [[T13]],[[T13]],[[T3]] 3840 ; MIPS32: slt [[T13]],[[T13]],[[T3]]
3841 ; MIPS32: srl [[T13]],[[T13]],0x18 3841 ; MIPS32: sll [[T13]],[[T13]],0x18
3842 ; MIPS32: sll [[T0]],[[T0]],0x8 3842 ; MIPS32: sll [[T0]],[[T0]],0x8
3843 ; MIPS32: srl [[T0]],[[T0]],0x8 3843 ; MIPS32: srl [[T0]],[[T0]],0x8
3844 ; MIPS32: or [[T13]],[[T13]],[[T0]] 3844 ; MIPS32: or [[T13]],[[T13]],[[T0]]
3845 ; MIPS32: move v0,[[T10]] 3845 ; MIPS32: move v0,[[T10]]
3846 ; MIPS32: move v1,[[T11]] 3846 ; MIPS32: move v1,[[T11]]
3847 ; MIPS32: move a0,[[T12]] 3847 ; MIPS32: move a0,[[T12]]
3848 ; MIPS32: move a1,[[T13]] 3848 ; MIPS32: move a1,[[T13]]
3849 } 3849 }
3850 3850
3851 define internal <16 x i1> @test_icmp_v16i8_uge(<16 x i8> %a, <16 x i8> %b) { 3851 define internal <16 x i1> @test_icmp_v16i8_uge(<16 x i8> %a, <16 x i8> %b) {
(...skipping 57 matching lines...) Expand 10 before | Expand all | Expand 10 after
3909 ; MIPS32: lui [[T9]],0xff00 3909 ; MIPS32: lui [[T9]],0xff00
3910 ; MIPS32: ori [[T9]],[[T9]],0xffff 3910 ; MIPS32: ori [[T9]],[[T9]],0xffff
3911 ; MIPS32: and [[T4]],[[T4]],[[T9]] 3911 ; MIPS32: and [[T4]],[[T4]],[[T9]]
3912 ; MIPS32: or [[T8]],[[T8]],[[T4]] 3912 ; MIPS32: or [[T8]],[[T8]],[[T4]]
3913 ; MIPS32: srl [[T10:.*]],a0,0x18 3913 ; MIPS32: srl [[T10:.*]],a0,0x18
3914 ; MIPS32: srl [[T0]],[[T0]],0x18 3914 ; MIPS32: srl [[T0]],[[T0]],0x18
3915 ; MIPS32: sll [[T10]],[[T10]],0x18 3915 ; MIPS32: sll [[T10]],[[T10]],0x18
3916 ; MIPS32: sll [[T0]],[[T0]],0x18 3916 ; MIPS32: sll [[T0]],[[T0]],0x18
3917 ; MIPS32: sltu [[T10]],[[T10]],[[T0]] 3917 ; MIPS32: sltu [[T10]],[[T10]],[[T0]]
3918 ; MIPS32: xori [[T10]],[[T10]],0x1 3918 ; MIPS32: xori [[T10]],[[T10]],0x1
3919 ; MIPS32: srl [[T10]],[[T10]],0x18 3919 ; MIPS32: sll [[T10]],[[T10]],0x18
3920 ; MIPS32: sll [[T8]],[[T8]],0x8 3920 ; MIPS32: sll [[T8]],[[T8]],0x8
3921 ; MIPS32: srl [[T8]],[[T8]],0x8 3921 ; MIPS32: srl [[T8]],[[T8]],0x8
3922 ; MIPS32: or [[T10]],[[T10]],[[T8]] 3922 ; MIPS32: or [[T10]],[[T10]],[[T8]]
3923 ; MIPS32: move [[T0]],a1 3923 ; MIPS32: move [[T0]],a1
3924 ; MIPS32: andi [[T0]],[[T0]],0xff 3924 ; MIPS32: andi [[T0]],[[T0]],0xff
3925 ; MIPS32: move [[T4]],[[T1]] 3925 ; MIPS32: move [[T4]],[[T1]]
3926 ; MIPS32: andi [[T4]],[[T4]],0xff 3926 ; MIPS32: andi [[T4]],[[T4]],0xff
3927 ; MIPS32: sll [[T0]],[[T0]],0x18 3927 ; MIPS32: sll [[T0]],[[T0]],0x18
3928 ; MIPS32: sll [[T4]],[[T4]],0x18 3928 ; MIPS32: sll [[T4]],[[T4]],0x18
3929 ; MIPS32: sltu [[T0]],[[T0]],[[T4]] 3929 ; MIPS32: sltu [[T0]],[[T0]],[[T4]]
(...skipping 33 matching lines...) Expand 10 before | Expand all | Expand 10 after
3963 ; MIPS32: lui [[T5]],0xff00 3963 ; MIPS32: lui [[T5]],0xff00
3964 ; MIPS32: ori [[T5]],[[T5]],0xffff 3964 ; MIPS32: ori [[T5]],[[T5]],0xffff
3965 ; MIPS32: and [[T4]],[[T4]],[[T5]] 3965 ; MIPS32: and [[T4]],[[T4]],[[T5]]
3966 ; MIPS32: or [[T0]],[[T0]],[[T4]] 3966 ; MIPS32: or [[T0]],[[T0]],[[T4]]
3967 ; MIPS32: srl [[T11:.*]],a1,0x18 3967 ; MIPS32: srl [[T11:.*]],a1,0x18
3968 ; MIPS32: srl [[T1]],[[T1]],0x18 3968 ; MIPS32: srl [[T1]],[[T1]],0x18
3969 ; MIPS32: sll [[T11]],[[T11]],0x18 3969 ; MIPS32: sll [[T11]],[[T11]],0x18
3970 ; MIPS32: sll [[T1]],[[T1]],0x18 3970 ; MIPS32: sll [[T1]],[[T1]],0x18
3971 ; MIPS32: sltu [[T11]],[[T11]],[[T1]] 3971 ; MIPS32: sltu [[T11]],[[T11]],[[T1]]
3972 ; MIPS32: xori [[T11]],[[T11]],0x1 3972 ; MIPS32: xori [[T11]],[[T11]],0x1
3973 ; MIPS32: srl [[T11]],[[T11]],0x18 3973 ; MIPS32: sll [[T11]],[[T11]],0x18
3974 ; MIPS32: sll [[T0]],[[T0]],0x8 3974 ; MIPS32: sll [[T0]],[[T0]],0x8
3975 ; MIPS32: srl [[T0]],[[T0]],0x8 3975 ; MIPS32: srl [[T0]],[[T0]],0x8
3976 ; MIPS32: or [[T11]],[[T11]],[[T0]] 3976 ; MIPS32: or [[T11]],[[T11]],[[T0]]
3977 ; MIPS32: move [[T0]],a2 3977 ; MIPS32: move [[T0]],a2
3978 ; MIPS32: andi [[T0]],[[T0]],0xff 3978 ; MIPS32: andi [[T0]],[[T0]],0xff
3979 ; MIPS32: move [[T1]],[[T2]] 3979 ; MIPS32: move [[T1]],[[T2]]
3980 ; MIPS32: andi [[T1]],[[T1]],0xff 3980 ; MIPS32: andi [[T1]],[[T1]],0xff
3981 ; MIPS32: sll [[T0]],[[T0]],0x18 3981 ; MIPS32: sll [[T0]],[[T0]],0x18
3982 ; MIPS32: sll [[T1]],[[T1]],0x18 3982 ; MIPS32: sll [[T1]],[[T1]],0x18
3983 ; MIPS32: sltu [[T0]],[[T0]],[[T1]] 3983 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
(...skipping 33 matching lines...) Expand 10 before | Expand all | Expand 10 after
4017 ; MIPS32: lui [[T4]],0xff00 4017 ; MIPS32: lui [[T4]],0xff00
4018 ; MIPS32: ori [[T4]],[[T4]],0xffff 4018 ; MIPS32: ori [[T4]],[[T4]],0xffff
4019 ; MIPS32: and [[T1]],[[T1]],[[T4]] 4019 ; MIPS32: and [[T1]],[[T1]],[[T4]]
4020 ; MIPS32: or [[T0]],[[T0]],[[T1]] 4020 ; MIPS32: or [[T0]],[[T0]],[[T1]]
4021 ; MIPS32: srl [[T12:.*]],a2,0x18 4021 ; MIPS32: srl [[T12:.*]],a2,0x18
4022 ; MIPS32: srl [[T2]],[[T2]],0x18 4022 ; MIPS32: srl [[T2]],[[T2]],0x18
4023 ; MIPS32: sll [[T12]],[[T12]],0x18 4023 ; MIPS32: sll [[T12]],[[T12]],0x18
4024 ; MIPS32: sll [[T2]],[[T2]],0x18 4024 ; MIPS32: sll [[T2]],[[T2]],0x18
4025 ; MIPS32: sltu [[T12]],[[T12]],[[T2]] 4025 ; MIPS32: sltu [[T12]],[[T12]],[[T2]]
4026 ; MIPS32: xori [[T12]],[[T12]],0x1 4026 ; MIPS32: xori [[T12]],[[T12]],0x1
4027 ; MIPS32: srl [[T12]],[[T12]],0x18 4027 ; MIPS32: sll [[T12]],[[T12]],0x18
4028 ; MIPS32: sll [[T0]],[[T0]],0x8 4028 ; MIPS32: sll [[T0]],[[T0]],0x8
4029 ; MIPS32: srl [[T0]],[[T0]],0x8 4029 ; MIPS32: srl [[T0]],[[T0]],0x8
4030 ; MIPS32: or [[T12]],[[T12]],[[T0]] 4030 ; MIPS32: or [[T12]],[[T12]],[[T0]]
4031 ; MIPS32: move [[T0]],a3 4031 ; MIPS32: move [[T0]],a3
4032 ; MIPS32: andi [[T0]],[[T0]],0xff 4032 ; MIPS32: andi [[T0]],[[T0]],0xff
4033 ; MIPS32: move [[T1]],[[T3]] 4033 ; MIPS32: move [[T1]],[[T3]]
4034 ; MIPS32: andi [[T1]],[[T1]],0xff 4034 ; MIPS32: andi [[T1]],[[T1]],0xff
4035 ; MIPS32: sll [[T0]],[[T0]],0x18 4035 ; MIPS32: sll [[T0]],[[T0]],0x18
4036 ; MIPS32: sll [[T1]],[[T1]],0x18 4036 ; MIPS32: sll [[T1]],[[T1]],0x18
4037 ; MIPS32: sltu [[T0]],[[T0]],[[T1]] 4037 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
(...skipping 33 matching lines...) Expand 10 before | Expand all | Expand 10 after
4071 ; MIPS32: lui [[T2]],0xff00 4071 ; MIPS32: lui [[T2]],0xff00
4072 ; MIPS32: ori [[T2]],[[T2]],0xffff 4072 ; MIPS32: ori [[T2]],[[T2]],0xffff
4073 ; MIPS32: and [[T1]],[[T1]],[[T2]] 4073 ; MIPS32: and [[T1]],[[T1]],[[T2]]
4074 ; MIPS32: or [[T0]],[[T0]],[[T1]] 4074 ; MIPS32: or [[T0]],[[T0]],[[T1]]
4075 ; MIPS32: srl [[T13:.*]],a3,0x18 4075 ; MIPS32: srl [[T13:.*]],a3,0x18
4076 ; MIPS32: srl [[T3]],[[T3]],0x18 4076 ; MIPS32: srl [[T3]],[[T3]],0x18
4077 ; MIPS32: sll [[T13]],[[T13]],0x18 4077 ; MIPS32: sll [[T13]],[[T13]],0x18
4078 ; MIPS32: sll [[T3]],[[T3]],0x18 4078 ; MIPS32: sll [[T3]],[[T3]],0x18
4079 ; MIPS32: sltu [[T13]],[[T13]],[[T3]] 4079 ; MIPS32: sltu [[T13]],[[T13]],[[T3]]
4080 ; MIPS32: xori [[T13]],[[T13]],0x1 4080 ; MIPS32: xori [[T13]],[[T13]],0x1
4081 ; MIPS32: srl [[T13]],[[T13]],0x18 4081 ; MIPS32: sll [[T13]],[[T13]],0x18
4082 ; MIPS32: sll [[T0]],[[T0]],0x8 4082 ; MIPS32: sll [[T0]],[[T0]],0x8
4083 ; MIPS32: srl [[T0]],[[T0]],0x8 4083 ; MIPS32: srl [[T0]],[[T0]],0x8
4084 ; MIPS32: or [[T13]],[[T13]],[[T0]] 4084 ; MIPS32: or [[T13]],[[T13]],[[T0]]
4085 ; MIPS32: move v0,[[T10]] 4085 ; MIPS32: move v0,[[T10]]
4086 ; MIPS32: move v1,[[T11]] 4086 ; MIPS32: move v1,[[T11]]
4087 ; MIPS32: move a0,[[T12]] 4087 ; MIPS32: move a0,[[T12]]
4088 ; MIPS32: move a1,[[T13]] 4088 ; MIPS32: move a1,[[T13]]
4089 } 4089 }
4090 4090
4091 define internal <16 x i1> @test_icmp_v16i8_ugt(<16 x i8> %a, <16 x i8> %b) { 4091 define internal <16 x i1> @test_icmp_v16i8_ugt(<16 x i8> %a, <16 x i8> %b) {
(...skipping 52 matching lines...) Expand 10 before | Expand all | Expand 10 after
4144 ; MIPS32: sll [[T9]],[[T9]],0x10 4144 ; MIPS32: sll [[T9]],[[T9]],0x10
4145 ; MIPS32: lui [[T4]],0xff00 4145 ; MIPS32: lui [[T4]],0xff00
4146 ; MIPS32: ori [[T4]],[[T4]],0xffff 4146 ; MIPS32: ori [[T4]],[[T4]],0xffff
4147 ; MIPS32: and [[T8]],[[T8]],[[T4]] 4147 ; MIPS32: and [[T8]],[[T8]],[[T4]]
4148 ; MIPS32: or [[T9]],[[T9]],[[T8]] 4148 ; MIPS32: or [[T9]],[[T9]],[[T8]]
4149 ; MIPS32: srl [[T10:.*]],a0,0x18 4149 ; MIPS32: srl [[T10:.*]],a0,0x18
4150 ; MIPS32: srl [[T0]],[[T0]],0x18 4150 ; MIPS32: srl [[T0]],[[T0]],0x18
4151 ; MIPS32: sll [[T10]],[[T10]],0x18 4151 ; MIPS32: sll [[T10]],[[T10]],0x18
4152 ; MIPS32: sll [[T0]],[[T0]],0x18 4152 ; MIPS32: sll [[T0]],[[T0]],0x18
4153 ; MIPS32: sltu [[T0]],[[T0]],[[T10]] 4153 ; MIPS32: sltu [[T0]],[[T0]],[[T10]]
4154 ; MIPS32: srl [[T0]],[[T0]],0x18 4154 ; MIPS32: sll [[T0]],[[T0]],0x18
4155 ; MIPS32: sll [[T9]],[[T9]],0x8 4155 ; MIPS32: sll [[T9]],[[T9]],0x8
4156 ; MIPS32: srl [[T9]],[[T9]],0x8 4156 ; MIPS32: srl [[T9]],[[T9]],0x8
4157 ; MIPS32: or v0,[[T0]],[[T9]] 4157 ; MIPS32: or v0,[[T0]],[[T9]]
4158 ; MIPS32: move [[T10]],a1 4158 ; MIPS32: move [[T10]],a1
4159 ; MIPS32: andi [[T10]],[[T10]],0xff 4159 ; MIPS32: andi [[T10]],[[T10]],0xff
4160 ; MIPS32: move [[T4]],[[T1]] 4160 ; MIPS32: move [[T4]],[[T1]]
4161 ; MIPS32: andi [[T4]],[[T4]],0xff 4161 ; MIPS32: andi [[T4]],[[T4]],0xff
4162 ; MIPS32: sll [[T10]],[[T10]],0x18 4162 ; MIPS32: sll [[T10]],[[T10]],0x18
4163 ; MIPS32: sll [[T4]],[[T4]],0x18 4163 ; MIPS32: sll [[T4]],[[T4]],0x18
4164 ; MIPS32: sltu [[T4]],[[T4]],[[T10]] 4164 ; MIPS32: sltu [[T4]],[[T4]],[[T10]]
(...skipping 29 matching lines...) Expand all
4194 ; MIPS32: sll [[T4]],[[T4]],0x10 4194 ; MIPS32: sll [[T4]],[[T4]],0x10
4195 ; MIPS32: lui [[T10]],0xff00 4195 ; MIPS32: lui [[T10]],0xff00
4196 ; MIPS32: ori [[T10]],[[T10]],0xffff 4196 ; MIPS32: ori [[T10]],[[T10]],0xffff
4197 ; MIPS32: and [[T5]],[[T5]],[[T10]] 4197 ; MIPS32: and [[T5]],[[T5]],[[T10]]
4198 ; MIPS32: or [[T4]],[[T4]],[[T5]] 4198 ; MIPS32: or [[T4]],[[T4]],[[T5]]
4199 ; MIPS32: srl [[T11:.*]],a1,0x18 4199 ; MIPS32: srl [[T11:.*]],a1,0x18
4200 ; MIPS32: srl [[T1]],[[T1]],0x18 4200 ; MIPS32: srl [[T1]],[[T1]],0x18
4201 ; MIPS32: sll [[T11]],[[T11]],0x18 4201 ; MIPS32: sll [[T11]],[[T11]],0x18
4202 ; MIPS32: sll [[T1]],[[T1]],0x18 4202 ; MIPS32: sll [[T1]],[[T1]],0x18
4203 ; MIPS32: sltu [[T1]],[[T1]],[[T11]] 4203 ; MIPS32: sltu [[T1]],[[T1]],[[T11]]
4204 ; MIPS32: srl [[T1]],[[T1]],0x18 4204 ; MIPS32: sll [[T1]],[[T1]],0x18
4205 ; MIPS32: sll [[T4]],[[T4]],0x8 4205 ; MIPS32: sll [[T4]],[[T4]],0x8
4206 ; MIPS32: srl [[T4]],[[T4]],0x8 4206 ; MIPS32: srl [[T4]],[[T4]],0x8
4207 ; MIPS32: or v1,[[T1]],[[T4]] 4207 ; MIPS32: or v1,[[T1]],[[T4]]
4208 ; MIPS32: move [[T10]],a2 4208 ; MIPS32: move [[T10]],a2
4209 ; MIPS32: andi [[T10]],[[T10]],0xff 4209 ; MIPS32: andi [[T10]],[[T10]],0xff
4210 ; MIPS32: move [[T11]],[[T2]] 4210 ; MIPS32: move [[T11]],[[T2]]
4211 ; MIPS32: andi [[T11]],[[T11]],0xff 4211 ; MIPS32: andi [[T11]],[[T11]],0xff
4212 ; MIPS32: sll [[T10]],[[T10]],0x18 4212 ; MIPS32: sll [[T10]],[[T10]],0x18
4213 ; MIPS32: sll [[T11]],[[T11]],0x18 4213 ; MIPS32: sll [[T11]],[[T11]],0x18
4214 ; MIPS32: sltu [[T11]],[[T11]],[[T10]] 4214 ; MIPS32: sltu [[T11]],[[T11]],[[T10]]
(...skipping 29 matching lines...) Expand all
4244 ; MIPS32: sll [[T11]],[[T11]],0x10 4244 ; MIPS32: sll [[T11]],[[T11]],0x10
4245 ; MIPS32: lui [[T10]],0xff00 4245 ; MIPS32: lui [[T10]],0xff00
4246 ; MIPS32: ori [[T10]],[[T10]],0xffff 4246 ; MIPS32: ori [[T10]],[[T10]],0xffff
4247 ; MIPS32: and [[T4]],[[T4]],[[T10]] 4247 ; MIPS32: and [[T4]],[[T4]],[[T10]]
4248 ; MIPS32: or [[T11]],[[T11]],[[T4]] 4248 ; MIPS32: or [[T11]],[[T11]],[[T4]]
4249 ; MIPS32: srl [[T12:.*]],a2,0x18 4249 ; MIPS32: srl [[T12:.*]],a2,0x18
4250 ; MIPS32: srl [[T2]],[[T2]],0x18 4250 ; MIPS32: srl [[T2]],[[T2]],0x18
4251 ; MIPS32: sll [[T12]],[[T12]],0x18 4251 ; MIPS32: sll [[T12]],[[T12]],0x18
4252 ; MIPS32: sll [[T2]],[[T2]],0x18 4252 ; MIPS32: sll [[T2]],[[T2]],0x18
4253 ; MIPS32: sltu [[T2]],[[T2]],[[T12]] 4253 ; MIPS32: sltu [[T2]],[[T2]],[[T12]]
4254 ; MIPS32: srl [[T2]],[[T2]],0x18 4254 ; MIPS32: sll [[T2]],[[T2]],0x18
4255 ; MIPS32: sll [[T11]],[[T11]],0x8 4255 ; MIPS32: sll [[T11]],[[T11]],0x8
4256 ; MIPS32: srl [[T11]],[[T11]],0x8 4256 ; MIPS32: srl [[T11]],[[T11]],0x8
4257 ; MIPS32: or [[T2]],[[T2]],[[T11]] 4257 ; MIPS32: or [[T2]],[[T2]],[[T11]]
4258 ; MIPS32: move [[T10]],a3 4258 ; MIPS32: move [[T10]],a3
4259 ; MIPS32: andi [[T10]],[[T10]],0xff 4259 ; MIPS32: andi [[T10]],[[T10]],0xff
4260 ; MIPS32: move [[T11]],[[T3]] 4260 ; MIPS32: move [[T11]],[[T3]]
4261 ; MIPS32: andi [[T11]],[[T11]],0xff 4261 ; MIPS32: andi [[T11]],[[T11]],0xff
4262 ; MIPS32: sll [[T10]],[[T10]],0x18 4262 ; MIPS32: sll [[T10]],[[T10]],0x18
4263 ; MIPS32: sll [[T11]],[[T11]],0x18 4263 ; MIPS32: sll [[T11]],[[T11]],0x18
4264 ; MIPS32: sltu [[T11]],[[T11]],[[T10]] 4264 ; MIPS32: sltu [[T11]],[[T11]],[[T10]]
(...skipping 29 matching lines...) Expand all
4294 ; MIPS32: sll [[T11]],[[T11]],0x10 4294 ; MIPS32: sll [[T11]],[[T11]],0x10
4295 ; MIPS32: lui [[T10]],0xff00 4295 ; MIPS32: lui [[T10]],0xff00
4296 ; MIPS32: ori [[T10]],[[T10]],0xffff 4296 ; MIPS32: ori [[T10]],[[T10]],0xffff
4297 ; MIPS32: and [[T12]],[[T12]],[[T10]] 4297 ; MIPS32: and [[T12]],[[T12]],[[T10]]
4298 ; MIPS32: or [[T11]],[[T11]],[[T12]] 4298 ; MIPS32: or [[T11]],[[T11]],[[T12]]
4299 ; MIPS32: srl [[T13:.*]],a3,0x18 4299 ; MIPS32: srl [[T13:.*]],a3,0x18
4300 ; MIPS32: srl [[T3]],[[T3]],0x18 4300 ; MIPS32: srl [[T3]],[[T3]],0x18
4301 ; MIPS32: sll [[T13]],[[T13]],0x18 4301 ; MIPS32: sll [[T13]],[[T13]],0x18
4302 ; MIPS32: sll [[T3]],[[T3]],0x18 4302 ; MIPS32: sll [[T3]],[[T3]],0x18
4303 ; MIPS32: sltu [[T3]],[[T3]],[[T13]] 4303 ; MIPS32: sltu [[T3]],[[T3]],[[T13]]
4304 ; MIPS32: srl [[T3]],[[T3]],0x18 4304 ; MIPS32: sll [[T3]],[[T3]],0x18
4305 ; MIPS32: sll [[T11]],[[T11]],0x8 4305 ; MIPS32: sll [[T11]],[[T11]],0x8
4306 ; MIPS32: srl [[T11]],[[T11]],0x8 4306 ; MIPS32: srl [[T11]],[[T11]],0x8
4307 ; MIPS32: or [[T3]],[[T3]],[[T11]] 4307 ; MIPS32: or [[T3]],[[T3]],[[T11]]
4308 ; MIPS32: move a0,[[T2]] 4308 ; MIPS32: move a0,[[T2]]
4309 ; MIPS32: move a1,[[T3]] 4309 ; MIPS32: move a1,[[T3]]
4310 } 4310 }
4311 4311
4312 define internal <16 x i1> @test_icmp_v16i8_ule(<16 x i8> %a, <16 x i8> %b) { 4312 define internal <16 x i1> @test_icmp_v16i8_ule(<16 x i8> %a, <16 x i8> %b) {
4313 entry: 4313 entry:
4314 %res = icmp ule <16 x i8> %a, %b 4314 %res = icmp ule <16 x i8> %a, %b
(...skipping 55 matching lines...) Expand 10 before | Expand all | Expand 10 after
4370 ; MIPS32: lui [[T4]],0xff00 4370 ; MIPS32: lui [[T4]],0xff00
4371 ; MIPS32: ori [[T4]],[[T4]],0xffff 4371 ; MIPS32: ori [[T4]],[[T4]],0xffff
4372 ; MIPS32: and [[T8]],[[T8]],[[T4]] 4372 ; MIPS32: and [[T8]],[[T8]],[[T4]]
4373 ; MIPS32: or [[T9]],[[T9]],[[T8]] 4373 ; MIPS32: or [[T9]],[[T9]],[[T8]]
4374 ; MIPS32: srl [[T10:.*]],a0,0x18 4374 ; MIPS32: srl [[T10:.*]],a0,0x18
4375 ; MIPS32: srl [[T0]],[[T0]],0x18 4375 ; MIPS32: srl [[T0]],[[T0]],0x18
4376 ; MIPS32: sll [[T10]],[[T10]],0x18 4376 ; MIPS32: sll [[T10]],[[T10]],0x18
4377 ; MIPS32: sll [[T0]],[[T0]],0x18 4377 ; MIPS32: sll [[T0]],[[T0]],0x18
4378 ; MIPS32: sltu [[T0]],[[T0]],[[T10]] 4378 ; MIPS32: sltu [[T0]],[[T0]],[[T10]]
4379 ; MIPS32: xori [[T0]],[[T0]],0x1 4379 ; MIPS32: xori [[T0]],[[T0]],0x1
4380 ; MIPS32: srl [[T0]],[[T0]],0x18 4380 ; MIPS32: sll [[T0]],[[T0]],0x18
4381 ; MIPS32: sll [[T9]],[[T9]],0x8 4381 ; MIPS32: sll [[T9]],[[T9]],0x8
4382 ; MIPS32: srl [[T9]],[[T9]],0x8 4382 ; MIPS32: srl [[T9]],[[T9]],0x8
4383 ; MIPS32: or v0,[[T0]],[[T9]] 4383 ; MIPS32: or v0,[[T0]],[[T9]]
4384 ; MIPS32: move [[T10]],a1 4384 ; MIPS32: move [[T10]],a1
4385 ; MIPS32: andi [[T10]],[[T10]],0xff 4385 ; MIPS32: andi [[T10]],[[T10]],0xff
4386 ; MIPS32: move [[T4]],[[T1]] 4386 ; MIPS32: move [[T4]],[[T1]]
4387 ; MIPS32: andi [[T4]],[[T4]],0xff 4387 ; MIPS32: andi [[T4]],[[T4]],0xff
4388 ; MIPS32: sll [[T10]],[[T10]],0x18 4388 ; MIPS32: sll [[T10]],[[T10]],0x18
4389 ; MIPS32: sll [[T4]],[[T4]],0x18 4389 ; MIPS32: sll [[T4]],[[T4]],0x18
4390 ; MIPS32: sltu [[T4]],[[T4]],[[T10]] 4390 ; MIPS32: sltu [[T4]],[[T4]],[[T10]]
(...skipping 33 matching lines...) Expand 10 before | Expand all | Expand 10 after
4424 ; MIPS32: lui [[T10]],0xff00 4424 ; MIPS32: lui [[T10]],0xff00
4425 ; MIPS32: ori [[T10]],[[T10]],0xffff 4425 ; MIPS32: ori [[T10]],[[T10]],0xffff
4426 ; MIPS32: and [[T5]],[[T5]],[[T10]] 4426 ; MIPS32: and [[T5]],[[T5]],[[T10]]
4427 ; MIPS32: or [[T4]],[[T4]],[[T5]] 4427 ; MIPS32: or [[T4]],[[T4]],[[T5]]
4428 ; MIPS32: srl [[T11:.*]],a1,0x18 4428 ; MIPS32: srl [[T11:.*]],a1,0x18
4429 ; MIPS32: srl [[T1]],[[T1]],0x18 4429 ; MIPS32: srl [[T1]],[[T1]],0x18
4430 ; MIPS32: sll [[T11]],[[T11]],0x18 4430 ; MIPS32: sll [[T11]],[[T11]],0x18
4431 ; MIPS32: sll [[T1]],[[T1]],0x18 4431 ; MIPS32: sll [[T1]],[[T1]],0x18
4432 ; MIPS32: sltu [[T1]],[[T1]],[[T11]] 4432 ; MIPS32: sltu [[T1]],[[T1]],[[T11]]
4433 ; MIPS32: xori [[T1]],[[T1]],0x1 4433 ; MIPS32: xori [[T1]],[[T1]],0x1
4434 ; MIPS32: srl [[T1]],[[T1]],0x18 4434 ; MIPS32: sll [[T1]],[[T1]],0x18
4435 ; MIPS32: sll [[T4]],[[T4]],0x8 4435 ; MIPS32: sll [[T4]],[[T4]],0x8
4436 ; MIPS32: srl [[T4]],[[T4]],0x8 4436 ; MIPS32: srl [[T4]],[[T4]],0x8
4437 ; MIPS32: or v1,[[T1]],[[T4]] 4437 ; MIPS32: or v1,[[T1]],[[T4]]
4438 ; MIPS32: move [[T10]],a2 4438 ; MIPS32: move [[T10]],a2
4439 ; MIPS32: andi [[T10]],[[T10]],0xff 4439 ; MIPS32: andi [[T10]],[[T10]],0xff
4440 ; MIPS32: move [[T11]],[[T2]] 4440 ; MIPS32: move [[T11]],[[T2]]
4441 ; MIPS32: andi [[T11]],[[T11]],0xff 4441 ; MIPS32: andi [[T11]],[[T11]],0xff
4442 ; MIPS32: sll [[T10]],[[T10]],0x18 4442 ; MIPS32: sll [[T10]],[[T10]],0x18
4443 ; MIPS32: sll [[T11]],[[T11]],0x18 4443 ; MIPS32: sll [[T11]],[[T11]],0x18
4444 ; MIPS32: sltu [[T11]],[[T11]],[[T10]] 4444 ; MIPS32: sltu [[T11]],[[T11]],[[T10]]
(...skipping 33 matching lines...) Expand 10 before | Expand all | Expand 10 after
4478 ; MIPS32: lui [[T10]],0xff00 4478 ; MIPS32: lui [[T10]],0xff00
4479 ; MIPS32: ori [[T10]],[[T10]],0xffff 4479 ; MIPS32: ori [[T10]],[[T10]],0xffff
4480 ; MIPS32: and [[T4]],[[T4]],[[T10]] 4480 ; MIPS32: and [[T4]],[[T4]],[[T10]]
4481 ; MIPS32: or [[T11]],[[T11]],[[T4]] 4481 ; MIPS32: or [[T11]],[[T11]],[[T4]]
4482 ; MIPS32: srl [[T12:.*]],a2,0x18 4482 ; MIPS32: srl [[T12:.*]],a2,0x18
4483 ; MIPS32: srl [[T2]],[[T2]],0x18 4483 ; MIPS32: srl [[T2]],[[T2]],0x18
4484 ; MIPS32: sll [[T12]],[[T12]],0x18 4484 ; MIPS32: sll [[T12]],[[T12]],0x18
4485 ; MIPS32: sll [[T2]],[[T2]],0x18 4485 ; MIPS32: sll [[T2]],[[T2]],0x18
4486 ; MIPS32: sltu [[T2]],[[T2]],[[T12]] 4486 ; MIPS32: sltu [[T2]],[[T2]],[[T12]]
4487 ; MIPS32: xori [[T2]],[[T2]],0x1 4487 ; MIPS32: xori [[T2]],[[T2]],0x1
4488 ; MIPS32: srl [[T2]],[[T2]],0x18 4488 ; MIPS32: sll [[T2]],[[T2]],0x18
4489 ; MIPS32: sll [[T11]],[[T11]],0x8 4489 ; MIPS32: sll [[T11]],[[T11]],0x8
4490 ; MIPS32: srl [[T11]],[[T11]],0x8 4490 ; MIPS32: srl [[T11]],[[T11]],0x8
4491 ; MIPS32: or [[T2]],[[T2]],[[T11]] 4491 ; MIPS32: or [[T2]],[[T2]],[[T11]]
4492 ; MIPS32: move [[T10]],a3 4492 ; MIPS32: move [[T10]],a3
4493 ; MIPS32: andi [[T10]],[[T10]],0xff 4493 ; MIPS32: andi [[T10]],[[T10]],0xff
4494 ; MIPS32: move [[T11]],[[T3]] 4494 ; MIPS32: move [[T11]],[[T3]]
4495 ; MIPS32: andi [[T11]],[[T11]],0xff 4495 ; MIPS32: andi [[T11]],[[T11]],0xff
4496 ; MIPS32: sll [[T10]],[[T10]],0x18 4496 ; MIPS32: sll [[T10]],[[T10]],0x18
4497 ; MIPS32: sll [[T11]],[[T11]],0x18 4497 ; MIPS32: sll [[T11]],[[T11]],0x18
4498 ; MIPS32: sltu [[T11]],[[T11]],[[T10]] 4498 ; MIPS32: sltu [[T11]],[[T11]],[[T10]]
(...skipping 33 matching lines...) Expand 10 before | Expand all | Expand 10 after
4532 ; MIPS32: lui [[T10]],0xff00 4532 ; MIPS32: lui [[T10]],0xff00
4533 ; MIPS32: ori [[T10]],[[T10]],0xffff 4533 ; MIPS32: ori [[T10]],[[T10]],0xffff
4534 ; MIPS32: and [[T12]],[[T12]],[[T10]] 4534 ; MIPS32: and [[T12]],[[T12]],[[T10]]
4535 ; MIPS32: or [[T11]],[[T11]],[[T12]] 4535 ; MIPS32: or [[T11]],[[T11]],[[T12]]
4536 ; MIPS32: srl [[T13:.*]],a3,0x18 4536 ; MIPS32: srl [[T13:.*]],a3,0x18
4537 ; MIPS32: srl [[T3]],[[T3]],0x18 4537 ; MIPS32: srl [[T3]],[[T3]],0x18
4538 ; MIPS32: sll [[T13]],[[T13]],0x18 4538 ; MIPS32: sll [[T13]],[[T13]],0x18
4539 ; MIPS32: sll [[T3]],[[T3]],0x18 4539 ; MIPS32: sll [[T3]],[[T3]],0x18
4540 ; MIPS32: sltu [[T3]],[[T3]],[[T13]] 4540 ; MIPS32: sltu [[T3]],[[T3]],[[T13]]
4541 ; MIPS32: xori [[T3]],[[T3]],0x1 4541 ; MIPS32: xori [[T3]],[[T3]],0x1
4542 ; MIPS32: srl [[T3]],[[T3]],0x18 4542 ; MIPS32: sll [[T3]],[[T3]],0x18
4543 ; MIPS32: sll [[T11]],[[T11]],0x8 4543 ; MIPS32: sll [[T11]],[[T11]],0x8
4544 ; MIPS32: srl [[T11]],[[T11]],0x8 4544 ; MIPS32: srl [[T11]],[[T11]],0x8
4545 ; MIPS32: or [[T3]],[[T3]],[[T11]] 4545 ; MIPS32: or [[T3]],[[T3]],[[T11]]
4546 ; MIPS32: move a0,[[T2]] 4546 ; MIPS32: move a0,[[T2]]
4547 ; MIPS32: move a1,[[T3]] 4547 ; MIPS32: move a1,[[T3]]
4548 } 4548 }
4549 4549
4550 define internal <16 x i1> @test_icmp_v16i8_ult(<16 x i8> %a, <16 x i8> %b) { 4550 define internal <16 x i1> @test_icmp_v16i8_ult(<16 x i8> %a, <16 x i8> %b) {
4551 entry: 4551 entry:
4552 %res = icmp ult <16 x i8> %a, %b 4552 %res = icmp ult <16 x i8> %a, %b
(...skipping 50 matching lines...) Expand 10 before | Expand all | Expand 10 after
4603 ; MIPS32: sll [[T8]],[[T8]],0x10 4603 ; MIPS32: sll [[T8]],[[T8]],0x10
4604 ; MIPS32: lui [[T9]],0xff00 4604 ; MIPS32: lui [[T9]],0xff00
4605 ; MIPS32: ori [[T9]],[[T9]],0xffff 4605 ; MIPS32: ori [[T9]],[[T9]],0xffff
4606 ; MIPS32: and [[T4]],[[T4]],[[T9]] 4606 ; MIPS32: and [[T4]],[[T4]],[[T9]]
4607 ; MIPS32: or [[T8]],[[T8]],[[T4]] 4607 ; MIPS32: or [[T8]],[[T8]],[[T4]]
4608 ; MIPS32: srl [[T10:.*]],a0,0x18 4608 ; MIPS32: srl [[T10:.*]],a0,0x18
4609 ; MIPS32: srl [[T0]],[[T0]],0x18 4609 ; MIPS32: srl [[T0]],[[T0]],0x18
4610 ; MIPS32: sll [[T10]],[[T10]],0x18 4610 ; MIPS32: sll [[T10]],[[T10]],0x18
4611 ; MIPS32: sll [[T0]],[[T0]],0x18 4611 ; MIPS32: sll [[T0]],[[T0]],0x18
4612 ; MIPS32: sltu [[T10]],[[T10]],[[T0]] 4612 ; MIPS32: sltu [[T10]],[[T10]],[[T0]]
4613 ; MIPS32: srl [[T10]],[[T10]],0x18 4613 ; MIPS32: sll [[T10]],[[T10]],0x18
4614 ; MIPS32: sll [[T8]],[[T8]],0x8 4614 ; MIPS32: sll [[T8]],[[T8]],0x8
4615 ; MIPS32: srl [[T8]],[[T8]],0x8 4615 ; MIPS32: srl [[T8]],[[T8]],0x8
4616 ; MIPS32: or [[T10]],[[T10]],[[T8]] 4616 ; MIPS32: or [[T10]],[[T10]],[[T8]]
4617 ; MIPS32: move [[T0]],a1 4617 ; MIPS32: move [[T0]],a1
4618 ; MIPS32: andi [[T0]],[[T0]],0xff 4618 ; MIPS32: andi [[T0]],[[T0]],0xff
4619 ; MIPS32: move [[T4]],[[T1]] 4619 ; MIPS32: move [[T4]],[[T1]]
4620 ; MIPS32: andi [[T4]],[[T4]],0xff 4620 ; MIPS32: andi [[T4]],[[T4]],0xff
4621 ; MIPS32: sll [[T0]],[[T0]],0x18 4621 ; MIPS32: sll [[T0]],[[T0]],0x18
4622 ; MIPS32: sll [[T4]],[[T4]],0x18 4622 ; MIPS32: sll [[T4]],[[T4]],0x18
4623 ; MIPS32: sltu [[T0]],[[T0]],[[T4]] 4623 ; MIPS32: sltu [[T0]],[[T0]],[[T4]]
(...skipping 29 matching lines...) Expand all
4653 ; MIPS32: sll [[T0]],[[T0]],0x10 4653 ; MIPS32: sll [[T0]],[[T0]],0x10
4654 ; MIPS32: lui [[T5]],0xff00 4654 ; MIPS32: lui [[T5]],0xff00
4655 ; MIPS32: ori [[T5]],[[T5]],0xffff 4655 ; MIPS32: ori [[T5]],[[T5]],0xffff
4656 ; MIPS32: and [[T4]],[[T4]],[[T5]] 4656 ; MIPS32: and [[T4]],[[T4]],[[T5]]
4657 ; MIPS32: or [[T0]],[[T0]],[[T4]] 4657 ; MIPS32: or [[T0]],[[T0]],[[T4]]
4658 ; MIPS32: srl [[T11:.*]],a1,0x18 4658 ; MIPS32: srl [[T11:.*]],a1,0x18
4659 ; MIPS32: srl [[T1]],[[T1]],0x18 4659 ; MIPS32: srl [[T1]],[[T1]],0x18
4660 ; MIPS32: sll [[T11]],[[T11]],0x18 4660 ; MIPS32: sll [[T11]],[[T11]],0x18
4661 ; MIPS32: sll [[T1]],[[T1]],0x18 4661 ; MIPS32: sll [[T1]],[[T1]],0x18
4662 ; MIPS32: sltu [[T11]],[[T11]],[[T1]] 4662 ; MIPS32: sltu [[T11]],[[T11]],[[T1]]
4663 ; MIPS32: srl [[T11]],[[T11]],0x18 4663 ; MIPS32: sll [[T11]],[[T11]],0x18
4664 ; MIPS32: sll [[T0]],[[T0]],0x8 4664 ; MIPS32: sll [[T0]],[[T0]],0x8
4665 ; MIPS32: srl [[T0]],[[T0]],0x8 4665 ; MIPS32: srl [[T0]],[[T0]],0x8
4666 ; MIPS32: or [[T11]],[[T11]],[[T0]] 4666 ; MIPS32: or [[T11]],[[T11]],[[T0]]
4667 ; MIPS32: move [[T0]],a2 4667 ; MIPS32: move [[T0]],a2
4668 ; MIPS32: andi [[T0]],[[T0]],0xff 4668 ; MIPS32: andi [[T0]],[[T0]],0xff
4669 ; MIPS32: move [[T1]],[[T2]] 4669 ; MIPS32: move [[T1]],[[T2]]
4670 ; MIPS32: andi [[T1]],[[T1]],0xff 4670 ; MIPS32: andi [[T1]],[[T1]],0xff
4671 ; MIPS32: sll [[T0]],[[T0]],0x18 4671 ; MIPS32: sll [[T0]],[[T0]],0x18
4672 ; MIPS32: sll [[T1]],[[T1]],0x18 4672 ; MIPS32: sll [[T1]],[[T1]],0x18
4673 ; MIPS32: sltu [[T0]],[[T0]],[[T1]] 4673 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
(...skipping 29 matching lines...) Expand all
4703 ; MIPS32: sll [[T0]],[[T0]],0x10 4703 ; MIPS32: sll [[T0]],[[T0]],0x10
4704 ; MIPS32: lui [[T4]],0xff00 4704 ; MIPS32: lui [[T4]],0xff00
4705 ; MIPS32: ori [[T4]],[[T4]],0xffff 4705 ; MIPS32: ori [[T4]],[[T4]],0xffff
4706 ; MIPS32: and [[T1]],[[T1]],[[T4]] 4706 ; MIPS32: and [[T1]],[[T1]],[[T4]]
4707 ; MIPS32: or [[T0]],[[T0]],[[T1]] 4707 ; MIPS32: or [[T0]],[[T0]],[[T1]]
4708 ; MIPS32: srl [[T12:.*]],a2,0x18 4708 ; MIPS32: srl [[T12:.*]],a2,0x18
4709 ; MIPS32: srl [[T2]],[[T2]],0x18 4709 ; MIPS32: srl [[T2]],[[T2]],0x18
4710 ; MIPS32: sll [[T12]],[[T12]],0x18 4710 ; MIPS32: sll [[T12]],[[T12]],0x18
4711 ; MIPS32: sll [[T2]],[[T2]],0x18 4711 ; MIPS32: sll [[T2]],[[T2]],0x18
4712 ; MIPS32: sltu [[T12]],[[T12]],[[T2]] 4712 ; MIPS32: sltu [[T12]],[[T12]],[[T2]]
4713 ; MIPS32: srl [[T12]],[[T12]],0x18 4713 ; MIPS32: sll [[T12]],[[T12]],0x18
4714 ; MIPS32: sll [[T0]],[[T0]],0x8 4714 ; MIPS32: sll [[T0]],[[T0]],0x8
4715 ; MIPS32: srl [[T0]],[[T0]],0x8 4715 ; MIPS32: srl [[T0]],[[T0]],0x8
4716 ; MIPS32: or [[T12]],[[T12]],[[T0]] 4716 ; MIPS32: or [[T12]],[[T12]],[[T0]]
4717 ; MIPS32: move [[T0]],a3 4717 ; MIPS32: move [[T0]],a3
4718 ; MIPS32: andi [[T0]],[[T0]],0xff 4718 ; MIPS32: andi [[T0]],[[T0]],0xff
4719 ; MIPS32: move [[T1]],[[T3]] 4719 ; MIPS32: move [[T1]],[[T3]]
4720 ; MIPS32: andi [[T1]],[[T1]],0xff 4720 ; MIPS32: andi [[T1]],[[T1]],0xff
4721 ; MIPS32: sll [[T0]],[[T0]],0x18 4721 ; MIPS32: sll [[T0]],[[T0]],0x18
4722 ; MIPS32: sll [[T1]],[[T1]],0x18 4722 ; MIPS32: sll [[T1]],[[T1]],0x18
4723 ; MIPS32: sltu [[T0]],[[T0]],[[T1]] 4723 ; MIPS32: sltu [[T0]],[[T0]],[[T1]]
(...skipping 29 matching lines...) Expand all
4753 ; MIPS32: sll [[T0]],[[T0]],0x10 4753 ; MIPS32: sll [[T0]],[[T0]],0x10
4754 ; MIPS32: lui [[T2]],0xff00 4754 ; MIPS32: lui [[T2]],0xff00
4755 ; MIPS32: ori [[T2]],[[T2]],0xffff 4755 ; MIPS32: ori [[T2]],[[T2]],0xffff
4756 ; MIPS32: and [[T1]],[[T1]],[[T2]] 4756 ; MIPS32: and [[T1]],[[T1]],[[T2]]
4757 ; MIPS32: or [[T0]],[[T0]],[[T1]] 4757 ; MIPS32: or [[T0]],[[T0]],[[T1]]
4758 ; MIPS32: srl [[T13:.*]],a3,0x18 4758 ; MIPS32: srl [[T13:.*]],a3,0x18
4759 ; MIPS32: srl [[T3]],[[T3]],0x18 4759 ; MIPS32: srl [[T3]],[[T3]],0x18
4760 ; MIPS32: sll [[T13]],[[T13]],0x18 4760 ; MIPS32: sll [[T13]],[[T13]],0x18
4761 ; MIPS32: sll [[T3]],[[T3]],0x18 4761 ; MIPS32: sll [[T3]],[[T3]],0x18
4762 ; MIPS32: sltu [[T13]],[[T13]],[[T3]] 4762 ; MIPS32: sltu [[T13]],[[T13]],[[T3]]
4763 ; MIPS32: srl [[T13]],[[T13]],0x18 4763 ; MIPS32: sll [[T13]],[[T13]],0x18
4764 ; MIPS32: sll [[T0]],[[T0]],0x8 4764 ; MIPS32: sll [[T0]],[[T0]],0x8
4765 ; MIPS32: srl [[T0]],[[T0]],0x8 4765 ; MIPS32: srl [[T0]],[[T0]],0x8
4766 ; MIPS32: or [[T13]],[[T13]],[[T0]] 4766 ; MIPS32: or [[T13]],[[T13]],[[T0]]
4767 ; MIPS32: move v0,[[T10]] 4767 ; MIPS32: move v0,[[T10]]
4768 ; MIPS32: move v1,[[T11]] 4768 ; MIPS32: move v1,[[T11]]
4769 ; MIPS32: move a0,[[T12]] 4769 ; MIPS32: move a0,[[T12]]
4770 ; MIPS32: move a1,[[T13]] 4770 ; MIPS32: move a1,[[T13]]
4771 } 4771 }
4772 4772
4773 define internal <16 x i1> @test_icmp_v16i1_eq(<16 x i1> %a, <16 x i1> %b) { 4773 define internal <16 x i1> @test_icmp_v16i1_eq(<16 x i1> %a, <16 x i1> %b) {
(...skipping 63 matching lines...) Expand 10 before | Expand all | Expand 10 after
4837 ; MIPS32: and [[T4]],[[T4]],[[T9]] 4837 ; MIPS32: and [[T4]],[[T4]],[[T9]]
4838 ; MIPS32: or [[T8]],[[T8]],[[T4]] 4838 ; MIPS32: or [[T8]],[[T8]],[[T4]]
4839 ; MIPS32: srl [[T10:.*]],a0,0x18 4839 ; MIPS32: srl [[T10:.*]],a0,0x18
4840 ; MIPS32: andi [[T10]],[[T10]],0x1 4840 ; MIPS32: andi [[T10]],[[T10]],0x1
4841 ; MIPS32: srl [[T0]],[[T0]],0x18 4841 ; MIPS32: srl [[T0]],[[T0]],0x18
4842 ; MIPS32: andi [[T0]],[[T0]],0x1 4842 ; MIPS32: andi [[T0]],[[T0]],0x1
4843 ; MIPS32: sll [[T10]],[[T10]],0x1f 4843 ; MIPS32: sll [[T10]],[[T10]],0x1f
4844 ; MIPS32: sll [[T0]],[[T0]],0x1f 4844 ; MIPS32: sll [[T0]],[[T0]],0x1f
4845 ; MIPS32: xor [[T10]],[[T10]],[[T0]] 4845 ; MIPS32: xor [[T10]],[[T10]],[[T0]]
4846 ; MIPS32: sltiu [[T10]],[[T10]],1 4846 ; MIPS32: sltiu [[T10]],[[T10]],1
4847 ; MIPS32: srl [[T10]],[[T10]],0x18 4847 ; MIPS32: sll [[T10]],[[T10]],0x18
4848 ; MIPS32: sll [[T8]],[[T8]],0x8 4848 ; MIPS32: sll [[T8]],[[T8]],0x8
4849 ; MIPS32: srl [[T8]],[[T8]],0x8 4849 ; MIPS32: srl [[T8]],[[T8]],0x8
4850 ; MIPS32: or [[T10]],[[T10]],[[T8]] 4850 ; MIPS32: or [[T10]],[[T10]],[[T8]]
4851 ; MIPS32: move [[T0]],a1 4851 ; MIPS32: move [[T0]],a1
4852 ; MIPS32: andi [[T0]],[[T0]],0xff 4852 ; MIPS32: andi [[T0]],[[T0]],0xff
4853 ; MIPS32: andi [[T0]],[[T0]],0x1 4853 ; MIPS32: andi [[T0]],[[T0]],0x1
4854 ; MIPS32: move [[T4]],[[T1]] 4854 ; MIPS32: move [[T4]],[[T1]]
4855 ; MIPS32: andi [[T4]],[[T4]],0xff 4855 ; MIPS32: andi [[T4]],[[T4]],0xff
4856 ; MIPS32: andi [[T4]],[[T4]],0x1 4856 ; MIPS32: andi [[T4]],[[T4]],0x1
4857 ; MIPS32: sll [[T0]],[[T0]],0x1f 4857 ; MIPS32: sll [[T0]],[[T0]],0x1f
(...skipping 41 matching lines...) Expand 10 before | Expand all | Expand 10 after
4899 ; MIPS32: and [[T4]],[[T4]],[[T5]] 4899 ; MIPS32: and [[T4]],[[T4]],[[T5]]
4900 ; MIPS32: or [[T0]],[[T0]],[[T4]] 4900 ; MIPS32: or [[T0]],[[T0]],[[T4]]
4901 ; MIPS32: srl [[T11:.*]],a1,0x18 4901 ; MIPS32: srl [[T11:.*]],a1,0x18
4902 ; MIPS32: andi [[T11]],[[T11]],0x1 4902 ; MIPS32: andi [[T11]],[[T11]],0x1
4903 ; MIPS32: srl [[T1]],[[T1]],0x18 4903 ; MIPS32: srl [[T1]],[[T1]],0x18
4904 ; MIPS32: andi [[T1]],[[T1]],0x1 4904 ; MIPS32: andi [[T1]],[[T1]],0x1
4905 ; MIPS32: sll [[T11]],[[T11]],0x1f 4905 ; MIPS32: sll [[T11]],[[T11]],0x1f
4906 ; MIPS32: sll [[T1]],[[T1]],0x1f 4906 ; MIPS32: sll [[T1]],[[T1]],0x1f
4907 ; MIPS32: xor [[T11]],[[T11]],[[T1]] 4907 ; MIPS32: xor [[T11]],[[T11]],[[T1]]
4908 ; MIPS32: sltiu [[T11]],[[T11]],1 4908 ; MIPS32: sltiu [[T11]],[[T11]],1
4909 ; MIPS32: srl [[T11]],[[T11]],0x18 4909 ; MIPS32: sll [[T11]],[[T11]],0x18
4910 ; MIPS32: sll [[T0]],[[T0]],0x8 4910 ; MIPS32: sll [[T0]],[[T0]],0x8
4911 ; MIPS32: srl [[T0]],[[T0]],0x8 4911 ; MIPS32: srl [[T0]],[[T0]],0x8
4912 ; MIPS32: or [[T11]],[[T11]],[[T0]] 4912 ; MIPS32: or [[T11]],[[T11]],[[T0]]
4913 ; MIPS32: move [[T0]],a2 4913 ; MIPS32: move [[T0]],a2
4914 ; MIPS32: andi [[T0]],[[T0]],0xff 4914 ; MIPS32: andi [[T0]],[[T0]],0xff
4915 ; MIPS32: andi [[T0]],[[T0]],0x1 4915 ; MIPS32: andi [[T0]],[[T0]],0x1
4916 ; MIPS32: move [[T1]],[[T2]] 4916 ; MIPS32: move [[T1]],[[T2]]
4917 ; MIPS32: andi [[T1]],[[T1]],0xff 4917 ; MIPS32: andi [[T1]],[[T1]],0xff
4918 ; MIPS32: andi [[T1]],[[T1]],0x1 4918 ; MIPS32: andi [[T1]],[[T1]],0x1
4919 ; MIPS32: sll [[T0]],[[T0]],0x1f 4919 ; MIPS32: sll [[T0]],[[T0]],0x1f
(...skipping 41 matching lines...) Expand 10 before | Expand all | Expand 10 after
4961 ; MIPS32: and [[T1]],[[T1]],[[T4]] 4961 ; MIPS32: and [[T1]],[[T1]],[[T4]]
4962 ; MIPS32: or [[T0]],[[T0]],[[T1]] 4962 ; MIPS32: or [[T0]],[[T0]],[[T1]]
4963 ; MIPS32: srl [[T12:.*]],a2,0x18 4963 ; MIPS32: srl [[T12:.*]],a2,0x18
4964 ; MIPS32: andi [[T12]],[[T12]],0x1 4964 ; MIPS32: andi [[T12]],[[T12]],0x1
4965 ; MIPS32: srl [[T2]],[[T2]],0x18 4965 ; MIPS32: srl [[T2]],[[T2]],0x18
4966 ; MIPS32: andi [[T2]],[[T2]],0x1 4966 ; MIPS32: andi [[T2]],[[T2]],0x1
4967 ; MIPS32: sll [[T12]],[[T12]],0x1f 4967 ; MIPS32: sll [[T12]],[[T12]],0x1f
4968 ; MIPS32: sll [[T2]],[[T2]],0x1f 4968 ; MIPS32: sll [[T2]],[[T2]],0x1f
4969 ; MIPS32: xor [[T12]],[[T12]],[[T2]] 4969 ; MIPS32: xor [[T12]],[[T12]],[[T2]]
4970 ; MIPS32: sltiu [[T12]],[[T12]],1 4970 ; MIPS32: sltiu [[T12]],[[T12]],1
4971 ; MIPS32: srl [[T12]],[[T12]],0x18 4971 ; MIPS32: sll [[T12]],[[T12]],0x18
4972 ; MIPS32: sll [[T0]],[[T0]],0x8 4972 ; MIPS32: sll [[T0]],[[T0]],0x8
4973 ; MIPS32: srl [[T0]],[[T0]],0x8 4973 ; MIPS32: srl [[T0]],[[T0]],0x8
4974 ; MIPS32: or [[T12]],[[T12]],[[T0]] 4974 ; MIPS32: or [[T12]],[[T12]],[[T0]]
4975 ; MIPS32: move [[T0]],a3 4975 ; MIPS32: move [[T0]],a3
4976 ; MIPS32: andi [[T0]],[[T0]],0xff 4976 ; MIPS32: andi [[T0]],[[T0]],0xff
4977 ; MIPS32: andi [[T0]],[[T0]],0x1 4977 ; MIPS32: andi [[T0]],[[T0]],0x1
4978 ; MIPS32: move [[T1]],[[T3]] 4978 ; MIPS32: move [[T1]],[[T3]]
4979 ; MIPS32: andi [[T1]],[[T1]],0xff 4979 ; MIPS32: andi [[T1]],[[T1]],0xff
4980 ; MIPS32: andi [[T1]],[[T1]],0x1 4980 ; MIPS32: andi [[T1]],[[T1]],0x1
4981 ; MIPS32: sll [[T0]],[[T0]],0x1f 4981 ; MIPS32: sll [[T0]],[[T0]],0x1f
(...skipping 41 matching lines...) Expand 10 before | Expand all | Expand 10 after
5023 ; MIPS32: and [[T1]],[[T1]],[[T2]] 5023 ; MIPS32: and [[T1]],[[T1]],[[T2]]
5024 ; MIPS32: or [[T0]],[[T0]],[[T1]] 5024 ; MIPS32: or [[T0]],[[T0]],[[T1]]
5025 ; MIPS32: srl [[T13:.*]],a3,0x18 5025 ; MIPS32: srl [[T13:.*]],a3,0x18
5026 ; MIPS32: andi [[T13]],[[T13]],0x1 5026 ; MIPS32: andi [[T13]],[[T13]],0x1
5027 ; MIPS32: srl [[T3]],[[T3]],0x18 5027 ; MIPS32: srl [[T3]],[[T3]],0x18
5028 ; MIPS32: andi [[T3]],[[T3]],0x1 5028 ; MIPS32: andi [[T3]],[[T3]],0x1
5029 ; MIPS32: sll [[T13]],[[T13]],0x1f 5029 ; MIPS32: sll [[T13]],[[T13]],0x1f
5030 ; MIPS32: sll [[T3]],[[T3]],0x1f 5030 ; MIPS32: sll [[T3]],[[T3]],0x1f
5031 ; MIPS32: xor [[T13]],[[T13]],[[T3]] 5031 ; MIPS32: xor [[T13]],[[T13]],[[T3]]
5032 ; MIPS32: sltiu [[T13]],[[T13]],1 5032 ; MIPS32: sltiu [[T13]],[[T13]],1
5033 ; MIPS32: srl [[T13]],[[T13]],0x18 5033 ; MIPS32: sll [[T13]],[[T13]],0x18
5034 ; MIPS32: sll [[T0]],[[T0]],0x8 5034 ; MIPS32: sll [[T0]],[[T0]],0x8
5035 ; MIPS32: srl [[T0]],[[T0]],0x8 5035 ; MIPS32: srl [[T0]],[[T0]],0x8
5036 ; MIPS32: or [[T13]],[[T13]],[[T0]] 5036 ; MIPS32: or [[T13]],[[T13]],[[T0]]
5037 ; MIPS32: move v0,[[T10]] 5037 ; MIPS32: move v0,[[T10]]
5038 ; MIPS32: move v1,[[T11]] 5038 ; MIPS32: move v1,[[T11]]
5039 ; MIPS32: move a0,[[T12]] 5039 ; MIPS32: move a0,[[T12]]
5040 ; MIPS32: move a1,[[T13]] 5040 ; MIPS32: move a1,[[T13]]
5041 } 5041 }
5042 5042
5043 define internal <16 x i1> @test_icmp_v16i1_ne(<16 x i1> %a, <16 x i1> %b) { 5043 define internal <16 x i1> @test_icmp_v16i1_ne(<16 x i1> %a, <16 x i1> %b) {
(...skipping 64 matching lines...) Expand 10 before | Expand all | Expand 10 after
5108 ; MIPS32: and [[T4]],[[T4]],[[T9]] 5108 ; MIPS32: and [[T4]],[[T4]],[[T9]]
5109 ; MIPS32: or [[T8]],[[T8]],[[T4]] 5109 ; MIPS32: or [[T8]],[[T8]],[[T4]]
5110 ; MIPS32: srl [[T10:.*]],a0,0x18 5110 ; MIPS32: srl [[T10:.*]],a0,0x18
5111 ; MIPS32: andi [[T10]],[[T10]],0x1 5111 ; MIPS32: andi [[T10]],[[T10]],0x1
5112 ; MIPS32: srl [[T0]],[[T0]],0x18 5112 ; MIPS32: srl [[T0]],[[T0]],0x18
5113 ; MIPS32: andi [[T0]],[[T0]],0x1 5113 ; MIPS32: andi [[T0]],[[T0]],0x1
5114 ; MIPS32: sll [[T10]],[[T10]],0x1f 5114 ; MIPS32: sll [[T10]],[[T10]],0x1f
5115 ; MIPS32: sll [[T0]],[[T0]],0x1f 5115 ; MIPS32: sll [[T0]],[[T0]],0x1f
5116 ; MIPS32: xor [[T10]],[[T10]],[[T0]] 5116 ; MIPS32: xor [[T10]],[[T10]],[[T0]]
5117 ; MIPS32: sltu [[T10]],zero,[[T10]] 5117 ; MIPS32: sltu [[T10]],zero,[[T10]]
5118 ; MIPS32: srl [[T10]],[[T10]],0x18 5118 ; MIPS32: sll [[T10]],[[T10]],0x18
5119 ; MIPS32: sll [[T8]],[[T8]],0x8 5119 ; MIPS32: sll [[T8]],[[T8]],0x8
5120 ; MIPS32: srl [[T8]],[[T8]],0x8 5120 ; MIPS32: srl [[T8]],[[T8]],0x8
5121 ; MIPS32: or [[T10]],[[T10]],[[T8]] 5121 ; MIPS32: or [[T10]],[[T10]],[[T8]]
5122 ; MIPS32: move [[T0]],a1 5122 ; MIPS32: move [[T0]],a1
5123 ; MIPS32: andi [[T0]],[[T0]],0xff 5123 ; MIPS32: andi [[T0]],[[T0]],0xff
5124 ; MIPS32: andi [[T0]],[[T0]],0x1 5124 ; MIPS32: andi [[T0]],[[T0]],0x1
5125 ; MIPS32: move [[T4]],[[T1]] 5125 ; MIPS32: move [[T4]],[[T1]]
5126 ; MIPS32: andi [[T4]],[[T4]],0xff 5126 ; MIPS32: andi [[T4]],[[T4]],0xff
5127 ; MIPS32: andi [[T4]],[[T4]],0x1 5127 ; MIPS32: andi [[T4]],[[T4]],0x1
5128 ; MIPS32: sll [[T0]],[[T0]],0x1f 5128 ; MIPS32: sll [[T0]],[[T0]],0x1f
(...skipping 41 matching lines...) Expand 10 before | Expand all | Expand 10 after
5170 ; MIPS32: and [[T4]],[[T4]],[[T5]] 5170 ; MIPS32: and [[T4]],[[T4]],[[T5]]
5171 ; MIPS32: or [[T0]],[[T0]],[[T4]] 5171 ; MIPS32: or [[T0]],[[T0]],[[T4]]
5172 ; MIPS32: srl [[T11:.*]],a1,0x18 5172 ; MIPS32: srl [[T11:.*]],a1,0x18
5173 ; MIPS32: andi [[T11]],[[T11]],0x1 5173 ; MIPS32: andi [[T11]],[[T11]],0x1
5174 ; MIPS32: srl [[T1]],[[T1]],0x18 5174 ; MIPS32: srl [[T1]],[[T1]],0x18
5175 ; MIPS32: andi [[T1]],[[T1]],0x1 5175 ; MIPS32: andi [[T1]],[[T1]],0x1
5176 ; MIPS32: sll [[T11]],[[T11]],0x1f 5176 ; MIPS32: sll [[T11]],[[T11]],0x1f
5177 ; MIPS32: sll [[T1]],[[T1]],0x1f 5177 ; MIPS32: sll [[T1]],[[T1]],0x1f
5178 ; MIPS32: xor [[T11]],[[T11]],[[T1]] 5178 ; MIPS32: xor [[T11]],[[T11]],[[T1]]
5179 ; MIPS32: sltu [[T11]],zero,[[T11]] 5179 ; MIPS32: sltu [[T11]],zero,[[T11]]
5180 ; MIPS32: srl [[T11]],[[T11]],0x18 5180 ; MIPS32: sll [[T11]],[[T11]],0x18
5181 ; MIPS32: sll [[T0]],[[T0]],0x8 5181 ; MIPS32: sll [[T0]],[[T0]],0x8
5182 ; MIPS32: srl [[T0]],[[T0]],0x8 5182 ; MIPS32: srl [[T0]],[[T0]],0x8
5183 ; MIPS32: or [[T11]],[[T11]],[[T0]] 5183 ; MIPS32: or [[T11]],[[T11]],[[T0]]
5184 ; MIPS32: move [[T0]],a2 5184 ; MIPS32: move [[T0]],a2
5185 ; MIPS32: andi [[T0]],[[T0]],0xff 5185 ; MIPS32: andi [[T0]],[[T0]],0xff
5186 ; MIPS32: andi [[T0]],[[T0]],0x1 5186 ; MIPS32: andi [[T0]],[[T0]],0x1
5187 ; MIPS32: move [[T1]],[[T2]] 5187 ; MIPS32: move [[T1]],[[T2]]
5188 ; MIPS32: andi [[T1]],[[T1]],0xff 5188 ; MIPS32: andi [[T1]],[[T1]],0xff
5189 ; MIPS32: andi [[T1]],[[T1]],0x1 5189 ; MIPS32: andi [[T1]],[[T1]],0x1
5190 ; MIPS32: sll [[T0]],[[T0]],0x1f 5190 ; MIPS32: sll [[T0]],[[T0]],0x1f
(...skipping 41 matching lines...) Expand 10 before | Expand all | Expand 10 after
5232 ; MIPS32: and [[T1]],[[T1]],[[T4]] 5232 ; MIPS32: and [[T1]],[[T1]],[[T4]]
5233 ; MIPS32: or [[T0]],[[T0]],[[T1]] 5233 ; MIPS32: or [[T0]],[[T0]],[[T1]]
5234 ; MIPS32: srl [[T12:.*]],a2,0x18 5234 ; MIPS32: srl [[T12:.*]],a2,0x18
5235 ; MIPS32: andi [[T12]],[[T12]],0x1 5235 ; MIPS32: andi [[T12]],[[T12]],0x1
5236 ; MIPS32: srl [[T2]],[[T2]],0x18 5236 ; MIPS32: srl [[T2]],[[T2]],0x18
5237 ; MIPS32: andi [[T2]],[[T2]],0x1 5237 ; MIPS32: andi [[T2]],[[T2]],0x1
5238 ; MIPS32: sll [[T12]],[[T12]],0x1f 5238 ; MIPS32: sll [[T12]],[[T12]],0x1f
5239 ; MIPS32: sll [[T2]],[[T2]],0x1f 5239 ; MIPS32: sll [[T2]],[[T2]],0x1f
5240 ; MIPS32: xor [[T12]],[[T12]],[[T2]] 5240 ; MIPS32: xor [[T12]],[[T12]],[[T2]]
5241 ; MIPS32: sltu [[T12]],zero,[[T12]] 5241 ; MIPS32: sltu [[T12]],zero,[[T12]]
5242 ; MIPS32: srl [[T12]],[[T12]],0x18 5242 ; MIPS32: sll [[T12]],[[T12]],0x18
5243 ; MIPS32: sll [[T0]],[[T0]],0x8 5243 ; MIPS32: sll [[T0]],[[T0]],0x8
5244 ; MIPS32: srl [[T0]],[[T0]],0x8 5244 ; MIPS32: srl [[T0]],[[T0]],0x8
5245 ; MIPS32: or [[T12]],[[T12]],[[T0]] 5245 ; MIPS32: or [[T12]],[[T12]],[[T0]]
5246 ; MIPS32: move [[T0]],a3 5246 ; MIPS32: move [[T0]],a3
5247 ; MIPS32: andi [[T0]],[[T0]],0xff 5247 ; MIPS32: andi [[T0]],[[T0]],0xff
5248 ; MIPS32: andi [[T0]],[[T0]],0x1 5248 ; MIPS32: andi [[T0]],[[T0]],0x1
5249 ; MIPS32: move [[T1]],[[T3]] 5249 ; MIPS32: move [[T1]],[[T3]]
5250 ; MIPS32: andi [[T1]],[[T1]],0xff 5250 ; MIPS32: andi [[T1]],[[T1]],0xff
5251 ; MIPS32: andi [[T1]],[[T1]],0x1 5251 ; MIPS32: andi [[T1]],[[T1]],0x1
5252 ; MIPS32: sll [[T0]],[[T0]],0x1f 5252 ; MIPS32: sll [[T0]],[[T0]],0x1f
(...skipping 41 matching lines...) Expand 10 before | Expand all | Expand 10 after
5294 ; MIPS32: and [[T1]],[[T1]],[[T2]] 5294 ; MIPS32: and [[T1]],[[T1]],[[T2]]
5295 ; MIPS32: or [[T0]],[[T0]],[[T1]] 5295 ; MIPS32: or [[T0]],[[T0]],[[T1]]
5296 ; MIPS32: srl [[T13:.*]],a3,0x18 5296 ; MIPS32: srl [[T13:.*]],a3,0x18
5297 ; MIPS32: andi [[T13]],[[T13]],0x1 5297 ; MIPS32: andi [[T13]],[[T13]],0x1
5298 ; MIPS32: srl [[T3]],[[T3]],0x18 5298 ; MIPS32: srl [[T3]],[[T3]],0x18
5299 ; MIPS32: andi [[T3]],[[T3]],0x1 5299 ; MIPS32: andi [[T3]],[[T3]],0x1
5300 ; MIPS32: sll [[T13]],[[T13]],0x1f 5300 ; MIPS32: sll [[T13]],[[T13]],0x1f
5301 ; MIPS32: sll [[T3]],[[T3]],0x1f 5301 ; MIPS32: sll [[T3]],[[T3]],0x1f
5302 ; MIPS32: xor [[T13]],[[T13]],[[T3]] 5302 ; MIPS32: xor [[T13]],[[T13]],[[T3]]
5303 ; MIPS32: sltu [[T13]],zero,[[T13]] 5303 ; MIPS32: sltu [[T13]],zero,[[T13]]
5304 ; MIPS32: srl [[T13]],[[T13]],0x18 5304 ; MIPS32: sll [[T13]],[[T13]],0x18
5305 ; MIPS32: sll [[T0]],[[T0]],0x8 5305 ; MIPS32: sll [[T0]],[[T0]],0x8
5306 ; MIPS32: srl [[T0]],[[T0]],0x8 5306 ; MIPS32: srl [[T0]],[[T0]],0x8
5307 ; MIPS32: or [[T13]],[[T13]],[[T0]] 5307 ; MIPS32: or [[T13]],[[T13]],[[T0]]
5308 ; MIPS32: move v0,[[T10]] 5308 ; MIPS32: move v0,[[T10]]
5309 ; MIPS32: move v1,[[T11]] 5309 ; MIPS32: move v1,[[T11]]
5310 ; MIPS32: move a0,[[T12]] 5310 ; MIPS32: move a0,[[T12]]
5311 ; MIPS32: move a1,[[T13]] 5311 ; MIPS32: move a1,[[T13]]
5312 } 5312 }
5313 5313
5314 define internal <16 x i1> @test_icmp_v16i1_sgt(<16 x i1> %a, <16 x i1> %b) { 5314 define internal <16 x i1> @test_icmp_v16i1_sgt(<16 x i1> %a, <16 x i1> %b) {
(...skipping 59 matching lines...) Expand 10 before | Expand all | Expand 10 after
5374 ; MIPS32: ori [[T4]],[[T4]],0xffff 5374 ; MIPS32: ori [[T4]],[[T4]],0xffff
5375 ; MIPS32: and [[T8]],[[T8]],[[T4]] 5375 ; MIPS32: and [[T8]],[[T8]],[[T4]]
5376 ; MIPS32: or [[T9]],[[T9]],[[T8]] 5376 ; MIPS32: or [[T9]],[[T9]],[[T8]]
5377 ; MIPS32: srl [[T10:.*]],a0,0x18 5377 ; MIPS32: srl [[T10:.*]],a0,0x18
5378 ; MIPS32: andi [[T10]],[[T10]],0x1 5378 ; MIPS32: andi [[T10]],[[T10]],0x1
5379 ; MIPS32: srl [[T0]],[[T0]],0x18 5379 ; MIPS32: srl [[T0]],[[T0]],0x18
5380 ; MIPS32: andi [[T0]],[[T0]],0x1 5380 ; MIPS32: andi [[T0]],[[T0]],0x1
5381 ; MIPS32: sll [[T10]],[[T10]],0x1f 5381 ; MIPS32: sll [[T10]],[[T10]],0x1f
5382 ; MIPS32: sll [[T0]],[[T0]],0x1f 5382 ; MIPS32: sll [[T0]],[[T0]],0x1f
5383 ; MIPS32: slt [[T0]],[[T0]],[[T10]] 5383 ; MIPS32: slt [[T0]],[[T0]],[[T10]]
5384 ; MIPS32: srl [[T0]],[[T0]],0x18 5384 ; MIPS32: sll [[T0]],[[T0]],0x18
5385 ; MIPS32: sll [[T9]],[[T9]],0x8 5385 ; MIPS32: sll [[T9]],[[T9]],0x8
5386 ; MIPS32: srl [[T9]],[[T9]],0x8 5386 ; MIPS32: srl [[T9]],[[T9]],0x8
5387 ; MIPS32: or v0,[[T0]],[[T9]] 5387 ; MIPS32: or v0,[[T0]],[[T9]]
5388 ; MIPS32: move [[T10]],a1 5388 ; MIPS32: move [[T10]],a1
5389 ; MIPS32: andi [[T10]],[[T10]],0xff 5389 ; MIPS32: andi [[T10]],[[T10]],0xff
5390 ; MIPS32: andi [[T10]],[[T10]],0x1 5390 ; MIPS32: andi [[T10]],[[T10]],0x1
5391 ; MIPS32: move [[T4]],[[T1]] 5391 ; MIPS32: move [[T4]],[[T1]]
5392 ; MIPS32: andi [[T4]],[[T4]],0xff 5392 ; MIPS32: andi [[T4]],[[T4]],0xff
5393 ; MIPS32: andi [[T4]],[[T4]],0x1 5393 ; MIPS32: andi [[T4]],[[T4]],0x1
5394 ; MIPS32: sll [[T10]],[[T10]],0x1f 5394 ; MIPS32: sll [[T10]],[[T10]],0x1f
(...skipping 37 matching lines...) Expand 10 before | Expand all | Expand 10 after
5432 ; MIPS32: ori [[T10]],[[T10]],0xffff 5432 ; MIPS32: ori [[T10]],[[T10]],0xffff
5433 ; MIPS32: and [[T5]],[[T5]],[[T10]] 5433 ; MIPS32: and [[T5]],[[T5]],[[T10]]
5434 ; MIPS32: or [[T4]],[[T4]],[[T5]] 5434 ; MIPS32: or [[T4]],[[T4]],[[T5]]
5435 ; MIPS32: srl [[T11:.*]],a1,0x18 5435 ; MIPS32: srl [[T11:.*]],a1,0x18
5436 ; MIPS32: andi [[T11]],[[T11]],0x1 5436 ; MIPS32: andi [[T11]],[[T11]],0x1
5437 ; MIPS32: srl [[T1]],[[T1]],0x18 5437 ; MIPS32: srl [[T1]],[[T1]],0x18
5438 ; MIPS32: andi [[T1]],[[T1]],0x1 5438 ; MIPS32: andi [[T1]],[[T1]],0x1
5439 ; MIPS32: sll [[T11]],[[T11]],0x1f 5439 ; MIPS32: sll [[T11]],[[T11]],0x1f
5440 ; MIPS32: sll [[T1]],[[T1]],0x1f 5440 ; MIPS32: sll [[T1]],[[T1]],0x1f
5441 ; MIPS32: slt [[T1]],[[T1]],[[T11]] 5441 ; MIPS32: slt [[T1]],[[T1]],[[T11]]
5442 ; MIPS32: srl [[T1]],[[T1]],0x18 5442 ; MIPS32: sll [[T1]],[[T1]],0x18
5443 ; MIPS32: sll [[T4]],[[T4]],0x8 5443 ; MIPS32: sll [[T4]],[[T4]],0x8
5444 ; MIPS32: srl [[T4]],[[T4]],0x8 5444 ; MIPS32: srl [[T4]],[[T4]],0x8
5445 ; MIPS32: or v1,[[T1]],[[T4]] 5445 ; MIPS32: or v1,[[T1]],[[T4]]
5446 ; MIPS32: move [[T10]],a2 5446 ; MIPS32: move [[T10]],a2
5447 ; MIPS32: andi [[T10]],[[T10]],0xff 5447 ; MIPS32: andi [[T10]],[[T10]],0xff
5448 ; MIPS32: andi [[T10]],[[T10]],0x1 5448 ; MIPS32: andi [[T10]],[[T10]],0x1
5449 ; MIPS32: move [[T11]],[[T2]] 5449 ; MIPS32: move [[T11]],[[T2]]
5450 ; MIPS32: andi [[T11]],[[T11]],0xff 5450 ; MIPS32: andi [[T11]],[[T11]],0xff
5451 ; MIPS32: andi [[T11]],[[T11]],0x1 5451 ; MIPS32: andi [[T11]],[[T11]],0x1
5452 ; MIPS32: sll [[T10]],[[T10]],0x1f 5452 ; MIPS32: sll [[T10]],[[T10]],0x1f
(...skipping 37 matching lines...) Expand 10 before | Expand all | Expand 10 after
5490 ; MIPS32: ori [[T10]],[[T10]],0xffff 5490 ; MIPS32: ori [[T10]],[[T10]],0xffff
5491 ; MIPS32: and [[T4]],[[T4]],[[T10]] 5491 ; MIPS32: and [[T4]],[[T4]],[[T10]]
5492 ; MIPS32: or [[T11]],[[T11]],[[T4]] 5492 ; MIPS32: or [[T11]],[[T11]],[[T4]]
5493 ; MIPS32: srl [[T12:.*]],a2,0x18 5493 ; MIPS32: srl [[T12:.*]],a2,0x18
5494 ; MIPS32: andi [[T12]],[[T12]],0x1 5494 ; MIPS32: andi [[T12]],[[T12]],0x1
5495 ; MIPS32: srl [[T2]],[[T2]],0x18 5495 ; MIPS32: srl [[T2]],[[T2]],0x18
5496 ; MIPS32: andi [[T2]],[[T2]],0x1 5496 ; MIPS32: andi [[T2]],[[T2]],0x1
5497 ; MIPS32: sll [[T12]],[[T12]],0x1f 5497 ; MIPS32: sll [[T12]],[[T12]],0x1f
5498 ; MIPS32: sll [[T2]],[[T2]],0x1f 5498 ; MIPS32: sll [[T2]],[[T2]],0x1f
5499 ; MIPS32: slt [[T2]],[[T2]],[[T12]] 5499 ; MIPS32: slt [[T2]],[[T2]],[[T12]]
5500 ; MIPS32: srl [[T2]],[[T2]],0x18 5500 ; MIPS32: sll [[T2]],[[T2]],0x18
5501 ; MIPS32: sll [[T11]],[[T11]],0x8 5501 ; MIPS32: sll [[T11]],[[T11]],0x8
5502 ; MIPS32: srl [[T11]],[[T11]],0x8 5502 ; MIPS32: srl [[T11]],[[T11]],0x8
5503 ; MIPS32: or [[T2]],[[T2]],[[T11]] 5503 ; MIPS32: or [[T2]],[[T2]],[[T11]]
5504 ; MIPS32: move [[T10]],a3 5504 ; MIPS32: move [[T10]],a3
5505 ; MIPS32: andi [[T10]],[[T10]],0xff 5505 ; MIPS32: andi [[T10]],[[T10]],0xff
5506 ; MIPS32: andi [[T10]],[[T10]],0x1 5506 ; MIPS32: andi [[T10]],[[T10]],0x1
5507 ; MIPS32: move [[T11]],[[T3]] 5507 ; MIPS32: move [[T11]],[[T3]]
5508 ; MIPS32: andi [[T11]],[[T11]],0xff 5508 ; MIPS32: andi [[T11]],[[T11]],0xff
5509 ; MIPS32: andi [[T11]],[[T11]],0x1 5509 ; MIPS32: andi [[T11]],[[T11]],0x1
5510 ; MIPS32: sll [[T10]],[[T10]],0x1f 5510 ; MIPS32: sll [[T10]],[[T10]],0x1f
(...skipping 37 matching lines...) Expand 10 before | Expand all | Expand 10 after
5548 ; MIPS32: ori [[T10]],[[T10]],0xffff 5548 ; MIPS32: ori [[T10]],[[T10]],0xffff
5549 ; MIPS32: and [[T12]],[[T12]],[[T10]] 5549 ; MIPS32: and [[T12]],[[T12]],[[T10]]
5550 ; MIPS32: or [[T11]],[[T11]],[[T12]] 5550 ; MIPS32: or [[T11]],[[T11]],[[T12]]
5551 ; MIPS32: srl [[T13:.*]],a3,0x18 5551 ; MIPS32: srl [[T13:.*]],a3,0x18
5552 ; MIPS32: andi [[T13]],[[T13]],0x1 5552 ; MIPS32: andi [[T13]],[[T13]],0x1
5553 ; MIPS32: srl [[T3]],[[T3]],0x18 5553 ; MIPS32: srl [[T3]],[[T3]],0x18
5554 ; MIPS32: andi [[T3]],[[T3]],0x1 5554 ; MIPS32: andi [[T3]],[[T3]],0x1
5555 ; MIPS32: sll [[T13]],[[T13]],0x1f 5555 ; MIPS32: sll [[T13]],[[T13]],0x1f
5556 ; MIPS32: sll [[T3]],[[T3]],0x1f 5556 ; MIPS32: sll [[T3]],[[T3]],0x1f
5557 ; MIPS32: slt [[T3]],[[T3]],[[T13]] 5557 ; MIPS32: slt [[T3]],[[T3]],[[T13]]
5558 ; MIPS32: srl [[T3]],[[T3]],0x18 5558 ; MIPS32: sll [[T3]],[[T3]],0x18
5559 ; MIPS32: sll [[T11]],[[T11]],0x8 5559 ; MIPS32: sll [[T11]],[[T11]],0x8
5560 ; MIPS32: srl [[T11]],[[T11]],0x8 5560 ; MIPS32: srl [[T11]],[[T11]],0x8
5561 ; MIPS32: or [[T3]],[[T3]],[[T11]] 5561 ; MIPS32: or [[T3]],[[T3]],[[T11]]
5562 ; MIPS32: move a0,[[T2]] 5562 ; MIPS32: move a0,[[T2]]
5563 ; MIPS32: move a1,[[T3]] 5563 ; MIPS32: move a1,[[T3]]
5564 } 5564 }
5565 5565
5566 define internal <16 x i1> @test_icmp_v16i1_sle(<16 x i1> %a, <16 x i1> %b) { 5566 define internal <16 x i1> @test_icmp_v16i1_sle(<16 x i1> %a, <16 x i1> %b) {
5567 entry: 5567 entry:
5568 %res = icmp sle <16 x i1> %a, %b 5568 %res = icmp sle <16 x i1> %a, %b
(...skipping 62 matching lines...) Expand 10 before | Expand all | Expand 10 after
5631 ; MIPS32: and [[T8]],[[T8]],[[T4]] 5631 ; MIPS32: and [[T8]],[[T8]],[[T4]]
5632 ; MIPS32: or [[T9]],[[T9]],[[T8]] 5632 ; MIPS32: or [[T9]],[[T9]],[[T8]]
5633 ; MIPS32: srl [[T10:.*]],a0,0x18 5633 ; MIPS32: srl [[T10:.*]],a0,0x18
5634 ; MIPS32: andi [[T10]],[[T10]],0x1 5634 ; MIPS32: andi [[T10]],[[T10]],0x1
5635 ; MIPS32: srl [[T0]],[[T0]],0x18 5635 ; MIPS32: srl [[T0]],[[T0]],0x18
5636 ; MIPS32: andi [[T0]],[[T0]],0x1 5636 ; MIPS32: andi [[T0]],[[T0]],0x1
5637 ; MIPS32: sll [[T10]],[[T10]],0x1f 5637 ; MIPS32: sll [[T10]],[[T10]],0x1f
5638 ; MIPS32: sll [[T0]],[[T0]],0x1f 5638 ; MIPS32: sll [[T0]],[[T0]],0x1f
5639 ; MIPS32: slt [[T0]],[[T0]],[[T10]] 5639 ; MIPS32: slt [[T0]],[[T0]],[[T10]]
5640 ; MIPS32: xori [[T0]],[[T0]],0x1 5640 ; MIPS32: xori [[T0]],[[T0]],0x1
5641 ; MIPS32: srl [[T0]],[[T0]],0x18 5641 ; MIPS32: sll [[T0]],[[T0]],0x18
5642 ; MIPS32: sll [[T9]],[[T9]],0x8 5642 ; MIPS32: sll [[T9]],[[T9]],0x8
5643 ; MIPS32: srl [[T9]],[[T9]],0x8 5643 ; MIPS32: srl [[T9]],[[T9]],0x8
5644 ; MIPS32: or v0,[[T0]],[[T9]] 5644 ; MIPS32: or v0,[[T0]],[[T9]]
5645 ; MIPS32: move [[T10]],a1 5645 ; MIPS32: move [[T10]],a1
5646 ; MIPS32: andi [[T10]],[[T10]],0xff 5646 ; MIPS32: andi [[T10]],[[T10]],0xff
5647 ; MIPS32: andi [[T10]],[[T10]],0x1 5647 ; MIPS32: andi [[T10]],[[T10]],0x1
5648 ; MIPS32: move [[T4]],[[T1]] 5648 ; MIPS32: move [[T4]],[[T1]]
5649 ; MIPS32: andi [[T4]],[[T4]],0xff 5649 ; MIPS32: andi [[T4]],[[T4]],0xff
5650 ; MIPS32: andi [[T4]],[[T4]],0x1 5650 ; MIPS32: andi [[T4]],[[T4]],0x1
5651 ; MIPS32: sll [[T10]],[[T10]],0x1f 5651 ; MIPS32: sll [[T10]],[[T10]],0x1f
(...skipping 41 matching lines...) Expand 10 before | Expand all | Expand 10 after
5693 ; MIPS32: and [[T5]],[[T5]],[[T10]] 5693 ; MIPS32: and [[T5]],[[T5]],[[T10]]
5694 ; MIPS32: or [[T4]],[[T4]],[[T5]] 5694 ; MIPS32: or [[T4]],[[T4]],[[T5]]
5695 ; MIPS32: srl [[T11:.*]],a1,0x18 5695 ; MIPS32: srl [[T11:.*]],a1,0x18
5696 ; MIPS32: andi [[T11]],[[T11]],0x1 5696 ; MIPS32: andi [[T11]],[[T11]],0x1
5697 ; MIPS32: srl [[T1]],[[T1]],0x18 5697 ; MIPS32: srl [[T1]],[[T1]],0x18
5698 ; MIPS32: andi [[T1]],[[T1]],0x1 5698 ; MIPS32: andi [[T1]],[[T1]],0x1
5699 ; MIPS32: sll [[T11]],[[T11]],0x1f 5699 ; MIPS32: sll [[T11]],[[T11]],0x1f
5700 ; MIPS32: sll [[T1]],[[T1]],0x1f 5700 ; MIPS32: sll [[T1]],[[T1]],0x1f
5701 ; MIPS32: slt [[T1]],[[T1]],[[T11]] 5701 ; MIPS32: slt [[T1]],[[T1]],[[T11]]
5702 ; MIPS32: xori [[T1]],[[T1]],0x1 5702 ; MIPS32: xori [[T1]],[[T1]],0x1
5703 ; MIPS32: srl [[T1]],[[T1]],0x18 5703 ; MIPS32: sll [[T1]],[[T1]],0x18
5704 ; MIPS32: sll [[T4]],[[T4]],0x8 5704 ; MIPS32: sll [[T4]],[[T4]],0x8
5705 ; MIPS32: srl [[T4]],[[T4]],0x8 5705 ; MIPS32: srl [[T4]],[[T4]],0x8
5706 ; MIPS32: or v1,[[T1]],[[T4]] 5706 ; MIPS32: or v1,[[T1]],[[T4]]
5707 ; MIPS32: move [[T10]],a2 5707 ; MIPS32: move [[T10]],a2
5708 ; MIPS32: andi [[T10]],[[T10]],0xff 5708 ; MIPS32: andi [[T10]],[[T10]],0xff
5709 ; MIPS32: andi [[T10]],[[T10]],0x1 5709 ; MIPS32: andi [[T10]],[[T10]],0x1
5710 ; MIPS32: move [[T11]],[[T2]] 5710 ; MIPS32: move [[T11]],[[T2]]
5711 ; MIPS32: andi [[T11]],[[T11]],0xff 5711 ; MIPS32: andi [[T11]],[[T11]],0xff
5712 ; MIPS32: andi [[T11]],[[T11]],0x1 5712 ; MIPS32: andi [[T11]],[[T11]],0x1
5713 ; MIPS32: sll [[T10]],[[T10]],0x1f 5713 ; MIPS32: sll [[T10]],[[T10]],0x1f
(...skipping 41 matching lines...) Expand 10 before | Expand all | Expand 10 after
5755 ; MIPS32: and [[T4]],[[T4]],[[T10]] 5755 ; MIPS32: and [[T4]],[[T4]],[[T10]]
5756 ; MIPS32: or [[T11]],[[T11]],[[T4]] 5756 ; MIPS32: or [[T11]],[[T11]],[[T4]]
5757 ; MIPS32: srl [[T12:.*]],a2,0x18 5757 ; MIPS32: srl [[T12:.*]],a2,0x18
5758 ; MIPS32: andi [[T12]],[[T12]],0x1 5758 ; MIPS32: andi [[T12]],[[T12]],0x1
5759 ; MIPS32: srl [[T2]],[[T2]],0x18 5759 ; MIPS32: srl [[T2]],[[T2]],0x18
5760 ; MIPS32: andi [[T2]],[[T2]],0x1 5760 ; MIPS32: andi [[T2]],[[T2]],0x1
5761 ; MIPS32: sll [[T12]],[[T12]],0x1f 5761 ; MIPS32: sll [[T12]],[[T12]],0x1f
5762 ; MIPS32: sll [[T2]],[[T2]],0x1f 5762 ; MIPS32: sll [[T2]],[[T2]],0x1f
5763 ; MIPS32: slt [[T2]],[[T2]],[[T12]] 5763 ; MIPS32: slt [[T2]],[[T2]],[[T12]]
5764 ; MIPS32: xori [[T2]],[[T2]],0x1 5764 ; MIPS32: xori [[T2]],[[T2]],0x1
5765 ; MIPS32: srl [[T2]],[[T2]],0x18 5765 ; MIPS32: sll [[T2]],[[T2]],0x18
5766 ; MIPS32: sll [[T11]],[[T11]],0x8 5766 ; MIPS32: sll [[T11]],[[T11]],0x8
5767 ; MIPS32: srl [[T11]],[[T11]],0x8 5767 ; MIPS32: srl [[T11]],[[T11]],0x8
5768 ; MIPS32: or [[T2]],[[T2]],[[T11]] 5768 ; MIPS32: or [[T2]],[[T2]],[[T11]]
5769 ; MIPS32: move [[T10]],a3 5769 ; MIPS32: move [[T10]],a3
5770 ; MIPS32: andi [[T10]],[[T10]],0xff 5770 ; MIPS32: andi [[T10]],[[T10]],0xff
5771 ; MIPS32: andi [[T10]],[[T10]],0x1 5771 ; MIPS32: andi [[T10]],[[T10]],0x1
5772 ; MIPS32: move [[T11]],[[T3]] 5772 ; MIPS32: move [[T11]],[[T3]]
5773 ; MIPS32: andi [[T11]],[[T11]],0xff 5773 ; MIPS32: andi [[T11]],[[T11]],0xff
5774 ; MIPS32: andi [[T11]],[[T11]],0x1 5774 ; MIPS32: andi [[T11]],[[T11]],0x1
5775 ; MIPS32: sll [[T10]],[[T10]],0x1f 5775 ; MIPS32: sll [[T10]],[[T10]],0x1f
(...skipping 41 matching lines...) Expand 10 before | Expand all | Expand 10 after
5817 ; MIPS32: and [[T12]],[[T12]],[[T10]] 5817 ; MIPS32: and [[T12]],[[T12]],[[T10]]
5818 ; MIPS32: or [[T11]],[[T11]],[[T12]] 5818 ; MIPS32: or [[T11]],[[T11]],[[T12]]
5819 ; MIPS32: srl [[T13:.*]],a3,0x18 5819 ; MIPS32: srl [[T13:.*]],a3,0x18
5820 ; MIPS32: andi [[T13]],[[T13]],0x1 5820 ; MIPS32: andi [[T13]],[[T13]],0x1
5821 ; MIPS32: srl [[T3]],[[T3]],0x18 5821 ; MIPS32: srl [[T3]],[[T3]],0x18
5822 ; MIPS32: andi [[T3]],[[T3]],0x1 5822 ; MIPS32: andi [[T3]],[[T3]],0x1
5823 ; MIPS32: sll [[T13]],[[T13]],0x1f 5823 ; MIPS32: sll [[T13]],[[T13]],0x1f
5824 ; MIPS32: sll [[T3]],[[T3]],0x1f 5824 ; MIPS32: sll [[T3]],[[T3]],0x1f
5825 ; MIPS32: slt [[T3]],[[T3]],[[T13]] 5825 ; MIPS32: slt [[T3]],[[T3]],[[T13]]
5826 ; MIPS32: xori [[T3]],[[T3]],0x1 5826 ; MIPS32: xori [[T3]],[[T3]],0x1
5827 ; MIPS32: srl [[T3]],[[T3]],0x18 5827 ; MIPS32: sll [[T3]],[[T3]],0x18
5828 ; MIPS32: sll [[T11]],[[T11]],0x8 5828 ; MIPS32: sll [[T11]],[[T11]],0x8
5829 ; MIPS32: srl [[T11]],[[T11]],0x8 5829 ; MIPS32: srl [[T11]],[[T11]],0x8
5830 ; MIPS32: or [[T3]],[[T3]],[[T11]] 5830 ; MIPS32: or [[T3]],[[T3]],[[T11]]
5831 ; MIPS32: move a0,[[T2]] 5831 ; MIPS32: move a0,[[T2]]
5832 ; MIPS32: move a1,[[T3]] 5832 ; MIPS32: move a1,[[T3]]
5833 } 5833 }
5834 5834
5835 define internal <16 x i1> @test_icmp_v16i1_slt(<16 x i1> %a, <16 x i1> %b) { 5835 define internal <16 x i1> @test_icmp_v16i1_slt(<16 x i1> %a, <16 x i1> %b) {
5836 entry: 5836 entry:
5837 %res = icmp slt <16 x i1> %a, %b 5837 %res = icmp slt <16 x i1> %a, %b
(...skipping 57 matching lines...) Expand 10 before | Expand all | Expand 10 after
5895 ; MIPS32: ori [[T9]],[[T9]],0xffff 5895 ; MIPS32: ori [[T9]],[[T9]],0xffff
5896 ; MIPS32: and [[T4]],[[T4]],[[T9]] 5896 ; MIPS32: and [[T4]],[[T4]],[[T9]]
5897 ; MIPS32: or [[T8]],[[T8]],[[T4]] 5897 ; MIPS32: or [[T8]],[[T8]],[[T4]]
5898 ; MIPS32: srl [[T10:.*]],a0,0x18 5898 ; MIPS32: srl [[T10:.*]],a0,0x18
5899 ; MIPS32: andi [[T10]],[[T10]],0x1 5899 ; MIPS32: andi [[T10]],[[T10]],0x1
5900 ; MIPS32: srl [[T0]],[[T0]],0x18 5900 ; MIPS32: srl [[T0]],[[T0]],0x18
5901 ; MIPS32: andi [[T0]],[[T0]],0x1 5901 ; MIPS32: andi [[T0]],[[T0]],0x1
5902 ; MIPS32: sll [[T10]],[[T10]],0x1f 5902 ; MIPS32: sll [[T10]],[[T10]],0x1f
5903 ; MIPS32: sll [[T0]],[[T0]],0x1f 5903 ; MIPS32: sll [[T0]],[[T0]],0x1f
5904 ; MIPS32: slt [[T10]],[[T10]],[[T0]] 5904 ; MIPS32: slt [[T10]],[[T10]],[[T0]]
5905 ; MIPS32: srl [[T10]],[[T10]],0x18 5905 ; MIPS32: sll [[T10]],[[T10]],0x18
5906 ; MIPS32: sll [[T8]],[[T8]],0x8 5906 ; MIPS32: sll [[T8]],[[T8]],0x8
5907 ; MIPS32: srl [[T8]],[[T8]],0x8 5907 ; MIPS32: srl [[T8]],[[T8]],0x8
5908 ; MIPS32: or [[T10]],[[T10]],[[T8]] 5908 ; MIPS32: or [[T10]],[[T10]],[[T8]]
5909 ; MIPS32: move [[T0]],a1 5909 ; MIPS32: move [[T0]],a1
5910 ; MIPS32: andi [[T0]],[[T0]],0xff 5910 ; MIPS32: andi [[T0]],[[T0]],0xff
5911 ; MIPS32: andi [[T0]],[[T0]],0x1 5911 ; MIPS32: andi [[T0]],[[T0]],0x1
5912 ; MIPS32: move [[T4]],[[T1]] 5912 ; MIPS32: move [[T4]],[[T1]]
5913 ; MIPS32: andi [[T4]],[[T4]],0xff 5913 ; MIPS32: andi [[T4]],[[T4]],0xff
5914 ; MIPS32: andi [[T4]],[[T4]],0x1 5914 ; MIPS32: andi [[T4]],[[T4]],0x1
5915 ; MIPS32: sll [[T0]],[[T0]],0x1f 5915 ; MIPS32: sll [[T0]],[[T0]],0x1f
(...skipping 37 matching lines...) Expand 10 before | Expand all | Expand 10 after
5953 ; MIPS32: ori [[T5]],[[T5]],0xffff 5953 ; MIPS32: ori [[T5]],[[T5]],0xffff
5954 ; MIPS32: and [[T4]],[[T4]],[[T5]] 5954 ; MIPS32: and [[T4]],[[T4]],[[T5]]
5955 ; MIPS32: or [[T0]],[[T0]],[[T4]] 5955 ; MIPS32: or [[T0]],[[T0]],[[T4]]
5956 ; MIPS32: srl [[T11:.*]],a1,0x18 5956 ; MIPS32: srl [[T11:.*]],a1,0x18
5957 ; MIPS32: andi [[T11]],[[T11]],0x1 5957 ; MIPS32: andi [[T11]],[[T11]],0x1
5958 ; MIPS32: srl [[T1]],[[T1]],0x18 5958 ; MIPS32: srl [[T1]],[[T1]],0x18
5959 ; MIPS32: andi [[T1]],[[T1]],0x1 5959 ; MIPS32: andi [[T1]],[[T1]],0x1
5960 ; MIPS32: sll [[T11]],[[T11]],0x1f 5960 ; MIPS32: sll [[T11]],[[T11]],0x1f
5961 ; MIPS32: sll [[T1]],[[T1]],0x1f 5961 ; MIPS32: sll [[T1]],[[T1]],0x1f
5962 ; MIPS32: slt [[T11]],[[T11]],[[T1]] 5962 ; MIPS32: slt [[T11]],[[T11]],[[T1]]
5963 ; MIPS32: srl [[T11]],[[T11]],0x18 5963 ; MIPS32: sll [[T11]],[[T11]],0x18
5964 ; MIPS32: sll [[T0]],[[T0]],0x8 5964 ; MIPS32: sll [[T0]],[[T0]],0x8
5965 ; MIPS32: srl [[T0]],[[T0]],0x8 5965 ; MIPS32: srl [[T0]],[[T0]],0x8
5966 ; MIPS32: or [[T11]],[[T11]],[[T0]] 5966 ; MIPS32: or [[T11]],[[T11]],[[T0]]
5967 ; MIPS32: move [[T0]],a2 5967 ; MIPS32: move [[T0]],a2
5968 ; MIPS32: andi [[T0]],[[T0]],0xff 5968 ; MIPS32: andi [[T0]],[[T0]],0xff
5969 ; MIPS32: andi [[T0]],[[T0]],0x1 5969 ; MIPS32: andi [[T0]],[[T0]],0x1
5970 ; MIPS32: move [[T1]],[[T2]] 5970 ; MIPS32: move [[T1]],[[T2]]
5971 ; MIPS32: andi [[T1]],[[T1]],0xff 5971 ; MIPS32: andi [[T1]],[[T1]],0xff
5972 ; MIPS32: andi [[T1]],[[T1]],0x1 5972 ; MIPS32: andi [[T1]],[[T1]],0x1
5973 ; MIPS32: sll [[T0]],[[T0]],0x1f 5973 ; MIPS32: sll [[T0]],[[T0]],0x1f
(...skipping 37 matching lines...) Expand 10 before | Expand all | Expand 10 after
6011 ; MIPS32: ori [[T4]],[[T4]],0xffff 6011 ; MIPS32: ori [[T4]],[[T4]],0xffff
6012 ; MIPS32: and [[T1]],[[T1]],[[T4]] 6012 ; MIPS32: and [[T1]],[[T1]],[[T4]]
6013 ; MIPS32: or [[T0]],[[T0]],[[T1]] 6013 ; MIPS32: or [[T0]],[[T0]],[[T1]]
6014 ; MIPS32: srl [[T12:.*]],a2,0x18 6014 ; MIPS32: srl [[T12:.*]],a2,0x18
6015 ; MIPS32: andi [[T12]],[[T12]],0x1 6015 ; MIPS32: andi [[T12]],[[T12]],0x1
6016 ; MIPS32: srl [[T2]],[[T2]],0x18 6016 ; MIPS32: srl [[T2]],[[T2]],0x18
6017 ; MIPS32: andi [[T2]],[[T2]],0x1 6017 ; MIPS32: andi [[T2]],[[T2]],0x1
6018 ; MIPS32: sll [[T12]],[[T12]],0x1f 6018 ; MIPS32: sll [[T12]],[[T12]],0x1f
6019 ; MIPS32: sll [[T2]],[[T2]],0x1f 6019 ; MIPS32: sll [[T2]],[[T2]],0x1f
6020 ; MIPS32: slt [[T12]],[[T12]],[[T2]] 6020 ; MIPS32: slt [[T12]],[[T12]],[[T2]]
6021 ; MIPS32: srl [[T12]],[[T12]],0x18 6021 ; MIPS32: sll [[T12]],[[T12]],0x18
6022 ; MIPS32: sll [[T0]],[[T0]],0x8 6022 ; MIPS32: sll [[T0]],[[T0]],0x8
6023 ; MIPS32: srl [[T0]],[[T0]],0x8 6023 ; MIPS32: srl [[T0]],[[T0]],0x8
6024 ; MIPS32: or [[T12]],[[T12]],[[T0]] 6024 ; MIPS32: or [[T12]],[[T12]],[[T0]]
6025 ; MIPS32: move [[T0]],a3 6025 ; MIPS32: move [[T0]],a3
6026 ; MIPS32: andi [[T0]],[[T0]],0xff 6026 ; MIPS32: andi [[T0]],[[T0]],0xff
6027 ; MIPS32: andi [[T0]],[[T0]],0x1 6027 ; MIPS32: andi [[T0]],[[T0]],0x1
6028 ; MIPS32: move [[T1]],[[T3]] 6028 ; MIPS32: move [[T1]],[[T3]]
6029 ; MIPS32: andi [[T1]],[[T1]],0xff 6029 ; MIPS32: andi [[T1]],[[T1]],0xff
6030 ; MIPS32: andi [[T1]],[[T1]],0x1 6030 ; MIPS32: andi [[T1]],[[T1]],0x1
6031 ; MIPS32: sll [[T0]],[[T0]],0x1f 6031 ; MIPS32: sll [[T0]],[[T0]],0x1f
(...skipping 37 matching lines...) Expand 10 before | Expand all | Expand 10 after
6069 ; MIPS32: ori [[T2]],[[T2]],0xffff 6069 ; MIPS32: ori [[T2]],[[T2]],0xffff
6070 ; MIPS32: and [[T1]],[[T1]],[[T2]] 6070 ; MIPS32: and [[T1]],[[T1]],[[T2]]
6071 ; MIPS32: or [[T0]],[[T0]],[[T1]] 6071 ; MIPS32: or [[T0]],[[T0]],[[T1]]
6072 ; MIPS32: srl [[T13:.*]],a3,0x18 6072 ; MIPS32: srl [[T13:.*]],a3,0x18
6073 ; MIPS32: andi [[T13]],[[T13]],0x1 6073 ; MIPS32: andi [[T13]],[[T13]],0x1
6074 ; MIPS32: srl [[T3]],[[T3]],0x18 6074 ; MIPS32: srl [[T3]],[[T3]],0x18
6075 ; MIPS32: andi [[T3]],[[T3]],0x1 6075 ; MIPS32: andi [[T3]],[[T3]],0x1
6076 ; MIPS32: sll [[T13]],[[T13]],0x1f 6076 ; MIPS32: sll [[T13]],[[T13]],0x1f
6077 ; MIPS32: sll [[T3]],[[T3]],0x1f 6077 ; MIPS32: sll [[T3]],[[T3]],0x1f
6078 ; MIPS32: slt [[T13]],[[T13]],[[T3]] 6078 ; MIPS32: slt [[T13]],[[T13]],[[T3]]
6079 ; MIPS32: srl [[T13]],[[T13]],0x18 6079 ; MIPS32: sll [[T13]],[[T13]],0x18
6080 ; MIPS32: sll [[T0]],[[T0]],0x8 6080 ; MIPS32: sll [[T0]],[[T0]],0x8
6081 ; MIPS32: srl [[T0]],[[T0]],0x8 6081 ; MIPS32: srl [[T0]],[[T0]],0x8
6082 ; MIPS32: or [[T13]],[[T13]],[[T0]] 6082 ; MIPS32: or [[T13]],[[T13]],[[T0]]
6083 ; MIPS32: move v0,[[T10]] 6083 ; MIPS32: move v0,[[T10]]
6084 ; MIPS32: move v1,[[T11]] 6084 ; MIPS32: move v1,[[T11]]
6085 ; MIPS32: move a0,[[T12]] 6085 ; MIPS32: move a0,[[T12]]
6086 ; MIPS32: move a1,[[T13]] 6086 ; MIPS32: move a1,[[T13]]
6087 } 6087 }
6088 6088
6089 define internal <16 x i1> @test_icmp_v16i1_uge(<16 x i1> %a, <16 x i1> %b) { 6089 define internal <16 x i1> @test_icmp_v16i1_uge(<16 x i1> %a, <16 x i1> %b) {
(...skipping 65 matching lines...) Expand 10 before | Expand all | Expand 10 after
6155 ; MIPS32: and [[T4]],[[T4]],[[T9]] 6155 ; MIPS32: and [[T4]],[[T4]],[[T9]]
6156 ; MIPS32: or [[T8]],[[T8]],[[T4]] 6156 ; MIPS32: or [[T8]],[[T8]],[[T4]]
6157 ; MIPS32: srl [[T10:.*]],a0,0x18 6157 ; MIPS32: srl [[T10:.*]],a0,0x18
6158 ; MIPS32: andi [[T10]],[[T10]],0x1 6158 ; MIPS32: andi [[T10]],[[T10]],0x1
6159 ; MIPS32: srl [[T0]],[[T0]],0x18 6159 ; MIPS32: srl [[T0]],[[T0]],0x18
6160 ; MIPS32: andi [[T0]],[[T0]],0x1 6160 ; MIPS32: andi [[T0]],[[T0]],0x1
6161 ; MIPS32: sll [[T10]],[[T10]],0x1f 6161 ; MIPS32: sll [[T10]],[[T10]],0x1f
6162 ; MIPS32: sll [[T0]],[[T0]],0x1f 6162 ; MIPS32: sll [[T0]],[[T0]],0x1f
6163 ; MIPS32: sltu [[T10]],[[T10]],[[T0]] 6163 ; MIPS32: sltu [[T10]],[[T10]],[[T0]]
6164 ; MIPS32: xori [[T10]],[[T10]],0x1 6164 ; MIPS32: xori [[T10]],[[T10]],0x1
6165 ; MIPS32: srl [[T10]],[[T10]],0x18 6165 ; MIPS32: sll [[T10]],[[T10]],0x18
6166 ; MIPS32: sll [[T8]],[[T8]],0x8 6166 ; MIPS32: sll [[T8]],[[T8]],0x8
6167 ; MIPS32: srl [[T8]],[[T8]],0x8 6167 ; MIPS32: srl [[T8]],[[T8]],0x8
6168 ; MIPS32: or [[T10]],[[T10]],[[T8]] 6168 ; MIPS32: or [[T10]],[[T10]],[[T8]]
6169 ; MIPS32: move [[T0]],a1 6169 ; MIPS32: move [[T0]],a1
6170 ; MIPS32: andi [[T0]],[[T0]],0xff 6170 ; MIPS32: andi [[T0]],[[T0]],0xff
6171 ; MIPS32: andi [[T0]],[[T0]],0x1 6171 ; MIPS32: andi [[T0]],[[T0]],0x1
6172 ; MIPS32: move [[T4]],[[T1]] 6172 ; MIPS32: move [[T4]],[[T1]]
6173 ; MIPS32: andi [[T4]],[[T4]],0xff 6173 ; MIPS32: andi [[T4]],[[T4]],0xff
6174 ; MIPS32: andi [[T4]],[[T4]],0x1 6174 ; MIPS32: andi [[T4]],[[T4]],0x1
6175 ; MIPS32: sll [[T0]],[[T0]],0x1f 6175 ; MIPS32: sll [[T0]],[[T0]],0x1f
(...skipping 41 matching lines...) Expand 10 before | Expand all | Expand 10 after
6217 ; MIPS32: and [[T4]],[[T4]],[[T5]] 6217 ; MIPS32: and [[T4]],[[T4]],[[T5]]
6218 ; MIPS32: or [[T0]],[[T0]],[[T4]] 6218 ; MIPS32: or [[T0]],[[T0]],[[T4]]
6219 ; MIPS32: srl [[T11:.*]],a1,0x18 6219 ; MIPS32: srl [[T11:.*]],a1,0x18
6220 ; MIPS32: andi [[T11]],[[T11]],0x1 6220 ; MIPS32: andi [[T11]],[[T11]],0x1
6221 ; MIPS32: srl [[T1]],[[T1]],0x18 6221 ; MIPS32: srl [[T1]],[[T1]],0x18
6222 ; MIPS32: andi [[T1]],[[T1]],0x1 6222 ; MIPS32: andi [[T1]],[[T1]],0x1
6223 ; MIPS32: sll [[T11]],[[T11]],0x1f 6223 ; MIPS32: sll [[T11]],[[T11]],0x1f
6224 ; MIPS32: sll [[T1]],[[T1]],0x1f 6224 ; MIPS32: sll [[T1]],[[T1]],0x1f
6225 ; MIPS32: sltu [[T11]],[[T11]],[[T1]] 6225 ; MIPS32: sltu [[T11]],[[T11]],[[T1]]
6226 ; MIPS32: xori [[T11]],[[T11]],0x1 6226 ; MIPS32: xori [[T11]],[[T11]],0x1
6227 ; MIPS32: srl [[T11]],[[T11]],0x18 6227 ; MIPS32: sll [[T11]],[[T11]],0x18
6228 ; MIPS32: sll [[T0]],[[T0]],0x8 6228 ; MIPS32: sll [[T0]],[[T0]],0x8
6229 ; MIPS32: srl [[T0]],[[T0]],0x8 6229 ; MIPS32: srl [[T0]],[[T0]],0x8
6230 ; MIPS32: or [[T11]],[[T11]],[[T0]] 6230 ; MIPS32: or [[T11]],[[T11]],[[T0]]
6231 ; MIPS32: move [[T0]],a2 6231 ; MIPS32: move [[T0]],a2
6232 ; MIPS32: andi [[T0]],[[T0]],0xff 6232 ; MIPS32: andi [[T0]],[[T0]],0xff
6233 ; MIPS32: andi [[T0]],[[T0]],0x1 6233 ; MIPS32: andi [[T0]],[[T0]],0x1
6234 ; MIPS32: move [[T1]],[[T2]] 6234 ; MIPS32: move [[T1]],[[T2]]
6235 ; MIPS32: andi [[T1]],[[T1]],0xff 6235 ; MIPS32: andi [[T1]],[[T1]],0xff
6236 ; MIPS32: andi [[T1]],[[T1]],0x1 6236 ; MIPS32: andi [[T1]],[[T1]],0x1
6237 ; MIPS32: sll [[T0]],[[T0]],0x1f 6237 ; MIPS32: sll [[T0]],[[T0]],0x1f
(...skipping 41 matching lines...) Expand 10 before | Expand all | Expand 10 after
6279 ; MIPS32: and [[T1]],[[T1]],[[T4]] 6279 ; MIPS32: and [[T1]],[[T1]],[[T4]]
6280 ; MIPS32: or [[T0]],[[T0]],[[T1]] 6280 ; MIPS32: or [[T0]],[[T0]],[[T1]]
6281 ; MIPS32: srl [[T12:.*]],a2,0x18 6281 ; MIPS32: srl [[T12:.*]],a2,0x18
6282 ; MIPS32: andi [[T12]],[[T12]],0x1 6282 ; MIPS32: andi [[T12]],[[T12]],0x1
6283 ; MIPS32: srl [[T2]],[[T2]],0x18 6283 ; MIPS32: srl [[T2]],[[T2]],0x18
6284 ; MIPS32: andi [[T2]],[[T2]],0x1 6284 ; MIPS32: andi [[T2]],[[T2]],0x1
6285 ; MIPS32: sll [[T12]],[[T12]],0x1f 6285 ; MIPS32: sll [[T12]],[[T12]],0x1f
6286 ; MIPS32: sll [[T2]],[[T2]],0x1f 6286 ; MIPS32: sll [[T2]],[[T2]],0x1f
6287 ; MIPS32: sltu [[T12]],[[T12]],[[T2]] 6287 ; MIPS32: sltu [[T12]],[[T12]],[[T2]]
6288 ; MIPS32: xori [[T12]],[[T12]],0x1 6288 ; MIPS32: xori [[T12]],[[T12]],0x1
6289 ; MIPS32: srl [[T12]],[[T12]],0x18 6289 ; MIPS32: sll [[T12]],[[T12]],0x18
6290 ; MIPS32: sll [[T0]],[[T0]],0x8 6290 ; MIPS32: sll [[T0]],[[T0]],0x8
6291 ; MIPS32: srl [[T0]],[[T0]],0x8 6291 ; MIPS32: srl [[T0]],[[T0]],0x8
6292 ; MIPS32: or [[T12]],[[T12]],[[T0]] 6292 ; MIPS32: or [[T12]],[[T12]],[[T0]]
6293 ; MIPS32: move [[T0]],a3 6293 ; MIPS32: move [[T0]],a3
6294 ; MIPS32: andi [[T0]],[[T0]],0xff 6294 ; MIPS32: andi [[T0]],[[T0]],0xff
6295 ; MIPS32: andi [[T0]],[[T0]],0x1 6295 ; MIPS32: andi [[T0]],[[T0]],0x1
6296 ; MIPS32: move [[T1]],[[T3]] 6296 ; MIPS32: move [[T1]],[[T3]]
6297 ; MIPS32: andi [[T1]],[[T1]],0xff 6297 ; MIPS32: andi [[T1]],[[T1]],0xff
6298 ; MIPS32: andi [[T1]],[[T1]],0x1 6298 ; MIPS32: andi [[T1]],[[T1]],0x1
6299 ; MIPS32: sll [[T0]],[[T0]],0x1f 6299 ; MIPS32: sll [[T0]],[[T0]],0x1f
(...skipping 41 matching lines...) Expand 10 before | Expand all | Expand 10 after
6341 ; MIPS32: and [[T1]],[[T1]],[[T2]] 6341 ; MIPS32: and [[T1]],[[T1]],[[T2]]
6342 ; MIPS32: or [[T0]],[[T0]],[[T1]] 6342 ; MIPS32: or [[T0]],[[T0]],[[T1]]
6343 ; MIPS32: srl [[T13:.*]],a3,0x18 6343 ; MIPS32: srl [[T13:.*]],a3,0x18
6344 ; MIPS32: andi [[T13]],[[T13]],0x1 6344 ; MIPS32: andi [[T13]],[[T13]],0x1
6345 ; MIPS32: srl [[T3]],[[T3]],0x18 6345 ; MIPS32: srl [[T3]],[[T3]],0x18
6346 ; MIPS32: andi [[T3]],[[T3]],0x1 6346 ; MIPS32: andi [[T3]],[[T3]],0x1
6347 ; MIPS32: sll [[T13]],[[T13]],0x1f 6347 ; MIPS32: sll [[T13]],[[T13]],0x1f
6348 ; MIPS32: sll [[T3]],[[T3]],0x1f 6348 ; MIPS32: sll [[T3]],[[T3]],0x1f
6349 ; MIPS32: sltu [[T13]],[[T13]],[[T3]] 6349 ; MIPS32: sltu [[T13]],[[T13]],[[T3]]
6350 ; MIPS32: xori [[T13]],[[T13]],0x1 6350 ; MIPS32: xori [[T13]],[[T13]],0x1
6351 ; MIPS32: srl [[T13]],[[T13]],0x18 6351 ; MIPS32: sll [[T13]],[[T13]],0x18
6352 ; MIPS32: sll [[T0]],[[T0]],0x8 6352 ; MIPS32: sll [[T0]],[[T0]],0x8
6353 ; MIPS32: srl [[T0]],[[T0]],0x8 6353 ; MIPS32: srl [[T0]],[[T0]],0x8
6354 ; MIPS32: or [[T13]],[[T13]],[[T0]] 6354 ; MIPS32: or [[T13]],[[T13]],[[T0]]
6355 ; MIPS32: move v0,[[T10]] 6355 ; MIPS32: move v0,[[T10]]
6356 ; MIPS32: move v1,[[T11]] 6356 ; MIPS32: move v1,[[T11]]
6357 ; MIPS32: move a0,[[T12]] 6357 ; MIPS32: move a0,[[T12]]
6358 ; MIPS32: move a1,[[T13]] 6358 ; MIPS32: move a1,[[T13]]
6359 } 6359 }
6360 6360
6361 define internal <16 x i1> @test_icmp_v16i1_ugt(<16 x i1> %a, <16 x i1> %b) { 6361 define internal <16 x i1> @test_icmp_v16i1_ugt(<16 x i1> %a, <16 x i1> %b) {
(...skipping 60 matching lines...) Expand 10 before | Expand all | Expand 10 after
6422 ; MIPS32: ori [[T4]],[[T4]],0xffff 6422 ; MIPS32: ori [[T4]],[[T4]],0xffff
6423 ; MIPS32: and [[T8]],[[T8]],[[T4]] 6423 ; MIPS32: and [[T8]],[[T8]],[[T4]]
6424 ; MIPS32: or [[T9]],[[T9]],[[T8]] 6424 ; MIPS32: or [[T9]],[[T9]],[[T8]]
6425 ; MIPS32: srl [[T10:.*]],a0,0x18 6425 ; MIPS32: srl [[T10:.*]],a0,0x18
6426 ; MIPS32: andi [[T10]],[[T10]],0x1 6426 ; MIPS32: andi [[T10]],[[T10]],0x1
6427 ; MIPS32: srl [[T0]],[[T0]],0x18 6427 ; MIPS32: srl [[T0]],[[T0]],0x18
6428 ; MIPS32: andi [[T0]],[[T0]],0x1 6428 ; MIPS32: andi [[T0]],[[T0]],0x1
6429 ; MIPS32: sll [[T10]],[[T10]],0x1f 6429 ; MIPS32: sll [[T10]],[[T10]],0x1f
6430 ; MIPS32: sll [[T0]],[[T0]],0x1f 6430 ; MIPS32: sll [[T0]],[[T0]],0x1f
6431 ; MIPS32: sltu [[T0]],[[T0]],[[T10]] 6431 ; MIPS32: sltu [[T0]],[[T0]],[[T10]]
6432 ; MIPS32: srl [[T0]],[[T0]],0x18 6432 ; MIPS32: sll [[T0]],[[T0]],0x18
6433 ; MIPS32: sll [[T9]],[[T9]],0x8 6433 ; MIPS32: sll [[T9]],[[T9]],0x8
6434 ; MIPS32: srl [[T9]],[[T9]],0x8 6434 ; MIPS32: srl [[T9]],[[T9]],0x8
6435 ; MIPS32: or v0,[[T0]],[[T9]] 6435 ; MIPS32: or v0,[[T0]],[[T9]]
6436 ; MIPS32: move [[T10]],a1 6436 ; MIPS32: move [[T10]],a1
6437 ; MIPS32: andi [[T10]],[[T10]],0xff 6437 ; MIPS32: andi [[T10]],[[T10]],0xff
6438 ; MIPS32: andi [[T10]],[[T10]],0x1 6438 ; MIPS32: andi [[T10]],[[T10]],0x1
6439 ; MIPS32: move [[T4]],[[T1]] 6439 ; MIPS32: move [[T4]],[[T1]]
6440 ; MIPS32: andi [[T4]],[[T4]],0xff 6440 ; MIPS32: andi [[T4]],[[T4]],0xff
6441 ; MIPS32: andi [[T4]],[[T4]],0x1 6441 ; MIPS32: andi [[T4]],[[T4]],0x1
6442 ; MIPS32: sll [[T10]],[[T10]],0x1f 6442 ; MIPS32: sll [[T10]],[[T10]],0x1f
(...skipping 37 matching lines...) Expand 10 before | Expand all | Expand 10 after
6480 ; MIPS32: ori [[T10]],[[T10]],0xffff 6480 ; MIPS32: ori [[T10]],[[T10]],0xffff
6481 ; MIPS32: and [[T5]],[[T5]],[[T10]] 6481 ; MIPS32: and [[T5]],[[T5]],[[T10]]
6482 ; MIPS32: or [[T4]],[[T4]],[[T5]] 6482 ; MIPS32: or [[T4]],[[T4]],[[T5]]
6483 ; MIPS32: srl [[T11:.*]],a1,0x18 6483 ; MIPS32: srl [[T11:.*]],a1,0x18
6484 ; MIPS32: andi [[T11]],[[T11]],0x1 6484 ; MIPS32: andi [[T11]],[[T11]],0x1
6485 ; MIPS32: srl [[T1]],[[T1]],0x18 6485 ; MIPS32: srl [[T1]],[[T1]],0x18
6486 ; MIPS32: andi [[T1]],[[T1]],0x1 6486 ; MIPS32: andi [[T1]],[[T1]],0x1
6487 ; MIPS32: sll [[T11]],[[T11]],0x1f 6487 ; MIPS32: sll [[T11]],[[T11]],0x1f
6488 ; MIPS32: sll [[T1]],[[T1]],0x1f 6488 ; MIPS32: sll [[T1]],[[T1]],0x1f
6489 ; MIPS32: sltu [[T1]],[[T1]],[[T11]] 6489 ; MIPS32: sltu [[T1]],[[T1]],[[T11]]
6490 ; MIPS32: srl [[T1]],[[T1]],0x18 6490 ; MIPS32: sll [[T1]],[[T1]],0x18
6491 ; MIPS32: sll [[T4]],[[T4]],0x8 6491 ; MIPS32: sll [[T4]],[[T4]],0x8
6492 ; MIPS32: srl [[T4]],[[T4]],0x8 6492 ; MIPS32: srl [[T4]],[[T4]],0x8
6493 ; MIPS32: or v1,[[T1]],[[T4]] 6493 ; MIPS32: or v1,[[T1]],[[T4]]
6494 ; MIPS32: move [[T10]],a2 6494 ; MIPS32: move [[T10]],a2
6495 ; MIPS32: andi [[T10]],[[T10]],0xff 6495 ; MIPS32: andi [[T10]],[[T10]],0xff
6496 ; MIPS32: andi [[T10]],[[T10]],0x1 6496 ; MIPS32: andi [[T10]],[[T10]],0x1
6497 ; MIPS32: move [[T11]],[[T2]] 6497 ; MIPS32: move [[T11]],[[T2]]
6498 ; MIPS32: andi [[T11]],[[T11]],0xff 6498 ; MIPS32: andi [[T11]],[[T11]],0xff
6499 ; MIPS32: andi [[T11]],[[T11]],0x1 6499 ; MIPS32: andi [[T11]],[[T11]],0x1
6500 ; MIPS32: sll [[T10]],[[T10]],0x1f 6500 ; MIPS32: sll [[T10]],[[T10]],0x1f
(...skipping 37 matching lines...) Expand 10 before | Expand all | Expand 10 after
6538 ; MIPS32: ori [[T10]],[[T10]],0xffff 6538 ; MIPS32: ori [[T10]],[[T10]],0xffff
6539 ; MIPS32: and [[T4]],[[T4]],[[T10]] 6539 ; MIPS32: and [[T4]],[[T4]],[[T10]]
6540 ; MIPS32: or [[T11]],[[T11]],[[T4]] 6540 ; MIPS32: or [[T11]],[[T11]],[[T4]]
6541 ; MIPS32: srl [[T12:.*]],a2,0x18 6541 ; MIPS32: srl [[T12:.*]],a2,0x18
6542 ; MIPS32: andi [[T12]],[[T12]],0x1 6542 ; MIPS32: andi [[T12]],[[T12]],0x1
6543 ; MIPS32: srl [[T2]],[[T2]],0x18 6543 ; MIPS32: srl [[T2]],[[T2]],0x18
6544 ; MIPS32: andi [[T2]],[[T2]],0x1 6544 ; MIPS32: andi [[T2]],[[T2]],0x1
6545 ; MIPS32: sll [[T12]],[[T12]],0x1f 6545 ; MIPS32: sll [[T12]],[[T12]],0x1f
6546 ; MIPS32: sll [[T2]],[[T2]],0x1f 6546 ; MIPS32: sll [[T2]],[[T2]],0x1f
6547 ; MIPS32: sltu [[T2]],[[T2]],[[T12]] 6547 ; MIPS32: sltu [[T2]],[[T2]],[[T12]]
6548 ; MIPS32: srl [[T2]],[[T2]],0x18 6548 ; MIPS32: sll [[T2]],[[T2]],0x18
6549 ; MIPS32: sll [[T11]],[[T11]],0x8 6549 ; MIPS32: sll [[T11]],[[T11]],0x8
6550 ; MIPS32: srl [[T11]],[[T11]],0x8 6550 ; MIPS32: srl [[T11]],[[T11]],0x8
6551 ; MIPS32: or [[T2]],[[T2]],[[T11]] 6551 ; MIPS32: or [[T2]],[[T2]],[[T11]]
6552 ; MIPS32: move [[T10]],a3 6552 ; MIPS32: move [[T10]],a3
6553 ; MIPS32: andi [[T10]],[[T10]],0xff 6553 ; MIPS32: andi [[T10]],[[T10]],0xff
6554 ; MIPS32: andi [[T10]],[[T10]],0x1 6554 ; MIPS32: andi [[T10]],[[T10]],0x1
6555 ; MIPS32: move [[T11]],[[T3]] 6555 ; MIPS32: move [[T11]],[[T3]]
6556 ; MIPS32: andi [[T11]],[[T11]],0xff 6556 ; MIPS32: andi [[T11]],[[T11]],0xff
6557 ; MIPS32: andi [[T11]],[[T11]],0x1 6557 ; MIPS32: andi [[T11]],[[T11]],0x1
6558 ; MIPS32: sll [[T10]],[[T10]],0x1f 6558 ; MIPS32: sll [[T10]],[[T10]],0x1f
(...skipping 37 matching lines...) Expand 10 before | Expand all | Expand 10 after
6596 ; MIPS32: ori [[T10]],[[T10]],0xffff 6596 ; MIPS32: ori [[T10]],[[T10]],0xffff
6597 ; MIPS32: and [[T12]],[[T12]],[[T10]] 6597 ; MIPS32: and [[T12]],[[T12]],[[T10]]
6598 ; MIPS32: or [[T11]],[[T11]],[[T12]] 6598 ; MIPS32: or [[T11]],[[T11]],[[T12]]
6599 ; MIPS32: srl [[T13:.*]],a3,0x18 6599 ; MIPS32: srl [[T13:.*]],a3,0x18
6600 ; MIPS32: andi [[T13]],[[T13]],0x1 6600 ; MIPS32: andi [[T13]],[[T13]],0x1
6601 ; MIPS32: srl [[T3]],[[T3]],0x18 6601 ; MIPS32: srl [[T3]],[[T3]],0x18
6602 ; MIPS32: andi [[T3]],[[T3]],0x1 6602 ; MIPS32: andi [[T3]],[[T3]],0x1
6603 ; MIPS32: sll [[T13]],[[T13]],0x1f 6603 ; MIPS32: sll [[T13]],[[T13]],0x1f
6604 ; MIPS32: sll [[T3]],[[T3]],0x1f 6604 ; MIPS32: sll [[T3]],[[T3]],0x1f
6605 ; MIPS32: sltu [[T3]],[[T3]],[[T13]] 6605 ; MIPS32: sltu [[T3]],[[T3]],[[T13]]
6606 ; MIPS32: srl [[T3]],[[T3]],0x18 6606 ; MIPS32: sll [[T3]],[[T3]],0x18
6607 ; MIPS32: sll [[T11]],[[T11]],0x8 6607 ; MIPS32: sll [[T11]],[[T11]],0x8
6608 ; MIPS32: srl [[T11]],[[T11]],0x8 6608 ; MIPS32: srl [[T11]],[[T11]],0x8
6609 ; MIPS32: or [[T3]],[[T3]],[[T11]] 6609 ; MIPS32: or [[T3]],[[T3]],[[T11]]
6610 ; MIPS32: move a0,[[T2]] 6610 ; MIPS32: move a0,[[T2]]
6611 ; MIPS32: move a1,[[T3]] 6611 ; MIPS32: move a1,[[T3]]
6612 } 6612 }
6613 6613
6614 define internal <16 x i1> @test_icmp_v16i1_ule(<16 x i1> %a, <16 x i1> %b) { 6614 define internal <16 x i1> @test_icmp_v16i1_ule(<16 x i1> %a, <16 x i1> %b) {
6615 entry: 6615 entry:
6616 %res = icmp ule <16 x i1> %a, %b 6616 %res = icmp ule <16 x i1> %a, %b
(...skipping 63 matching lines...) Expand 10 before | Expand all | Expand 10 after
6680 ; MIPS32: and [[T8]],[[T8]],[[T4]] 6680 ; MIPS32: and [[T8]],[[T8]],[[T4]]
6681 ; MIPS32: or [[T9]],[[T9]],[[T8]] 6681 ; MIPS32: or [[T9]],[[T9]],[[T8]]
6682 ; MIPS32: srl [[T10:.*]],a0,0x18 6682 ; MIPS32: srl [[T10:.*]],a0,0x18
6683 ; MIPS32: andi [[T10]],[[T10]],0x1 6683 ; MIPS32: andi [[T10]],[[T10]],0x1
6684 ; MIPS32: srl [[T0]],[[T0]],0x18 6684 ; MIPS32: srl [[T0]],[[T0]],0x18
6685 ; MIPS32: andi [[T0]],[[T0]],0x1 6685 ; MIPS32: andi [[T0]],[[T0]],0x1
6686 ; MIPS32: sll [[T10]],[[T10]],0x1f 6686 ; MIPS32: sll [[T10]],[[T10]],0x1f
6687 ; MIPS32: sll [[T0]],[[T0]],0x1f 6687 ; MIPS32: sll [[T0]],[[T0]],0x1f
6688 ; MIPS32: sltu [[T0]],[[T0]],[[T10]] 6688 ; MIPS32: sltu [[T0]],[[T0]],[[T10]]
6689 ; MIPS32: xori [[T0]],[[T0]],0x1 6689 ; MIPS32: xori [[T0]],[[T0]],0x1
6690 ; MIPS32: srl [[T0]],[[T0]],0x18 6690 ; MIPS32: sll [[T0]],[[T0]],0x18
6691 ; MIPS32: sll [[T9]],[[T9]],0x8 6691 ; MIPS32: sll [[T9]],[[T9]],0x8
6692 ; MIPS32: srl [[T9]],[[T9]],0x8 6692 ; MIPS32: srl [[T9]],[[T9]],0x8
6693 ; MIPS32: or v0,[[T0]],[[T9]] 6693 ; MIPS32: or v0,[[T0]],[[T9]]
6694 ; MIPS32: move [[T10]],a1 6694 ; MIPS32: move [[T10]],a1
6695 ; MIPS32: andi [[T10]],[[T10]],0xff 6695 ; MIPS32: andi [[T10]],[[T10]],0xff
6696 ; MIPS32: andi [[T10]],[[T10]],0x1 6696 ; MIPS32: andi [[T10]],[[T10]],0x1
6697 ; MIPS32: move [[T4]],[[T1]] 6697 ; MIPS32: move [[T4]],[[T1]]
6698 ; MIPS32: andi [[T4]],[[T4]],0xff 6698 ; MIPS32: andi [[T4]],[[T4]],0xff
6699 ; MIPS32: andi [[T4]],[[T4]],0x1 6699 ; MIPS32: andi [[T4]],[[T4]],0x1
6700 ; MIPS32: sll [[T10]],[[T10]],0x1f 6700 ; MIPS32: sll [[T10]],[[T10]],0x1f
(...skipping 41 matching lines...) Expand 10 before | Expand all | Expand 10 after
6742 ; MIPS32: and [[T5]],[[T5]],[[T10]] 6742 ; MIPS32: and [[T5]],[[T5]],[[T10]]
6743 ; MIPS32: or [[T4]],[[T4]],[[T5]] 6743 ; MIPS32: or [[T4]],[[T4]],[[T5]]
6744 ; MIPS32: srl [[T11:.*]],a1,0x18 6744 ; MIPS32: srl [[T11:.*]],a1,0x18
6745 ; MIPS32: andi [[T11]],[[T11]],0x1 6745 ; MIPS32: andi [[T11]],[[T11]],0x1
6746 ; MIPS32: srl [[T1]],[[T1]],0x18 6746 ; MIPS32: srl [[T1]],[[T1]],0x18
6747 ; MIPS32: andi [[T1]],[[T1]],0x1 6747 ; MIPS32: andi [[T1]],[[T1]],0x1
6748 ; MIPS32: sll [[T11]],[[T11]],0x1f 6748 ; MIPS32: sll [[T11]],[[T11]],0x1f
6749 ; MIPS32: sll [[T1]],[[T1]],0x1f 6749 ; MIPS32: sll [[T1]],[[T1]],0x1f
6750 ; MIPS32: sltu [[T1]],[[T1]],[[T11]] 6750 ; MIPS32: sltu [[T1]],[[T1]],[[T11]]
6751 ; MIPS32: xori [[T1]],[[T1]],0x1 6751 ; MIPS32: xori [[T1]],[[T1]],0x1
6752 ; MIPS32: srl [[T1]],[[T1]],0x18 6752 ; MIPS32: sll [[T1]],[[T1]],0x18
6753 ; MIPS32: sll [[T4]],[[T4]],0x8 6753 ; MIPS32: sll [[T4]],[[T4]],0x8
6754 ; MIPS32: srl [[T4]],[[T4]],0x8 6754 ; MIPS32: srl [[T4]],[[T4]],0x8
6755 ; MIPS32: or v1,[[T1]],[[T4]] 6755 ; MIPS32: or v1,[[T1]],[[T4]]
6756 ; MIPS32: move [[T10]],a2 6756 ; MIPS32: move [[T10]],a2
6757 ; MIPS32: andi [[T10]],[[T10]],0xff 6757 ; MIPS32: andi [[T10]],[[T10]],0xff
6758 ; MIPS32: andi [[T10]],[[T10]],0x1 6758 ; MIPS32: andi [[T10]],[[T10]],0x1
6759 ; MIPS32: move [[T11]],[[T2]] 6759 ; MIPS32: move [[T11]],[[T2]]
6760 ; MIPS32: andi [[T11]],[[T11]],0xff 6760 ; MIPS32: andi [[T11]],[[T11]],0xff
6761 ; MIPS32: andi [[T11]],[[T11]],0x1 6761 ; MIPS32: andi [[T11]],[[T11]],0x1
6762 ; MIPS32: sll [[T10]],[[T10]],0x1f 6762 ; MIPS32: sll [[T10]],[[T10]],0x1f
(...skipping 41 matching lines...) Expand 10 before | Expand all | Expand 10 after
6804 ; MIPS32: and [[T4]],[[T4]],[[T10]] 6804 ; MIPS32: and [[T4]],[[T4]],[[T10]]
6805 ; MIPS32: or [[T11]],[[T11]],[[T4]] 6805 ; MIPS32: or [[T11]],[[T11]],[[T4]]
6806 ; MIPS32: srl [[T12:.*]],a2,0x18 6806 ; MIPS32: srl [[T12:.*]],a2,0x18
6807 ; MIPS32: andi [[T12]],[[T12]],0x1 6807 ; MIPS32: andi [[T12]],[[T12]],0x1
6808 ; MIPS32: srl [[T2]],[[T2]],0x18 6808 ; MIPS32: srl [[T2]],[[T2]],0x18
6809 ; MIPS32: andi [[T2]],[[T2]],0x1 6809 ; MIPS32: andi [[T2]],[[T2]],0x1
6810 ; MIPS32: sll [[T12]],[[T12]],0x1f 6810 ; MIPS32: sll [[T12]],[[T12]],0x1f
6811 ; MIPS32: sll [[T2]],[[T2]],0x1f 6811 ; MIPS32: sll [[T2]],[[T2]],0x1f
6812 ; MIPS32: sltu [[T2]],[[T2]],[[T12]] 6812 ; MIPS32: sltu [[T2]],[[T2]],[[T12]]
6813 ; MIPS32: xori [[T2]],[[T2]],0x1 6813 ; MIPS32: xori [[T2]],[[T2]],0x1
6814 ; MIPS32: srl [[T2]],[[T2]],0x18 6814 ; MIPS32: sll [[T2]],[[T2]],0x18
6815 ; MIPS32: sll [[T11]],[[T11]],0x8 6815 ; MIPS32: sll [[T11]],[[T11]],0x8
6816 ; MIPS32: srl [[T11]],[[T11]],0x8 6816 ; MIPS32: srl [[T11]],[[T11]],0x8
6817 ; MIPS32: or [[T2]],[[T2]],[[T11]] 6817 ; MIPS32: or [[T2]],[[T2]],[[T11]]
6818 ; MIPS32: move [[T10]],a3 6818 ; MIPS32: move [[T10]],a3
6819 ; MIPS32: andi [[T10]],[[T10]],0xff 6819 ; MIPS32: andi [[T10]],[[T10]],0xff
6820 ; MIPS32: andi [[T10]],[[T10]],0x1 6820 ; MIPS32: andi [[T10]],[[T10]],0x1
6821 ; MIPS32: move [[T11]],[[T3]] 6821 ; MIPS32: move [[T11]],[[T3]]
6822 ; MIPS32: andi [[T11]],[[T11]],0xff 6822 ; MIPS32: andi [[T11]],[[T11]],0xff
6823 ; MIPS32: andi [[T11]],[[T11]],0x1 6823 ; MIPS32: andi [[T11]],[[T11]],0x1
6824 ; MIPS32: sll [[T10]],[[T10]],0x1f 6824 ; MIPS32: sll [[T10]],[[T10]],0x1f
(...skipping 41 matching lines...) Expand 10 before | Expand all | Expand 10 after
6866 ; MIPS32: and [[T12]],[[T12]],[[T10]] 6866 ; MIPS32: and [[T12]],[[T12]],[[T10]]
6867 ; MIPS32: or [[T11]],[[T11]],[[T12]] 6867 ; MIPS32: or [[T11]],[[T11]],[[T12]]
6868 ; MIPS32: srl [[T13:.*]],a3,0x18 6868 ; MIPS32: srl [[T13:.*]],a3,0x18
6869 ; MIPS32: andi [[T13]],[[T13]],0x1 6869 ; MIPS32: andi [[T13]],[[T13]],0x1
6870 ; MIPS32: srl [[T3]],[[T3]],0x18 6870 ; MIPS32: srl [[T3]],[[T3]],0x18
6871 ; MIPS32: andi [[T3]],[[T3]],0x1 6871 ; MIPS32: andi [[T3]],[[T3]],0x1
6872 ; MIPS32: sll [[T13]],[[T13]],0x1f 6872 ; MIPS32: sll [[T13]],[[T13]],0x1f
6873 ; MIPS32: sll [[T3]],[[T3]],0x1f 6873 ; MIPS32: sll [[T3]],[[T3]],0x1f
6874 ; MIPS32: sltu [[T3]],[[T3]],[[T13]] 6874 ; MIPS32: sltu [[T3]],[[T3]],[[T13]]
6875 ; MIPS32: xori [[T3]],[[T3]],0x1 6875 ; MIPS32: xori [[T3]],[[T3]],0x1
6876 ; MIPS32: srl [[T3]],[[T3]],0x18 6876 ; MIPS32: sll [[T3]],[[T3]],0x18
6877 ; MIPS32: sll [[T11]],[[T11]],0x8 6877 ; MIPS32: sll [[T11]],[[T11]],0x8
6878 ; MIPS32: srl [[T11]],[[T11]],0x8 6878 ; MIPS32: srl [[T11]],[[T11]],0x8
6879 ; MIPS32: or [[T3]],[[T3]],[[T11]] 6879 ; MIPS32: or [[T3]],[[T3]],[[T11]]
6880 ; MIPS32: move a0,[[T2]] 6880 ; MIPS32: move a0,[[T2]]
6881 ; MIPS32: move a1,[[T3]] 6881 ; MIPS32: move a1,[[T3]]
6882 } 6882 }
6883 6883
6884 define internal <16 x i1> @test_icmp_v16i1_ult(<16 x i1> %a, <16 x i1> %b) { 6884 define internal <16 x i1> @test_icmp_v16i1_ult(<16 x i1> %a, <16 x i1> %b) {
6885 entry: 6885 entry:
6886 %res = icmp ult <16 x i1> %a, %b 6886 %res = icmp ult <16 x i1> %a, %b
(...skipping 58 matching lines...) Expand 10 before | Expand all | Expand 10 after
6945 ; MIPS32: ori [[T9]],[[T9]],0xffff 6945 ; MIPS32: ori [[T9]],[[T9]],0xffff
6946 ; MIPS32: and [[T4]],[[T4]],[[T9]] 6946 ; MIPS32: and [[T4]],[[T4]],[[T9]]
6947 ; MIPS32: or [[T8]],[[T8]],[[T4]] 6947 ; MIPS32: or [[T8]],[[T8]],[[T4]]
6948 ; MIPS32: srl [[T10:.*]],a0,0x18 6948 ; MIPS32: srl [[T10:.*]],a0,0x18
6949 ; MIPS32: andi [[T10]],[[T10]],0x1 6949 ; MIPS32: andi [[T10]],[[T10]],0x1
6950 ; MIPS32: srl [[T0]],[[T0]],0x18 6950 ; MIPS32: srl [[T0]],[[T0]],0x18
6951 ; MIPS32: andi [[T0]],[[T0]],0x1 6951 ; MIPS32: andi [[T0]],[[T0]],0x1
6952 ; MIPS32: sll [[T10]],[[T10]],0x1f 6952 ; MIPS32: sll [[T10]],[[T10]],0x1f
6953 ; MIPS32: sll [[T0]],[[T0]],0x1f 6953 ; MIPS32: sll [[T0]],[[T0]],0x1f
6954 ; MIPS32: sltu [[T10]],[[T10]],[[T0]] 6954 ; MIPS32: sltu [[T10]],[[T10]],[[T0]]
6955 ; MIPS32: srl [[T10]],[[T10]],0x18 6955 ; MIPS32: sll [[T10]],[[T10]],0x18
6956 ; MIPS32: sll [[T8]],[[T8]],0x8 6956 ; MIPS32: sll [[T8]],[[T8]],0x8
6957 ; MIPS32: srl [[T8]],[[T8]],0x8 6957 ; MIPS32: srl [[T8]],[[T8]],0x8
6958 ; MIPS32: or [[T10]],[[T10]],[[T8]] 6958 ; MIPS32: or [[T10]],[[T10]],[[T8]]
6959 ; MIPS32: move [[T0]],a1 6959 ; MIPS32: move [[T0]],a1
6960 ; MIPS32: andi [[T0]],[[T0]],0xff 6960 ; MIPS32: andi [[T0]],[[T0]],0xff
6961 ; MIPS32: andi [[T0]],[[T0]],0x1 6961 ; MIPS32: andi [[T0]],[[T0]],0x1
6962 ; MIPS32: move [[T4]],[[T1]] 6962 ; MIPS32: move [[T4]],[[T1]]
6963 ; MIPS32: andi [[T4]],[[T4]],0xff 6963 ; MIPS32: andi [[T4]],[[T4]],0xff
6964 ; MIPS32: andi [[T4]],[[T4]],0x1 6964 ; MIPS32: andi [[T4]],[[T4]],0x1
6965 ; MIPS32: sll [[T0]],[[T0]],0x1f 6965 ; MIPS32: sll [[T0]],[[T0]],0x1f
(...skipping 37 matching lines...) Expand 10 before | Expand all | Expand 10 after
7003 ; MIPS32: ori [[T5]],[[T5]],0xffff 7003 ; MIPS32: ori [[T5]],[[T5]],0xffff
7004 ; MIPS32: and [[T4]],[[T4]],[[T5]] 7004 ; MIPS32: and [[T4]],[[T4]],[[T5]]
7005 ; MIPS32: or [[T0]],[[T0]],[[T4]] 7005 ; MIPS32: or [[T0]],[[T0]],[[T4]]
7006 ; MIPS32: srl [[T11:.*]],a1,0x18 7006 ; MIPS32: srl [[T11:.*]],a1,0x18
7007 ; MIPS32: andi [[T11]],[[T11]],0x1 7007 ; MIPS32: andi [[T11]],[[T11]],0x1
7008 ; MIPS32: srl [[T1]],[[T1]],0x18 7008 ; MIPS32: srl [[T1]],[[T1]],0x18
7009 ; MIPS32: andi [[T1]],[[T1]],0x1 7009 ; MIPS32: andi [[T1]],[[T1]],0x1
7010 ; MIPS32: sll [[T11]],[[T11]],0x1f 7010 ; MIPS32: sll [[T11]],[[T11]],0x1f
7011 ; MIPS32: sll [[T1]],[[T1]],0x1f 7011 ; MIPS32: sll [[T1]],[[T1]],0x1f
7012 ; MIPS32: sltu [[T11]],[[T11]],[[T1]] 7012 ; MIPS32: sltu [[T11]],[[T11]],[[T1]]
7013 ; MIPS32: srl [[T11]],[[T11]],0x18 7013 ; MIPS32: sll [[T11]],[[T11]],0x18
7014 ; MIPS32: sll [[T0]],[[T0]],0x8 7014 ; MIPS32: sll [[T0]],[[T0]],0x8
7015 ; MIPS32: srl [[T0]],[[T0]],0x8 7015 ; MIPS32: srl [[T0]],[[T0]],0x8
7016 ; MIPS32: or [[T11]],[[T11]],[[T0]] 7016 ; MIPS32: or [[T11]],[[T11]],[[T0]]
7017 ; MIPS32: move [[T0]],a2 7017 ; MIPS32: move [[T0]],a2
7018 ; MIPS32: andi [[T0]],[[T0]],0xff 7018 ; MIPS32: andi [[T0]],[[T0]],0xff
7019 ; MIPS32: andi [[T0]],[[T0]],0x1 7019 ; MIPS32: andi [[T0]],[[T0]],0x1
7020 ; MIPS32: move [[T1]],[[T2]] 7020 ; MIPS32: move [[T1]],[[T2]]
7021 ; MIPS32: andi [[T1]],[[T1]],0xff 7021 ; MIPS32: andi [[T1]],[[T1]],0xff
7022 ; MIPS32: andi [[T1]],[[T1]],0x1 7022 ; MIPS32: andi [[T1]],[[T1]],0x1
7023 ; MIPS32: sll [[T0]],[[T0]],0x1f 7023 ; MIPS32: sll [[T0]],[[T0]],0x1f
(...skipping 37 matching lines...) Expand 10 before | Expand all | Expand 10 after
7061 ; MIPS32: ori [[T4]],[[T4]],0xffff 7061 ; MIPS32: ori [[T4]],[[T4]],0xffff
7062 ; MIPS32: and [[T1]],[[T1]],[[T4]] 7062 ; MIPS32: and [[T1]],[[T1]],[[T4]]
7063 ; MIPS32: or [[T0]],[[T0]],[[T1]] 7063 ; MIPS32: or [[T0]],[[T0]],[[T1]]
7064 ; MIPS32: srl [[T12:.*]],a2,0x18 7064 ; MIPS32: srl [[T12:.*]],a2,0x18
7065 ; MIPS32: andi [[T12]],[[T12]],0x1 7065 ; MIPS32: andi [[T12]],[[T12]],0x1
7066 ; MIPS32: srl [[T2]],[[T2]],0x18 7066 ; MIPS32: srl [[T2]],[[T2]],0x18
7067 ; MIPS32: andi [[T2]],[[T2]],0x1 7067 ; MIPS32: andi [[T2]],[[T2]],0x1
7068 ; MIPS32: sll [[T12]],[[T12]],0x1f 7068 ; MIPS32: sll [[T12]],[[T12]],0x1f
7069 ; MIPS32: sll [[T2]],[[T2]],0x1f 7069 ; MIPS32: sll [[T2]],[[T2]],0x1f
7070 ; MIPS32: sltu [[T12]],[[T12]],[[T2]] 7070 ; MIPS32: sltu [[T12]],[[T12]],[[T2]]
7071 ; MIPS32: srl [[T12]],[[T12]],0x18 7071 ; MIPS32: sll [[T12]],[[T12]],0x18
7072 ; MIPS32: sll [[T0]],[[T0]],0x8 7072 ; MIPS32: sll [[T0]],[[T0]],0x8
7073 ; MIPS32: srl [[T0]],[[T0]],0x8 7073 ; MIPS32: srl [[T0]],[[T0]],0x8
7074 ; MIPS32: or [[T12]],[[T12]],[[T0]] 7074 ; MIPS32: or [[T12]],[[T12]],[[T0]]
7075 ; MIPS32: move [[T0]],a3 7075 ; MIPS32: move [[T0]],a3
7076 ; MIPS32: andi [[T0]],[[T0]],0xff 7076 ; MIPS32: andi [[T0]],[[T0]],0xff
7077 ; MIPS32: andi [[T0]],[[T0]],0x1 7077 ; MIPS32: andi [[T0]],[[T0]],0x1
7078 ; MIPS32: move [[T1]],[[T3]] 7078 ; MIPS32: move [[T1]],[[T3]]
7079 ; MIPS32: andi [[T1]],[[T1]],0xff 7079 ; MIPS32: andi [[T1]],[[T1]],0xff
7080 ; MIPS32: andi [[T1]],[[T1]],0x1 7080 ; MIPS32: andi [[T1]],[[T1]],0x1
7081 ; MIPS32: sll [[T0]],[[T0]],0x1f 7081 ; MIPS32: sll [[T0]],[[T0]],0x1f
(...skipping 37 matching lines...) Expand 10 before | Expand all | Expand 10 after
7119 ; MIPS32: ori [[T2]],[[T2]],0xffff 7119 ; MIPS32: ori [[T2]],[[T2]],0xffff
7120 ; MIPS32: and [[T1]],[[T1]],[[T2]] 7120 ; MIPS32: and [[T1]],[[T1]],[[T2]]
7121 ; MIPS32: or [[T0]],[[T0]],[[T1]] 7121 ; MIPS32: or [[T0]],[[T0]],[[T1]]
7122 ; MIPS32: srl [[T13:.*]],a3,0x18 7122 ; MIPS32: srl [[T13:.*]],a3,0x18
7123 ; MIPS32: andi [[T13]],[[T13]],0x1 7123 ; MIPS32: andi [[T13]],[[T13]],0x1
7124 ; MIPS32: srl [[T3]],[[T3]],0x18 7124 ; MIPS32: srl [[T3]],[[T3]],0x18
7125 ; MIPS32: andi [[T3]],[[T3]],0x1 7125 ; MIPS32: andi [[T3]],[[T3]],0x1
7126 ; MIPS32: sll [[T13]],[[T13]],0x1f 7126 ; MIPS32: sll [[T13]],[[T13]],0x1f
7127 ; MIPS32: sll [[T3]],[[T3]],0x1f 7127 ; MIPS32: sll [[T3]],[[T3]],0x1f
7128 ; MIPS32: sltu [[T13]],[[T13]],[[T3]] 7128 ; MIPS32: sltu [[T13]],[[T13]],[[T3]]
7129 ; MIPS32: srl [[T13]],[[T13]],0x18 7129 ; MIPS32: sll [[T13]],[[T13]],0x18
7130 ; MIPS32: sll [[T0]],[[T0]],0x8 7130 ; MIPS32: sll [[T0]],[[T0]],0x8
7131 ; MIPS32: srl [[T0]],[[T0]],0x8 7131 ; MIPS32: srl [[T0]],[[T0]],0x8
7132 ; MIPS32: or [[T13]],[[T13]],[[T0]] 7132 ; MIPS32: or [[T13]],[[T13]],[[T0]]
7133 ; MIPS32: move v0,[[T10]] 7133 ; MIPS32: move v0,[[T10]]
7134 ; MIPS32: move v1,[[T11]] 7134 ; MIPS32: move v1,[[T11]]
7135 ; MIPS32: move a0,[[T12]] 7135 ; MIPS32: move a0,[[T12]]
7136 ; MIPS32: move a1,[[T13]] 7136 ; MIPS32: move a1,[[T13]]
7137 } 7137 }
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